JPH0759153B2 - Inverter control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a full-bridge type inverter control circuit.

BACKGROUND ART Conventionally, there is an inverter of this type shown in FIG. This inverter is an N-channel MOSFET (hereinafter simply referred to as
A so-called full-bridge type inverter using a called a FET) as switching elements, FETs Q _1, Q to a DC power source Vin
₂ and FETQ ₃ and Q ₄ are connected in parallel, and a load L such as a motor is connected between the connection point of FETQ ₁ and Q _{2 and} the connection point of FETQ ₃ and Q ₄ , respectively. FET Q ₁ , Q ₄ and FET Q ₂ , Q ₃ which are pairs of ₁ and Q ₄ and FET Q ₂ and Q ₃ are alternately turned on and off for each pair, and load L is indicated by arrows a and The alternating current shown in FIG. The above FETQ
_{1 to} Q ₄ are switched based on the output of the control circuit 1. The control circuit 1 is configured to alternately turn on / off the FETs Q _{1 to} Q ₄ by the input signals v ₁ and v ₂ which are logic signals whose phases are opposite to each other. Switching control is performed for each FET Q _{1 to} Q ₄ . The control circuit 1 _1, with one ₄ input signal v ₁ is input, the control circuit 1 _2, 1 ₃ to the input signal v ₂ is input. Also, the respective input signals v ₁ , v ₂
Is a control circuit via photocouplers PC _{11 to} PC ₁₄ and transistors Q _{51 to} Q ₅₄ for amplifying the outputs of the photocouplers PC _{11 to} PC _14.
1 _1, 1 while being respectively input to _4, the transistors Q ₅₁ ~
The output of Q ₅₄ is inverted by transistors Q _{61 to} Q ₆₄ , respectively, and the current is amplified by the complementary connected transistors Q _{71 to} Q ₇₄ , Q _{81 to} Q ₈₄ , which act as buffers, and the FETs Q ₁ to
Supplied to the gate of Q ₄ . The control circuit 1 ₁ to 1 _4, the power supply through a float-type power supply unit 2 is supplied.

The operation of this conventional circuit will be described. Note that the transistor
The operations of Q ₁ and Q ₄ and the transistors Q ₂ and Q ₃ are the same, so the operation of the transistors Q ₁ and Q ₂ will be described here. Now, assuming that the input signal v ₁ is at high level, the input signal v ₂ is at low level. In this case, the input signal v ₁ is input to the control circuit 1 ₁ via a photocoupler PC _11, since the base current of the transistor Q ₆₁ in the transistor Q ₅₁ is bypassed, the transistor Q ₆₁ is turned off and the transistor Q ₇₁ is Turned on. Therefore, the output of the float type power supply unit 2 is supplied to the gate of the FET Q ₁ via the transistor Q _71, and the FET Q ₁ becomes conductive. On the other hand, in the control circuit 1 ₂ the input signal v
_{Since 2} is low, transistor Q ₆₂ conducts,
Since the transistor Q ₈₂ is turned on, the gate and source of the FET Q ₂ are short-circuited and the FET Q ₂ is turned off. Therefore, in this state, FETs Q ₁ and Q ₄ are turned on, and DC power supply Vi
A current flows through the load L in the direction of arrow a due to n. Also,
When the input signal v ₁ is at the low level and the input signal v ₂ is at the high level, this time the FET Q ₂ and Q ₃ are operated in the reverse operation of the above case.
Is turned on and FETs Q ₁ and Q ₄ are turned off, so that the current flows in the direction of arrow B.

By the way, in this type of inverter, photo coupler PC ₁₁ ~
Input signals v ₁ , v ₂ due to signal transmission delay of PC _14, etc.
There is a risk that all FETs Q _{1 to} Q ₄ will be turned on when inverting. Therefore, normally, as shown in FIG.
Both v ₁ and v ₂ have a dead time td that becomes a low level. That is, if both FETQ ₁ , Q ₂ and FETQ ₃ , Q _{4 are} turned on at the same time, the DC power supply Vi will be applied to FETQ ₁ , Q ₂ and FETQ ₃ , Q ₄ .
This is because the n output will be short-circuited, and a large current will flow through the FETs Q _{1 to} Q ₄ , causing damage.

The above is the description of the conventional inverter control circuit.
In this inverter, photocouplers PC _{11 to} PC for each FET Q _{1 to} Q ₄
Due to the use of substantially control circuit 1 ₁ to 1 ₄ of the same structure made of _14, many number of complex circuit components circuit configuration, there Therefore the cost problem.

[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide an inverter control circuit that can simplify the circuit configuration and reduce the cost. .

DISCLOSURE OF THE INVENTION (Structure) The present invention connects two series circuits in which two MOSFETs are connected in series to a DC power source in parallel, and connects a load between the connection points of the MOSFETs in each series circuit. In a full-bridge type inverter that turns on and off each pair of MOSFETs in a diagonal position and turns each pair of MOSFETs alternately to pass AC current to the load, the gates of both MOSFETs on the positive side of the DC power supply The control voltage obtained from the DC power supply is applied via the first resistor to the float power supply, and the control voltage of the float power supply is connected between the gate and the source of each MOSFET on the positive side, and the control voltage is always applied to the control terminal. A pair of switching elements that are on-controlled, and each of the negative electrode side that is a diagonal position with respect to each positive electrode side MOSFET to which each switching element is connected.
A pair of first diodes that are connected between the drain of the MOSFET and the control terminals of the switching elements with the MOSFETs on the negative side serving as cathodes and turn off the switching elements by turning on the MOSFETs on the negative side. And a control means consisting of, and applies an input signal to the gate of each MOSFET on the negative side through a second resistor, and a pair of gates of each MOSFET on the negative side is used as an anode between both ends of each second resistor. It is characterized in that the second diodes are respectively connected.

Since the above configuration is adopted, the MOSF on the negative side of the DC power supply
The ET is directly switched by the input signal input via the second resistor. Also, the MOSFET on the positive side of the DC power supply is
Normally, the switching element is turned off by being on-controlled, but when the MOSFET on the negative electrode side in the diagonal position is turned on, the switching element is turned off through the first diode and turned on. In other words, the negative side MO
When one of the SFETs is turned on, the MOSFET on the positive side in the diagonal position is turned on after that.

Further, the input signal is input to the gate of the MOSFET on the negative side via the second resistor, and the second diode is connected in parallel to the second resistor with the anode connected to the gate of the MOSFET. , If there is an input signal, through the second resistor
Charges the gate capacitance of the MOSFET (capacitance component between the source and gate), and if there is no input signal, MO
The charge is discharged from the gate capacitance of the SFET, and as a result, the charge time and the discharge time of the gate capacitance of the MOSFET are different. In other words, the time delay from the rise of the input signal to the turning on of the MOSFET is larger than the time delay from the fall of the input signal to the turning off of the MOSFET. If the input signal is alternately applied to each MOSFET, the MOSFET whose input signal falls is turned off and then the MOSFET whose input signal rises is turned on with a delay. In other words, it is possible to prevent the negative-side MOSFETs from turning on at the same time without providing a dead time for the input signal.

As described above, the positive-side MOSFET connected in series to the negative-side MOSFET is immediately turned off following the turning-off of the diagonal negative-side MOSFET, so that both negative-side MOSFETs are turned on at the same time. Otherwise, the negative-side MOSFET and the positive-side MOSFET connected in series with each other are prevented from being turned on at the same time. Furthermore, regarding the MOSFET on the positive side,
Since the first resistor is inserted in the power supply path from the float power supply to the gate capacitance and only the switching element is inserted in the discharge path of the gate capacitance, the diagonal position after the MOSFET on the negative side is turned on. There is a time delay until the MOSFET on the positive side of the device turns on.
When the SFET turns on, the other negative-side MOSFET is surely turned off.Therefore, the positive-side MOSFET is further delayed to turn on, and the negative-side MOSFET connected in series with the negative-side MOSFET. It is possible to more reliably prevent the MOSFET on the positive electrode side from being turned on at the same time.

As is clear from the above description, since it is only necessary to apply the input signal to the negative-side MOSFET and it is not necessary to provide the dead time for the input signal, the control circuit has a simple configuration, which leads to cost reduction. is there.

(Embodiment) FIG. 1 shows an embodiment of the present invention. In the inverter of this embodiment, the input signals v ₁ and v ₂ are fed to the negative side FETs Q ₂ and Q _{4 of the} DC power source Vin.
Type directly to, Yes and to perform the switching of the FETs Q _2, Q _4, a float supply PS _1, PS ₃ to obtain a control voltage for FETs Q _1, Q ₃ from the DC power supply Vin, the DC power source Vin In accordance with the switching of the FETs Q ₂ and Q ₄ on the negative side of, the control circuits 1 ₁ and 1 _{3 including} control means for controlling the application of the control voltage to the FETs Q ₁ and Q ₃ by the float power supplies PS ₁ and PS ₃ The FETs Q ₁ and Q ₃ on the positive side of the power supply Vin are switched.

The configuration of this embodiment will be specifically described below. The input signals v ₁ and v ₂ are logic signals whose phases are opposite to each other, and the input signals v ₁ and v ₂ are connected to the diode D ₂₂ and the resistor R _42.
Further, it is directly input to the FETs Q ₂ and Q ₄ on the negative side of the DC power supply Vin via the diode D ₂₄ and the resistor R ₄₄ , respectively. Float power
PS ₁ and PS ₃ outputs are connected to the gates of FETs Q ₁ and Q ₂ via resistors R ₁₁ and R _{13, respectively,} and transistors Q ₉₁ and Q ₉₃ are connected between the gate and source of FETs Q ₁ and Q ₃ , respectively. ing. Bias resistors R ₂₁ and R _{23 for} biasing the outputs of the float power supplies PS ₁ and PS ₃ are connected to the bases of the transistors Q ₉₁ and Q _{93, respectively, and} the base of the transistor Q ₉₁ is a resistor R ₃₁ and a diode D. _It is connected to the connection point of FETs Q ₃ and Q ₄ via a series circuit with _11, and the base of transistor Q ₉₃ is resistor R ₃₃ and diode D 3.
It is connected to the connection point of FETs Q ₁ and Q ₂ via a series circuit with ₁₃ .

The operation of this embodiment will be described below. Now, assuming that the input signal v ₁ is high level and the input signal v ₂ is low level, the FET Q ₂ is turned on. When the FET Q ₂ is turned on, the base current of the transistor Q ₉₃ is changed to the resistor R ₃₃ , the diode D ₁₃ and the FE.
Bypassing through TQ ₂ and turning off transistor Q ₉₃ , the float power supply PS ₃ output is connected through resistor R ₁₃ to FET Q ₃
It is input to the gate of and FETQ ₃ turns on. On the other hand, the FET Q ₄ is turned off because the input signal v ₂ is at the low level, so that the output of the float power supply PS ₁ is applied to the base of the transistor Q ₉₁ via the bias resistor R ₂₁ and the transistor Q ₉₁ is turned on. Therefore, the output of the float power supply PS ₁ is not applied to the gate of the FET Q ₁ , and the FET Q ₁ is turned off. So in this case F
Since ETQ ₂ and Q ₃ are on and FETs Q ₁ and Q ₄ are off, a current in the direction of arrow a in the figure flows through the load L at the DC power supply Vin. When the input signals v ₁ and v ₂ are inverted, on the contrary, the FETs Q ₁ and Q ₄ are turned on, the FETs Q ₂ and Q ₃ are turned off, and a current flows in the load L in the direction of arrow B in the figure. Thus, according to this embodiment, the DC power supply
The FETs Q ₂ and Q ₄ on the negative side of Vin switch by directly applying the input signals v ₁ and v _2, and the FETs Q ₁ and Q ₃ on the positive side of the DC power supply Vin are FETs.
Since the control means controls the switching according to the switching state of Q ₂ and Q _4, the FET Q
₁ to Q ₄ is not necessary to provide the control circuit 1 ₁ to 1 ₄ of the same structure for each, it is possible to simplify the configuration of the control circuit, thereby making it possible to reduce the cost.

By the way, in this embodiment, as a switching element
The use of MOSFETs Q _{1 to} Q ₄ has the following advantages. That is, the FETs Q ₁ and Q ₃ are connected to the resistors R ₁₁ and R ₁₃ from the float power supplies PS ₁ and PS ₃ , respectively.
Gate voltage is applied through, and the FETs Q _2, Q ₄ resistance
The input signals v ₁ and v ₂ are applied via R ₄₂ and R ₄₄ , respectively.If the FETs Q _{1 to} Q ₄ are of the MOS type, the FETs Q _{1 to} Q ₄ have gate capacitances, and therefore the resistances By appropriately selecting the resistance values of R ₁₁ , R ₁₃ and resistors R ₄₂ , R ₄₄ , it is possible to delay the turn-on time of FETs Q _{1 to} Q ₄ , and turn off FETs Q ₁ , Q ₃ by using transistor Q _91. , Q ₉₃ , the charge stored in the gate capacitances of the FETs Q ₁ and Q ₃ is rapidly discharged, and the FETs Q ₂ and Q ₄ are turned off by the diodes R ₂₂ and D ₂₄ . _42, by bypassing the R ₄₄ to discharge the charged electric charge of the gate capacitance, are then similarly quickly. Therefore, by providing the difference between the time constants of the gate charge path and the discharge path of each MOSFET as described above, it is not necessary to provide the dead time td as shown in FIG. 3 in the input signals v ₁ and v _2. , Therefore it is not necessary to provide a circuit such as a timer circuit for providing the dead time td in front of the control circuit 1 ₁ to 1 _4, further Hakare be simplified control circuit, it is possible to further reduce the cost.

[Effects of the Invention] As described above, the present invention connects two series circuits in which two MOSFETs are connected in series to a DC power source in parallel, and connects a load between the connection points of the MOSFETs in each series circuit, In diagonal positions
In a full-bridge type inverter, in which MOSFETs are paired to turn on and off each pair of MOSFETs alternately to pass AC current to the load, both MOSFs on the positive side of the DC power supply
It is connected between the gate and source of each MOSFET on the positive side and the float power supply that applies the control voltage obtained from the DC power supply to the gate of ET via the first resistor, and the control voltage of the float power supply is applied to the control terminal. By doing so, a pair of switching elements that are always on-controlled, the drains of the MOSFETs on the negative side that are diagonally opposite to the MOSFETs on the positive side to which the switching elements are connected, and the control terminals of the switching elements And a pair of first MOSFETs that are connected to each other with the respective MOSFETs on the negative electrode side serving as cathodes and turn off the respective switching elements by turning on the respective MOSFETs on the negative electrode side.
Each diode on the negative side is equipped with a control means consisting of
An input signal is applied to the gate of the SFET through each second resistor, and each negative-side MOSF is placed between both ends of each second resistor.
A pair of second diodes are connected to each other with the gate side of ET as the anode, and the gate capacitance of each MOSFET on the negative side is charged by the input signal via the second resistor and connected in parallel to the second resistor. Since it is discharged through the discharged second diode, the time from the rising edge of the input signal to the turning on is longer than the time from the falling edge of the input signal to the turning off. It is possible to operate such that one MOSFET is turned off and the other MOSFET is turned on only by applying an input signal that becomes to both negative side MOSFETs. Both MOs on the positive side
The same applies to the SFET. The first resistance is inserted in the charge path from the float power supply to the gate capacitance, and the switching element is only inserted in the discharge path of the gate capacitance. From turning off the switching element rather than the time from turning off to the MOSFET
It takes longer to turn on the MOSFET. Since the switching element for controlling each MOSFET on the positive electrode side is connected to the MOSFET on the negative electrode side in the diagonal position via the first diode, each MOSFET on the positive electrode side is connected to the negative side MOSFET in the diagonal position. Since the MOSFETs are turned on and off following the turning on and off, it is surely prevented that the negative-side MOSFET and the positive-side MOSFET connected in series with each other are simultaneously turned on.

By the operation described above, it suffices to apply the input signal only to the negative-side MOSFET, and there is no need to provide a dead time in the input signal. Therefore, the control circuit has a simple configuration,
This has the effect of reducing costs. In addition, the first diode can prevent the counter electromotive voltage generated at the time of switching the load from being applied to the control circuit that generates the input signal or the gate of the MOSFET, and prevents the breakdown due to the counter electromotive voltage. There is also the effect of

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional example, and FIG. 3 is an explanatory diagram showing input signals of the same. 1 ₁ to 1 ₄ control circuit, Q ₁ to Q ₄ are FET, PS _1, PS ₃ float power, Q _91, Q ₉₃ are _{transistors, D 11, D 13, D} 22, D 24 diodes, R ₁₁ , R ₁₃ , R ₄₂ , R ₄₄ are resistors, v ₁ , v ₂ are input signals, Vin
Is a DC power supply, and L is a load.

Claims (1)

[Claims] 1. A series circuit in which two MOSFETs are connected in series to a DC power source are connected in parallel, and the MOSFETs in each series circuit are connected.
In a full-bridge type inverter, in which a load is connected between the connection points, diagonally-positioned MOSFETs are grouped, and each paired MOSFET is alternately turned on and off to pass an alternating current to the load, Control of the float power supply that is connected between the gate and source of each MOSFET on the positive side and the float power supply that applies the control voltage obtained from the DC power source to the gates of both MOSFETs on the positive side of the DC power source via the first resistor. A pair of switching elements that are always turned on by applying a voltage to the control terminal, and a drain of each negative-side MOSFET that is diagonally opposite to each positive-side MOSFET to which each switching element is connected. One of the switching elements is connected to the control terminal of each of the switching elements with each MOSFET on the negative electrode side serving as a cathode, and each of the switching elements is turned off by turning on each MOSFET on the negative electrode side. And a control means including a first diode of the above, and an input signal is applied to the gate of each MOSFET on the negative side through a second resistor, and the gate side of each MOSFET on the negative side is provided between both ends of each second resistor. A control circuit for an inverter, characterized in that a pair of second diodes are connected to each as an anode.