JPH0760170B2 - IC tester signal output circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal output circuit of an IC tester, and more particularly to a conventional signal correction circuit that corrects the phase of a signal given to a device under test (DUT) from each pin. The present invention relates to an improvement of a skew correction circuit that can reduce the influence of the phase difference on the inspection result.

[Prior Art] A tester such as an LSI is provided with a driver that applies a signal of a predetermined waveform to each pin or to some pins, but each pin has the same output waveform generation timing. Each driver is provided with a skew correction circuit. If no skew correction means is taken, usually, a phase shift, that is, a skew occurs for each pin due to the influence of variations in the characteristics of the circuit and the elements used.

If this skew is left as it is, it also affects the inspection result of the test element by the tester. Therefore, the skew correction circuit minimizes the amount of skew between the pins.

The circuit of an IC tester that generates an output waveform for a certain pin can be roughly divided into a waveform pattern generating section, a timing generating section, and a pin electronics section including a waveform formatter and a driver, as shown in FIG. As described above, there is a phase difference between two output signal waveforms supplied from different pin electronics in which different driver circuits are mounted. Considering the case where there is a time lag of 1 ns in the position of the same phase (midpoint of the signal amplitude), this is due to skew correction in the driver 8 of the driver circuit in the pin electronics, as shown in FIG. If the circuit 7 is placed in front and the correction circuit 7 delays the input signal waveform on the circuit side by 1 ns, the phases of both are made equal and the skew can be corrected. That is,
In this case, the correction circuit 7 of the circuit is the correction circuit 7 of the circuit.
Is set to delay by 1 ns.
It should be noted that this is an example of two circuits, but in reality, such a delay is an output waveform having the longest delay time as a value for correcting skew values by measuring skew values corresponding to the respective pins. The phase correction amount is sequentially added as a delay time to the correction circuit 7 in front of each driver in accordance with the above.

[Problems to be Solved by the Invention] However, in the conventional skew correction circuit, the amplitude of the input signal is considered to be the same for the time being, the amplitude is ignored, and the skew correction is performed regardless of this. Therefore, as shown in FIG. 2, when the amplitudes of the signals to be corrected are the same, the correction can be surely performed as desired, but the rate of change in the signal waveform with time (rise or fall) is the same. However, when the amplitudes of the signal waveforms are different from each other, for example, for signals having different amplitudes as shown in FIG. 4, it is not possible to determine the delay amount in different amplitude relationships as described above. I didn't.

Conventionally, a delay amount for skew correction is set at a specific amplitude, so there is a slight difference in the rise timing between the phase-adjusted specific amplitude and a different signal. Affects tester inspection performance.

This is because even if the rise times of the two signals are coincident with each other due to the skew correction, there is a difference in the time until the two signals rise to the midpoint of the amplitude of the signal waveform. From the viewpoint of the tester, there is a phase difference corresponding to the time difference.

By the way, here, focusing on the midpoint, first, in the operation of the device under test in digital processing, each input voltage does not matter, but the logic level of the input signal is H level. It is important to be in the state of L or the state of L. This is because if the timings of reaching the H and L levels are as uniform as possible, the voltage values in the H and L states do not cause much problems.

Next, the slope of the output signal is raised to its limit because each circuit operates so as to maintain the slew rate as high as possible. Because of this, it is not possible to freely change the slope of rising and falling. In FIG. 4, the output waveform is drawn with a gentle slope for convenience of explanation, but in reality, the output waveform is steeper. Therefore, if the waveforms are matched at the starting point of the rising, the difference in the level after the rising becomes large, and a large timing shift occurs according to the amplitude of the output waveform. This makes it impossible to consider substantial phase matching. On the other hand, if the phase is matched at the position at the timing when the waveform completely rises, the rising start point will be greatly deviated. This also leads to a substantial phase shift.

Since there is a problem that such a shift cannot be physically eliminated, it is only possible to consider the midpoint of these amplitudes as a reference, and in this way, the phase shift is evenly distributed on both sides, and the actual waveform rises. The hunger and falling slew rates are very fast in the tester, so it doesn't matter much.
Therefore, when considering the phases of two pulses, normally,
There is no choice but to pay attention to the midpoint of the rising or falling of each waveform.

Further, the waveform includes not only the rising waveform but also the falling waveform. When considering the delay times of both, it is preferable that the reference points are the same. From this point of view, we will focus on the midpoint.

Therefore, the object of the present invention is to eliminate the disadvantages of the conventional skew correction circuit as described above, and the pins of the tester such as the LSI are out of phase with the inspection signal applied to the device under test.
That is, it is an object of the present invention to provide a signal output circuit of an IC tester that can perform appropriate skew correction even if the amplitudes of skews are different.

[Means for Solving the Problems] The feature of the signal output circuit of the IC tester of the present invention that achieves such an object is that the output voltage waveform supplied to a pin of the device under test is the output voltage waveform of another pin. And a skew correction circuit that gives a predetermined delay amount corresponding to the phase correction amount to match the input signal to the input signal and outputs the signal from the skew correction circuit to a pin In a signal output circuit of an IC tester having a driver, each digital value corresponding to each amplitude value of the output voltage waveform is used as an address to correspond to the phase correction amount for each of the plurality of amplitudes of the output voltage waveform. A memory that stores data in each address and an address that corresponds to the amplitude that receives the signal that determines the amplitude of the output waveform set in the driver The generated comprise a circuit for accessing the memory, and generates a predetermined delay amount by receiving the data skew correction circuit is read from the memory.

[Operation] By adopting such a configuration, for each pin, the amplitude of the voltage waveform and the necessary phase correction amount corresponding to the magnitude of the amplitude are converted into digital values, respectively, in advance.
The amplitude value is used as an address, the corresponding phase correction amount is combined as data and stored in the skew correction memory, and the amplitude of the signal actually input to the pin electronics of the tester is calculated as a digital value. By using the digital value as an address, the data stored in the memory can be read, and the input signal of the driver can be phase-corrected by the read value and output to the pin.

As a matter of course, the phase correction amount set in the skew correction circuit is necessarily set in accordance with the output waveform having the longest delay time as a reference. The reason why the longest delay time is set is that the time can be delayed but cannot be increased. The same applies to the above phase correction amount. Of course, in the output waveform to be used (including waveforms with different amplitudes), the phase correction amount for each pin is set with reference to the output waveform with the longest delay time. Is.

Now, for example, in the case shown in FIG. 4, if the data corresponding to the phase correction amount stored in the memory is used as the data with the midpoint of each amplitude as a reference, the waveform (1) is shown in the figure. By delaying the time difference with respect to the point as a reference, there is no time difference between the voltage waveforms (1) and (2) output from both pins at the midpoint of the amplitude of the voltage waveform. be able to.

In the case of FIG. 4, when the voltage waveforms have the same temporal changes, if the time difference between the output waveforms of each pin is set to 0 at the midpoint of the amplitudes of the output waveforms of both pins, the wave of small amplitude is the minimum. From the state until the state reaches the maximum state, it completely overlaps with the change in the waveform with large amplitude. This is a waveform in which the timings of the sloped portions are coincident so that when the two waveforms in the waveform of FIG. The waveforms differ only in the start position.
Since the timing to reach the logic level H state or the logic level L state coincides from the midpoint of the amplitude, the timing deviation to reach the H and L level states is reduced. From this point of view, as a tester, it can be considered that both pins are supplied with signals having no phase difference as compared with the prior art when viewed from the logic level.

The above is the same when, for example, one output waveform has a logic level H of 2V and a logic level L of 0V, and the other waveform has a logic level H of 0V and a logic level L of −2V. is there. Since the timing of reaching each logic level H or logic level L is based on each midpoint,
As long as the amplitudes are the same, the timing of transition to the H and L logic levels is the same. Even if the amplitudes are slightly different,
This shift amount is small. As described above, it is important for the device under test whether the logic level of the input signal is in the H state or the L state, and the timing of reaching the H and L levels is as high as possible. If you have all, H,
The voltage value in the L state does not matter much.

Therefore, the phase correction amount of the present invention is generated with the amplitude as a reference.

Further, in the IC test, the allowable range from the time of the logic level H or the logic level L (how many percent or less of the allowable range, etc.) may be a problem. In such a case, according to the present invention, the phase correction amount corresponding to the amplitude can be automatically set in the skew correction circuit by the data stored in the memory, so that the phase difference between the signals supplied to the plurality of pins can be increased. Is not limited to the case where the phase is corrected to 0 at the midpoint of the amplitude as described above, but the signal waveform has the highest value (logical level H) by changing the data of the phase correction amount according to the amplitude.
Can be made the same in the output waveform between different amplitudes. In addition, the phase correction amount data is
As shown in the figure, by changing the data so that the rising timings (starting timings from the logic level L) are the same, the rising timings can be made the same between the waveforms having different amplitudes.

This makes it possible to set effective timing for various test items. Therefore, the present invention is not limited to the phase correction data based on the midpoint.

That is, the phase correction data according to the amplitude stored in the memory according to the present invention may be determined so as to be most suitable according to the purpose of the test performed by the tester.

[Embodiment] FIG. 1 is a block diagram of an embodiment to which a signal output circuit of an IC tester of the present invention is applied.

1 is a voltage value corresponding to the logic level H (for example, 0V, 2V, 3
V, 4V, 5V, 6V, etc.) is input as a digital value, 2 is a signal for inputting a voltage value corresponding to a logic level L (for example, 0V, −2V, −3V, etc.) as a digital value, and 3 is , A D / A converter for D / A converting the signal 1 of the logic level H, 4 is a D / A converter for D / A converting the signal 2 of the logic level L, and 5 is shown in a digital value state The difference between the signal 1 of the logic level H and the signal 2 of the logic level L is calculated in the state of a digital value to obtain an address value corresponding to the amplitude of the logic level signal (difference between the level of the signal 1 and the level of the signal 2). The calculator 6 for calculating a digital value (address value of the memory 6) is a memory for generating a skew correction value (phase correction amount) according to the amplitude, and is composed of, for example, a RAM or a ROM. Reference numeral 7 denotes a skew correction circuit, which is 2V, when the amplitude of the input signal to the pin is a specific reference value with respect to the input signal of the driver 8 generated according to the timing signal generated by the timing generator. In the case of 3V, 5V, 6V, etc., the phase correction is performed by receiving the data from the memory 6 so that the phase of the output signal to the relevant pin matches the output signal phase of the other pin.

For example, as the data of the memory 6, the logic level L is 0V.
Then, the output waveform with the logic level H of 2V, and the output waveform with the longest delay time for each pin, so that the phase of the waveform of the output signal output to the relevant pin matches the output signal phase of other pins. Is used as a reference, and a phase correction value for performing skew correction is stored in the memory 6 at an address position corresponding to an amplitude of 2V.

In this case, the skew is measured at the midpoint of the waveform, 2V.
In case of, the position of 1.0V is used as a reference. This can be understood from the explanation of FIG. 4 and the case of FIG. 5 described later. Further, in the case of an output waveform in which the amplitude of the input signal to the pin, for example, the logic level L is 0V and the logic level H is 4V, with respect to the reference position of the output waveform with the longest delay time, If the phase correction value calculated based on the middle point (2.0V) is 4V, the amplitude of the memory 6 corresponding to each pin is 4V.
Will be stored in the address position corresponding to.

In other words, with the output waveform having the longest delay time as a reference, the same amount of phase correction as the delay amount given to the skew correction circuit 7 according to the conventional technique is expanded in the address of the amplitude of the specific reference value and stored in the memory 6. Therefore, the skew correction circuit 7
Phase correction is applied to.

In this way, in the case of a signal with an amplitude of 5V, the digital value corresponding to the difference value 5V is input to the calculator 5 and the calculator 5
Calculates the address position corresponding to the amplitude 5V of the memory 6 by adding a predetermined value to the digital value or multiplying it by a predetermined number. As a result of this calculation, the memory 6 is accessed and the phase correction amount stored corresponding to 5V is read out as data and set in the skew correction circuit 7 as a delay time. As a result, the signal input to the driver is delayed by the delay time corresponding to the amplitude of 5V, and the timing is matched with the output waveforms of the other pins.

Now, the voltage waveform (1) input to the three pins,
It is assumed that the amplitudes and phases of (2) and (3) are as shown in FIG. The amplitude of (1) is 6V, the amplitude of (2) is 4V,
The amplitude of (3) is 2 V, the rising timings of the three signals are the same, and the deviation a at the midpoint of the amplitude is 1 ns and the deviation b is 1 ns.
And If the reference waveform is (3), the phase correction corresponding to the amplitude for (3) is 0ns, the phase correction corresponding to the amplitude for (2) is 1ns, and the phase correction corresponding to the amplitude for (1) is 2ns.
Just go. The phase correction corresponding to the magnitude of these amplitudes is set as data in the skew correction memory 6 of the above-described embodiment, and skew correction is performed by the skew correction circuit by reading these data according to the amplitude. become.

That is, for the pins that generate the reference waveform (3) among the pins, the conventional skew correction circuit 7 provided for each pin receives the data from the memory 6 so that the phase deviation does not occur. It is corrected so as to match the reference value of the reference waveform (3).

In addition, when the output waveform with the longest delay time is used as the reference, the explanation from this reference is based on the reference waveform (3) of each pin.
Since the phase has already been corrected at the timing to meet this criterion, I will omit this.

[Effects of the Invention] As described above, according to the present invention, the phase difference between the signals supplied from each pin of the tester to the device under test is greater than that of the conventional one, even if the amplitude of the signal at each pin is large or small. Can be corrected with high accuracy as expected.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment to which a signal output circuit of an IC tester of the present invention is applied, FIG. 2 is an explanatory diagram of a phase difference of the signals, and FIG. 3 is an explanation of a conventional skew correction circuit. 4 and FIG. 4 are diagrams for explaining the influence of the amplitude on the phase difference correction, and FIG. 5 is an explanatory diagram of the timing for output voltage waveforms having different amplitudes. Input signal corresponding to 1 ... H, input signal corresponding to 2 ... L, 3,4 ... D / A converter, 5 ... calculator, 6 ... skew correction memory, 7 ... conventional type Skew correction circuit, 8 ... Driver.

Claims (2)

[Claims] 1. A predetermined delay amount corresponding to a phase correction amount for matching a phase of an output voltage waveform supplied to a pin of a device under test with an output voltage waveform of another pin, and outputting the input signal. In a signal output circuit of an IC tester having a skew correction circuit and a driver that receives a signal from the skew correction circuit and sends the signal of the output voltage waveform to the certain pin, A memory that stores data corresponding to the phase correction amount for each of the plurality of amplitudes of the output voltage waveform at the address, with each corresponding digital value as an address, and the output waveform set in the driver. A signal for determining the amplitude of the memory, generating the address value corresponding to the amplitude, and accessing the memory. A signal output circuit of an IC tester in which the skew correction circuit receives the data read from the memory and generates the predetermined delay amount. 2. The signal output circuit of the IC tester according to claim 1, wherein the data stored in the memory corresponds to the phase correction amount obtained with the midpoint of each amplitude as a reference.