JPH0760384B2 - Instruction execution method and data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to speeding up an information processing apparatus for pipeline control.

[Background of the Invention]

In a pipeline-controlled information processing device, the entire processing of instructions is divided into a plurality of partial processes, and an independent processing device is provided for each partial process. First, the first instruction is processed by the processing device that performs the first partial processing. When the processing is completed and the processing apparatus performs the second partial processing, the processing apparatus performing the first partial processing starts the processing of the second instruction. When the first instruction is transferred to the processing device that performs the third partial processing, the second instruction is processed by the processing device that performs the second partial processing, and the third instruction is processed by the first partial processing device. As described above, since the execution of the subsequent instruction of the first instruction is started before the entire processing of the first instruction is completed, the pipeline control information processing apparatus can realize high instruction processing performance.

However, if an instruction (hereinafter referred to as a subsequent instruction) that precedes an instruction (hereinafter referred to as a subsequent instruction) is an instruction that changes a register, and the subsequent instruction is an instruction that refers to that register (register conflict) Called state), the instruction processing does not proceed as described above. That is, until the preceding instruction writes the operation result in the register, or until the preceding instruction generates the operation result, the entire processing of the subsequent instruction, at least the partial processing that refers to the register, must be stopped. The suspension of execution of the subsequent instruction due to such a register conflict is a major impediment to performance improvement in the pipeline control information processing apparatus.

Japanese Patent Laid-Open No. 58-96346 is an example of shortening the execution stop due to a register conflict.

[Object of the Invention]

An object of the present invention is to provide an information processing apparatus of pipeline control which has a high instruction processing performance by eliminating execution stop of subsequent instructions at the time of register conflict.

[Outline of Invention]

According to the present invention, when the subsequent instruction is executed by using the operation result written in the register by the preceding instruction, the processing of the subsequent instruction and the processing using the operation result are performed until the operation result is determined. In the data processing device to be stopped, the instruction address of the preceding instruction, the instruction address of the instruction before the preceding instruction, the prefetch address when prefetching the preceding instruction, the prefetch when prefetching the instruction before the preceding instruction The memory operand address of the preceding instruction, the operation result, and the operation are associated with the associative key consisting of all the addresses or arbitrary bit position data combinations and the memory operand address determining information of the preceding instruction. Means for storing information indicating the result, and a store address of the store instruction when the store instruction is executed by the data processing device. The memory operand that matches the
Search for an address in the storage means, and at some time,
Associative writing means for rewriting the operation result corresponding to it with the store data of the store instruction, and rewriting the information indicating the operation result with the information indicating the memory operand, and the preceding instruction being executed. When the associated key is stored, the storage means is searched, and when the associated key is stored, means for outputting the operation result or the memory operand corresponding thereto, and the operation result from the output means Is output, the processing of the subsequent instruction stopped by using the operation result from the output means is started, and the operation result from the output means is equal to the operation result obtained by the operation of the preceding instruction. In this case, the processing of the started subsequent instruction is continued, and if they are not equal, the processing of the subsequent instruction is invalidated, and the processing of the subsequent instruction is performed using the operation result obtained by the operation of the preceding instruction. And a means for re-executing the above, when the memory operand is output from the output means, the operation specified by the preceding instruction is applied to the memory operand, and the subsequent operation stopped using the operation result. We propose a data processing device characterized in that it has means for starting the processing of instructions.

As a result, the processing of the subsequent instruction that is stopped when the register conflict occurs can be started using the information output from the associative memory, so that the above object can be achieved.

Example of Invention

 An embodiment of the present invention will be described in detail below with reference to the drawings.

First, the instruction format used in this embodiment will be described with reference to FIG. 1A. In this instruction format, each instruction word has a 4-byte length. The first byte represents an opcode (op).
The upper 4 bits of the second and third bytes represent the three register indicating fields (R1, X2, B2). The bottom 4 bits of the 3rd byte and the 4th byte represent the displacement (D2). In this instruction format, each register designation field is 4 bits and each designates one of 15 registers.

If the instruction is not a Store instruction, this means that the sum of the contents of the general-purpose register indicated by the X2 field, the contents of the general-purpose register indicated by the B2 field and the displacement D2 is used as the operand address, and the main memory pointed to by this address The operation indicated by the operation code op is performed on the contents of the location (called the second operand) and the contents of the general-purpose register designated by the R1 field (called the first operand).
It is to be stored in the general-purpose register designated by the R1 field.

If the instruction is a store instruction, the contents of the general-purpose register which is the first operand
It is stored in the location on the main memory which is the operand.

This command format is quoted from the command format of IBM System / 370, and more specifically, "IBM System (Ststem) / 370 operation processing (307Principles of Ope
ration) ”.

FIG. 1B is a newmonic representation of the instructions shown in FIG. 1A.

FIG. 2 is an example of an instruction sequence causing a register conflict. The preceding instruction () is an Add instruction, which means that the contents of register 1, the contents of register 2 and the address obtained by adding displacement 100 are added to the contents of register 5 and stored in register 5. Subsequent instruction () is a Subtract instruction, meaning that the contents of register 1, the contents of register 5 and displacement 150 are subtracted from the contents of register 8 and stored in register 8. To do.

Since the preceding instruction writes the operation result in the register 5 and the succeeding instruction uses the contents of the register 5, a register conflict has occurred.

Next, the outline of the overall configuration of the embodiment will be described with reference to FIG. This embodiment uses, as the operation result of the preceding instruction, the operation result of the preceding instruction stored in the associative memory in the previous execution or the result of performing the operation on the second operand of the preceding instruction stored in the associative memory. Is.

First, 304 is an instruction storage device, and 326 is an operand storage device. The instruction store 304 and the operand store are addressed byte by byte with a 24 bit address.

Reference numeral 100 is a prefetch instruction address register. Prefetching of instructions always starts at a 4-instruction word boundary on the instruction storage device.
It is performed in units of command words. Therefore, the prefetch instruction address register (IFA) 100 stores the upper 20 bits (bits 0 to 19) of the 24 bit address.

102 is a delay register of the prefetch instruction address register.

104, 106, 108, 110 are instruction buffers IB0, IB1, IB2, I respectively
It is B3, and the four instruction words prefetched from the instruction storage device 304 are stored in this order.

112 is an instruction register and 114 is an instruction counter.
One instruction word is always placed in 4 bytes from the instruction word boundary on the instruction storage device. Therefore, the upper 22 bits (bits 0-21) of the 24 bit address are stored in the instruction counter. The value of the instruction counter 114 is the instruction address of the instruction word in the instruction register 112 at that time.

118 is a register file composed of 16 registers.

An address adder 324 adds the contents of the register indicated by the X2 field of the instruction word, that is, the X2 register value and the contents of the register indicated by the B2 field, that is, the B2 register value and the displacement D2. The addition result is stored in the operand address register 120.

122 is an operand data register and 330 is an ALU.

124, 130, 132, 134, and 136 are the delay register of the instruction register 122, the delay register of the instruction counter 114, the delay register of the X2 register value, the delay register value of the B2 register value, and the delay register of the prefetch instruction address, respectively, and the operand address register 120 stores the operand address. At that time, the instruction register value, the instruction counter value, the X2 register value, the B2 register value of the instruction and the prefetch instruction address when prefetching the instruction are stored.

126,138,140,142,144 are registers 124,130,132,1 respectively
These are 34,136 delay registers, and when the operand data is stored in the operand data register 122, the instruction register value of the instruction, the instruction counter value, the X2 register value, the B2
The register value and the prefetch instruction address when prefetching the instruction are stored in each.

Reference numeral 320 is an associative memory device, and 322 is a register conflict detection device.

Next, the overall operation when there is no register conflict will be described using the overall configuration diagram of FIG. 3 and the timing chart of FIG.

As shown in FIG. 5, it is assumed that the prefetch address register for prefetching the first to fourth instructions is stored in the prefetch address register from time TO. It is also assumed that the instruction register 112 and the instruction counter 114 store the instruction word before the first instruction, that is, the instruction word and instruction address of the 0th instruction before time T2. The address of the prefetch address register 100 is applied to the instruction storage device 304 via the signal line 500, and four instruction words starting from that address are output to the signal line 506, and four instruction words from the first instruction word to the fourth instruction word. Is time T1
Are stored in the instruction buffers 104, 106, 108, 110.

The address incrementer 302 receives the address of the prefetch address register 100 as an input, and outputs the address increased by four instruction words to the signal line 502. The signal on the signal line 586, which is the selection signal of the selector 300, is usually the “right selection signal” (only when it is explained below when a value other than the “right selection signal” is taken). The signal 502 is output to the signal line 506 through the selector 300 and stored in the prefetch address register 100. Time stored is time T0
It is time T4 after four cycles of. Order Bahhua 104,106,108,
These four command words are stored in 110 until time T5 when the next four command words are stored. Since the prefetch address register 100 is normally incremented by four instruction words in this way, subsequent instructions are sequentially prefetched and stored in units of four instructions in the instruction buffers 104, 106, 108 and 110.

Prior to time T2, the instruction counter 114 stores the instruction address of the 0th instruction. The value of the instruction counter 114 is applied to the address incrementer 310 via the signal line 530, incremented by one instruction word, and becomes the instruction address of the first instruction. The increased value is input to the selector 308 via the signal line 520. The selection signal 586 of the selector 308 is usually the “right selection signal” as described above, and at this time, the value of the signal line 520 is output to the signal line 518 via the selector 308. Signal line
The value of 518 is stored in the instruction counter 114. The value is also applied to the selector 306. The selector 306 uses the signal line 51
Looking at the lower 2 bits of the 22-bit address value of 8, if it is 0, the data of the signal line 508 is output to the signal line 516, and if it is 1, the data of the signal line 510 is output to the signal line 516. To be done. If it is 2, the data on signal line 512 is signal 5
16 is output, and if it is 3, the data of the signal line 514 is output to the signal line 516. As a result, the instruction next to the instruction set in the instruction register at the previous time is selected by the selector 306 and stored in the instruction register 112. At time T2, the first instruction word from the instruction buffer IBO 104 is stored in the instruction register 112, and at the same time, the instruction address of the first instruction is stored in the instruction counter 114.

Further, the value of the prefetch instruction address register is stored in the IFASV register 102 at the time T2 delayed by two cycles of the prefetch instruction address register IFA100.

The values of the register file 118 including 16 registers are applied to the selectors 312 and 314 via the signal line 532. Further, 4 bits of the X2 field of the first instruction in the instruction register 112 are applied to the selector 312 via the signal line 524. Accordingly, the selector 312 outputs the value of the register designated by the X2 field to the signal line 534. Signal line for selector 314
4 bits of the B2 field of the first instruction in the instruction register 112 are applied via 526. Selector 314 is now B
2 Output the value of the register indicated by the field to the signal line 536. Normally, "0" is applied to the signal lines 592, 590, 593, 591 (a value other than "0" is applied only in the case described below). At this time, the selectors 316, 318 shown in FIG. According to the operation diagram, the value of the signal line 534 is output to the signal line 540 via the selector 316, and the value of the signal line 536 is output to the signal line 542 via the selector 318.

In this way, the contents of the register designated by the X2 field of the first instruction are inputted to the address adder via the signal line 540, and the contents of the register designated by the B2 field of the first instruction are inputted via the signal line 542. Is entered. Furthermore, the signal line
The displacement D2 of the first instruction in the instruction register 112 is input via 528. The address adder adds the above three input values and outputs the operand address of the first instruction, which is the addition result, to the signal line 548, which is stored in the OA 120 of the operand address register at time T3. At the same time, the first command word is stored in the IR1 register 124 via the signal line 522,
The first instruction address is stored in the IC1 register 130 via the signal line 530, the X2 register value of the first instruction is stored in the GRX1 register 132 via the signal line 540, and the GRB1 is the B2 register of the first instruction. The value is stored via signal line 542, IFA1
The register 136 stores the prefetch instruction address when the first instruction is prefetched.

The operand address of the first instruction in the operand address register 120 is applied to the operand storage device 326 via the signal line 550, and the operand data of the first instruction at the location indicated by the address is output to the signal line 552. It At time T4, the operand data of this first instruction is stored in the operand data register 122.

At the same time, IR1 is sent to IR2 register 126 via signal line 562.
The register stores the first instruction word, the IC2 register 138 stores the instruction address of the first instruction from the IC1 register 130 via the signal line 572, and the GRX2 register 140 stores the GRX1 register via the signal line 570. 132 stores the X2 register value of the first instruction, GRB2 register 142 stores the B2 register value of the first instruction from GRB1 register 134 via signal line 568, and IFA2 register 144 stores signal line 566. Through IFA 1
The prefetch instruction address when the first instruction word is prefetched from the register 136 is stored, and the OA2 register 706 stores the signal line 55.
The operand address is stored from the OA register 120 via 0.

The ALU330 has three input signal lines. The operand data of the first instruction in the operand data register 122 is input from the signal line 554. The operation code of the first instruction in the IR2 register 126 is input from the signal line 594. The value of the register file 118 composed of 16 registers is applied to the selector 328 via the signal line 532, and the value of the signal line 558 is further applied.
The R1 field of the first instruction is applied via the. As a result, the selector 328 applies the value of the register designated by the R1 field, that is, the R1 register value to the signal line 560, which is input to the ALU 330. ALU is signal line 560
The input data from is the first operand data, and the signal line
Input data from 554 as the second operand data,
Perform the operation of the operation code shown on the signal line 594 to both,
The calculation result is output to the signal line 556.

The operation result of the first instruction is applied to the register file 118 via the signal line 556, and the IR2 register is applied via the signal line 558.
The R1 field of the first instruction at 126 is applied. Time T
When it reaches 5, the operation result of the first instruction is written in the register designated by the R1 field, that is, the R1 register.

When the instruction is a store instruction, the fact is detected by the write instruction detector 710 and input to the operand storage device 326 via the signal line 712. As a result, when the contents of the R1 register of the store instruction inputted via the signal line 560 to the operand address of the store instruction inputted via the signal line 708 at the operand storage device become the time T5. Written. At this time, the writing to the R1 register described above is not performed.

With the above, the processing of the first instruction ends.

In the processing of the second instruction, first, at time T3, the second instruction word is stored in the instruction register 112, and the instruction address of the second instruction is stored in the instruction counter IC. After that, the processing proceeds in the same manner as the first instruction.

The processing of the instructions after the third instruction proceeds like the first and second instructions at a time one cycle behind the processing of the previous instruction. However, since the prefetch of the instruction is performed in units of four instruction words, the prefetch instruction address register 100, the instruction buffers 104, 106, 108, 110, and the IFASV register 102 are stored once every four cycles.

As described above, 1 if there is no register conflict
Command processing progresses every cycle.

Next, an explanation will be given of the overall operation when there is a register conflict. Before that, referring to FIG.
0 is explained.

The storage capacity of the associative memory device in the embodiment is 10 words.

Each word has an IC storage unit ICP346, an IR storage unit IRP348, an X2 register value storage unit GRXP350, a B2 register value storage unit GRBP352, a prefetch instruction address storage unit IFAP354, and a data storage unit DATAP35.
6 and an address storage unit ADDRP345 and a flag storage unit FLGP347.

When data is applied to the signal lines 530, 522, 540.542,500, the associative memory device searches. Signal line 530,522,540,542,500
When there is a word in which the above data and the data in IC storage unit ICP346, IR storage unit IRP348, X2 register value storage unit GRXP350, B2 register value storage unit GRBP352, and prefetch instruction address storage unit IFAP354 all match, there is a match detector 344. Outputs "1" to set the HITL register 156 to "1", and the data in the data storage unit DATAP356 of that word is transferred to the DATAL register 158.
And stores the data of the flag storage unit FLGP347 in the FLGL register 157. When there is no matching word, the match detector 344 outputs "0" and sets the HITL register 156 to "0".

On the other hand, when “1” is applied to the signal line 584 or “0” is applied to the signal line 586, the associative memory device outputs the signal lines 580, 564, 578, 57.
Data on 6,574,556,708 are stored in IC memory ICP346, IR
Storage unit IRP348, X2 register value storage unit GRXP350, B2 register value storage unit GRBP352, prefetch instruction address storage unit IFAP354,
Data storage unit DATAP356 Address storage unit ADDRP345 is used as data, and a flag storage unit FLGP347 is set to "1". At that time, when a word in which all the data in the IC storage unit ICP346, the IR storage unit IRP348, the X2 register value storage unit GRXP350, the B2 register value storage unit GRBP352, and the prefetch instruction address storage unit IFAP354 are already stored, that word is stored. Overwritten. When the matching word is not yet stored, a new word is assigned and registered.

When “1” is applied to the signal line 712, that is,
When the Store instruction is executed, the associative memory device detects whether there is a word in which the operand address of the Store instruction sent via the signal line 708 and the address storage unit ADDRP exist and exists. In this case, the data storage unit DATAP of all such words is rewritten with the contents of the R1 register of the store instruction transferred via the signal line 560, and the flag storage unit FLGP of that word is rewritten.
Store "0".

Note that "1" in the flag storage unit FLGP means that the corresponding data storage unit DATAP stores the operation result when the instruction was previously executed, and "0" in the flag storage unit FLGP.
Means that the second operand data is stored in the corresponding data storage unit DATAP.

This is the end of the description of the associative memory device.

Next, the operation when there is a register conflict will be described. The two instructions in FIG. 2 are considered as the instruction having a register conflict, and the Add instruction is the first instruction and the Subtract instruction is the second instruction. The third and subsequent instructions are arbitrary instructions that do not cause register conflict with these instructions.

In the present invention, the operation result of the preceding instruction (the first instruction in the example considered below) causing the register conflict is obtained by using the information stored in the associative storage device. Therefore, when the preceding instruction is executed, whether or not the prediction can be made depends on whether or not there is information in the associative memory.

First, a case where the associative storage device has no information at the time of previous execution will be described. FIG. 6 is used as a timing chart.

Most of the instruction prefetching from the first instruction to the fourth instruction and the processing of the first instruction are the same as the operation when there is no register conflict as described above. That is, regarding the first to fourth instructions in the timing chart of FIG.
IFA, IBO-3, IFASV, IR / IC, OA / IR1 / IC1 / for 1st instruction
The timing of GRX1 / GRB1 / IFA1, OD / IR2 / IC2 / GRX2 / GRB2 / IFA2, GR is the same as that of FIG. The other parts will be described below.

First, from time TO, the prefetch instruction address stored in the prefetch instruction address register 100 is applied to the prefetch instruction address storage unit IFAP354 of the associative storage device via the signal line 500. At time T2, the instruction word, instruction address, X2 register value, and B2 register value of the first instruction are stored in the IR storage unit 348, IC storage unit 346, and X2 register value storage of the associative storage device via the signal lines 522, 530, 540, and 542, respectively. Part 35
0, applied to the B2 register value storage unit 352.

The associative memory device searches for the data on the signal lines 530, 522, 540, 542,500. Since we are now considering the case where the associative memory does not have information from the previous execution, HITL
“0” is stored in the register 156. Further, this “0” is applied to the signal line 546.

At time T3, the first instruction Add to the IR1 register 124
The instruction word of the instruction is stored, and the instruction register 112 stores the instruction word of the Subtract instruction which is the second instruction. Therefore, the first on the signal line 582.
The R1 field “5” of the instruction is applied, and the X2 field “5” of the second instruction is applied to the signal line 524. Since it is assumed that there is no register conflict other than the first instruction and the second instruction, a value different from “5” is applied to the signal lines 558 and 526. Therefore, the output of the coincidence comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, 166 become "0". Therefore, the output signal line 593 of the OR circuit 168 becomes "1". Further, the output signal line 591 of the OR circuit 170, the output signal line 592 of the AND circuit 172, the output signal line 590 of the AND circuit 174, AND
The output signal line 584 of the circuit 180 becomes “0”.

Since the signal line 592 is "0" and the signal line 593 is "1", no significant data is output on the signal line 540 as shown in FIG. On the other hand, the selector 318 applies the B2 register value of the second instruction on the signal line 536 to the address adder 324 via the signal line 542. The displacement of the second command is applied to the address adder from the signal line 528. As a result, at time T4, significant data is not stored in the operand address register 120.

Also, IR1 register 124, IC1 register 130, GRX1 register 13
No significant data is stored in the 2, GRB1 register 134 or IFA1 register 136.

In the subsequent operation of the second instruction, since the significant data is not output on the signal line 540, the address adder 548 does not output the significant data. Therefore, no significant data is stored in the operand address register 120 even at time T4. Further, no significant data is stored in the IR1 register 124, the IC1 register 130, the GRX1 register 132, the GRB1 register 134, or the IFA1 register 136.

On the other hand, at time T4, the IR2 register 126 stores the instruction word of the Add instruction which is the first instruction. At this time, the output of the coincidence comparison circuit 164 becomes "1", and the outputs of the other coincidence comparison circuits 160, 162, 166 become "0". Therefore, the OR circuit 168
The output signal line 593 of and the output signal line 584 of the AND circuit 180 are "1".
become. In addition, the output signal lines 591 and 596 of the OR circuits 170 and 182 and the AN
The output signal lines 592 and 590 of the D circuits 172 and 174 become "0". At this time as well, the signal line 592 is "0" and the signal line 593 is "1", so that no data is output on the signal line 540. Since no significant data is output on the signal line 540, the address adder 548 does not output any significant data. Therefore, no significant data is stored in the operand address register 120 even at time T5. Also, IR1 register 124, IC1
No significant data is stored in the register 130, the GRX1 register 132, the GRB1 register 134, or the IFA register 136.

On the other hand, at time T5, no significant data is stored in the IR2 register 138. At this time, the coincidence comparison circuits 160, 16
The output of 2,164,166 is "0". Therefore signal line 590,591,5
92,593,584,596 are all "0".

As a result, the selector 316 outputs the X2 register value of the second address on the signal line 534 to the address adder 324 via the signal line 540.
To the second address on the signal line 536.
Address adder 324 from signal B2 register value via 542
Apply to. The displacement of the second address is applied to the address adder from the signal line 528. As a result, at time T6, the operand address of the second address is stored in the operand address register 120.

Also, IR1 register 124, IC1 register 130, GRX1 register 13
2, the GRB1 register 134 and the IFA1 register 136 store the same data as the operation when there is no register conflict at time T6.

The subsequent operation of the second address proceeds in the same manner as when there is no register conflict.

From time T4, the operation of the first instruction is being performed by ALU330,
The calculation result is applied to the associative memory device via the signal line 556 between the times T4 and T5.

Further, the "1" on signal line 584 is applied to the associative memory. As a result, the IC storage unit 346 and the IR storage unit of the associative storage device
348, X2 register value storage unit 350, B2 register value storage unit 352, prefetch instruction address storage unit 354, data storage unit 356, address storage unit 347 are respectively the instruction address of the first instruction on the signal line 580 and the signal line 564. First instruction word of, the X2 register value of the first instruction on the signal line 578, the B2 register value of the first instruction on the signal line 576, the prefetch instruction address when prefetching the first instruction on the signal line 574, and the signal line Operation result of 1st instruction on 556, signal line 7
A word which is the operand address of the first instruction on 08 and whose flag storage unit 347 is "1" is registered at time T5.

This completes the description when there is no information in the associative memory.

Next, a case where there is information in the associative memory will be described. The associative memory may store the operation result of the preceding instruction at the previous execution time or may store the memory operand of the preceding instruction.

First, the case where the associative storage device has the information result of the previous execution will be described. FIG. 7 is used as a timing chart.

The operation result is obtained by performing an operation on the first operand and the second operand (memory operand) in an operation instruction other than the load instruction. Since the first operand at the previous execution may not match the first operand at the next execution, the operation result in the associative memory cannot be said to be correct. Therefore, in the following cases, the processing of the second instruction is started with the operation result of the associative memory, and when the operation result of the first instruction is obtained later, it is compared with the operation result of the associative memory. The method is to re-process the two instructions.

Most of the instruction prefetching from the first instruction to the fourth instruction and the processing of the first instruction are the same as the operation when there is no register conflict as described above. That is, regarding the first to fourth instructions in the timing chart of FIG.
IFA, IBO-3IFASV, IR / IC, OA / IR1 / IC1 / G related to 1st instruction
The timing of RX1 / GRB1 / IFA1, OD / IR2 / IC2 / GRX2 / GRB2 / IFA2, GR is the same as that of FIG. The other parts will be described below.

First, from time TO, the prefetch instruction address stored in the prefetch instruction address register 100 is applied to the prefetch instruction address storage unit IFAP354 of the associative storage device via the signal line 500. Further, at time T2, the instruction word of the first instruction, the instruction address X2 register value, and the B2 register value are respectively IR storage unit 348, IC storage unit 346, and X2 register value storage unit of the associative storage device via signal lines 522, 530, 540, and 542, respectively. 350,
It is applied to the B2 register value storage unit 352.

The associative memory device searches for the data on the signal lines 530, 522, 540, 542,500. Now, considering that the associative storage device has the information of the previous execution, DA at time T3
The TAL register 158 stores the previous operation result of the first instruction, the FLGL register 157 stores "1", and the HITL register 156 stores "1". Further, this “1” is applied to the signal line 546.

At time T3, the first instruction Add to the IR1 register 124
The instruction word of the instruction is stored, and the instruction register 112 stores the instruction word of the Subtract instruction which is the second instruction. Therefore, the first on the signal line 582.
The R1 field “5” of the instruction is applied, and the X2 field “5” of the second instruction is applied to the signal line 524. Since it is assumed that there is no register conflict other than the first instruction and the second instruction, a value different from “5” is applied to the signal lines 558 and 526. Therefore, the output of the coincidence comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, 166 become "0". Therefore, with the output signal line 593 of the OR circuit 168
Output signal line 596 of OR circuit 182 and output signal line of AND circuit 172
172 becomes "1". Also, the output signal line 591, AND of the OR circuit
The output signal line 590 of the circuit 174 and the output signal line of the AND circuit 180 are "0".

The signal line 596 serves as the set signal of the ICSV register 158. Since this signal line is "1", the instruction address of the second instruction is stored in the ICSV register 116 at the time T4 and DATASV.
The register 154 stores the previous operation result of the first instruction.

Since the signal line 592 is "1" and the signal line 714 is "1", the selector 316 outputs the previous operation result of the first instruction on the signal line 538 via the signal line 540 as shown in FIG. Then, the selector 318 applies the B2 register value of the second instruction on the signal line 536 to the address adder 324 via the signal line 542.
Apply to. The displacement of the second command is applied to the address adder from the signal line 528. As a result, at time T4,
The operand address of the second instruction is stored in the operand address register 120.

Also, IR1 register 124, IC1 register 130, GRX1 register 13
2, the GRB1 register 134 and the IFA1 register 136 store the same data as the operation when there is no register conflict at time T4.

The subsequent operation of the second instruction proceeds in the same manner as when there is no register conflict.

From time T4, the operation of the first instruction is being performed by ALU330,
The calculation result is applied to the comparator 332 via the signal line 556 between the times T4 and T5. The previous operation result of the first instruction stored in the DATASV register 154 is applied to the other input of the comparator 332.

The following operation is divided into two types depending on whether or not the calculation result of the ALU330 matches the previous calculation result. First, the case where they match will be described. In this case, “1” is applied on the signal line 586. This “1” is input to the selectors 300 and 308.
At this time, the selector 300 transfers the data on the signal line 502 to the signal line 506.
Then, the selector 308 outputs the data on the signal line 520 to the signal line 51.
Output to 8. This is the same operation as when there is no register conflict, and the subsequent operation proceeds in the same manner as in that case.

A case where the calculation result of the ALU330 does not match the previous calculation result will be described below. Although FIG. 7 has been used as the timing chart in the above description, FIG. 8 is used in the following description. In this case, “0” is applied to the signal line 586. This “0” is input to the selectors 300 and 308. At this time, the selector 300 outputs the data on the signal line 504 to the signal line 506, and the selector 308 outputs the data on the signal line 504 to the signal line 518.
Output to. As a result, at time T5, the high-order 20 bits of the instruction address of the second instruction stored in the ICSV register 116 are stored in the prefetch instruction address register 100. This value is the same as the prefetch address from the first instruction to the fourth instruction. As a result, prefetching is executed at time T6.
The first to fourth instructions are the instruction buffers 104, 106, 108, 11
Stored in 0. Since the instruction address of the second instruction is applied to the signal line 518, the instruction register 11 at the time T7.
In 2 is stored the second instruction on the instruction buffer (IB1) 106. At time 5, the first instruction, which had a register conflict with the second instruction, has already written the operation result in the register designated by the R1 field. Therefore, at time T7, the procedure is the same as the description of the operation when there is no register conflict between the first instruction and the second instruction.

Further, "0" on the signal line 586 is applied to the associative memory. As a result, the IC storage unit 346 and the IR storage unit of the associative storage device
348, X2 register value storage unit 350, B2 register value storage unit 352, prefetch instruction address storage unit 354, data storage unit 356, address storage unit 345 are respectively the instruction address of the first instruction on the signal line 580 and the signal line 564. First instruction word of the, the X2 register value of the first instruction on the signal line 578, the B2 register value of the first instruction on the signal line 576, the prefetch instruction address when prefetching the first instruction on the signal line 574, the signal line Operation result of 1st instruction on 556, signal line 7
The word which is the operand address of the first instruction on 08 and whose flag memory is "1" is registered at time T5.

This is the end of the explanation when the calculation result in the ALU 330 does not match the previous calculation result.

Further, this concludes the description of the case where the associative memory device has the result of the previous execution operation.

Consider the following situation. First, the addition (Ad
d) Instructions and Subtract instructions are executed. The above-mentioned register conflict exists between them. The calculation result of the add instruction is stored in the associative memory 320, as described above. Then a Store instruction is executed. The store address of this instruction is assumed to be the same as the operand address of the Add instruction described above. If the contents of the associative memory 320 (that is, the above operation result) are not changed at the time of executing this Store instruction, the associative memory is executed when the above-mentioned addition (Add) instruction or subtract instruction is executed again. The operation result of the previous execution of the Add instruction is output from 320,
It will be used in the subtract instruction. Since the operand data used in the second addition (Add) instruction has been changed by the above-mentioned Store instruction, the operation result of the previous execution of the addition (Add) instruction output from the associative memory 320 Does not correctly predict the operation result of the second execution of the add instruction. Thus, when a Store instruction is executed and its store address is equal to the operand address of the instruction stored in associative memory, the operation result of this instruction stored in associative memory is The result will be different when the instruction is executed after that. When the store instruction is executed, the operation result in the associative memory may be rewritten with the store data.
At this time, the associative memory 320 is executed when the second Add command is executed.
As described above, the situation where the contents of is incorrect is 1
This is only when the operand data of the Add instruction is rewritten by the store instruction between the execution time of the second Add and Subtract instruction and the execution time of the second Add instruction. If the result is rewritten, the rewritten data in the associative memory 320 will always be correct. The processing will be described below.

As already mentioned in the description of the associative memory device 320, the store (S
When the "tore" command is executed, "1" is transferred to the associative memory device via the signal line 712. At the same time, the operand address (ie, store address) of the Store instruction is transferred via the signal line 708, and the contents of the R1 register of the Store instruction (ie, store data) is transferred via the signal line 560. Is transferred.

At this time, the associative storage device stores the address storage unit ADDR.
All the words equal to the address are searched, the data storage part DATAP of the same word is rewritten with the store data, and the flag storage part of the word is rewritten to "0".

This is the end of the description of the processing when the Store instruction is executed.

Next, a case where the associative memory device has the second operand (memory operand) of the preceding instruction will be described. FIG. 7 is used as a timing chart.

In this case, when the store instruction is executed as described above, the data in the associative memory {the previous operation result of the first instruction or the first instruction
Store instruction memory data (second operand)}
Since the data is rewritten, the second operand in the associative memory is always correct. Further, in this case, when the first instruction is subsequently executed for this second operand as described below, the operation is performed using the first operand at the time of execution of the first instruction. Is correct, unlike previous arithmetic results stored in associative memory. Therefore, in this case, the previous operation result and AL
It is not necessary to perform coincidence comparison of operation results in U and redo processing of the second instruction. It should be noted that data rewriting in the associative memory 320 by the store data by such a store instruction has not occurred, and the operation result (the operation result of the first Add instruction) exists in the associative memory 320 as described above. In this case, the value of the R1 register, which is the first operand at the time of executing the second Add instruction, may be different from that at the time of the first Add instruction. Matching comparison and redo processing of the second instruction (Subtract instruction) are indispensable.

Most of the instruction prefetching from the first instruction to the fourth instruction and the processing of the first instruction are the same as the operation when there is no register conflict as described above. That is, regarding the first to fourth instructions in the timing chart of FIG.
IFA, IBO-3IFASV, IR / IC, OA / IR1 / IC1 / G related to 1st instruction
The timing of RX1 / GRB1 / IFA1, OD / IR2 / IC2 / GRX2 / GRB2 / IFA2, GR is the same as that of FIG. The other parts will be described below.

First, from time TO, the prefetch instruction address stored in the prefetch instruction address register 100 is applied to the prefetch instruction address storage unit IFAP354 of the associative storage device via the signal line 500. Further, at time T2, the instruction word of the first instruction, the instruction address X2 register value, and the B2 register value are respectively transmitted via the signal lines 522, 530, 540, and 542 to the IR storage unit 348, the IC storage unit 346, and the X2 register value storage unit of the associative storage device. 350,
It is applied to the B2 register value storage unit 352.

The associative memory device searches for the data on the signal lines 530, 522, 540, 542,500. Since it is now considered that the associative memory device has the second operand (memory operand) of the preceding instruction, the DATAL register 158 has the first operand at the time T3.
The instruction, that is, the second operand of the preceding instruction is stored,
"0" is stored in the FLGL register 157, and the HITL register 1
“1” is stored in 56. Furthermore, this "1" is a signal line
Applied to 546.

At time T3, the first instruction Add to the IR1 register 124
The instruction word of the instruction is stored, and the instruction register 112 stores the instruction word of the Subtract instruction which is the second instruction. Therefore, the first on the signal line 582.
The R1 field “5” of the instruction is applied, and the X2 field “5” of the second instruction is applied to the signal line 542. Since it is assumed that there is no register conflict other than the first instruction and the second instruction, a value different from “5” is applied to the signal lines 558 and 526. Therefore, the output of the coincidence comparison circuit 160 becomes "1", and the outputs of the other coincidence comparison circuits 162, 164, 166 become "0". Therefore, with the output signal line 593 of the OR circuit 168
The output signal line of the OR circuit 182 and the output signal line 172 of the AND circuit 172
Becomes "1". Further, the output signal line 591 of the OR circuit, the output signal line 590 of the AND circuit 174, and the output signal line of the AND circuit 180 become “0”.

To the ALU360, the second operand of the first instruction is input via the signal line 538, the content of the R1 register of the first instruction, that is, the first operand is input via the signal line 606, and the signal line
The operation code of the first instruction is input via 604. ALU36
0 calculates the first instruction by this, and outputs the calculation result on the signal line 600.

Since the signal line 592 is “1” and the signal line 714 is “0”, the selector 316 adds the calculation result of the first instruction on the signal line 600 to the address addition via the signal line 540 as shown in FIG. Then, the selector 318 applies the B2 register value of the second instruction on the signal line 536 to the address adder 324 via the signal line 542. The displacement of the second command is applied to the address adder from the signal line 528. As a result, at time T4, the second instruction operand address becomes the operand address register 120.
Stored in.

Also, IR1 register 124, IC1 register 130, GRX1 register 13
2, the GRB1 register 134 and the IFA1 register 136 store the same data as the operation when there is no register conflict at time T4.

The subsequent operation of the second instruction proceeds in the same manner as when there is no register conflict.

This completes the description of the case where the associative memory device has the second operand of the preceding instruction.

Next, the effect peculiar to this embodiment will be described.

In the case where the present invention is not used, when the preceding instruction and the succeeding instruction having a register conflict are executed, the operation is the same as the case where the associative storage device of the above-mentioned operation description does not have information of the previous execution, and two cycles of idle time are generated.

If you use the present invention, you will not have to spend your free time.
Instruction processing performance is improved when a register conflict occurs.

In the above-described embodiment, as the operation result of the preceding instruction, the previous operation result of the preceding instruction stored in the associative memory or the second operand (memory operand) of the preceding instruction stored in the associative memory The result obtained by performing the operation using the first operand of the preceding instruction is used. However, in the present invention, the previous operation result of the preceding instruction is not stored in the associative memory, but the second operand of the preceding instruction is always stored, and the operation result of the preceding instruction always precedes the second operand. It can also be applied to the case where the result obtained by performing the operation using the first operand of the instruction is used.

An embodiment in this case is shown in FIG.

In the associative memory of this figure, when there is no information in the associative memory,
The second operand of the preceding instruction is stored via the signal line 554 instead of the signal line 556 in the figure, and the flag storage unit is set to "0".
By doing so, the second operand of the preceding instruction is always stored in the associative memory. Therefore, when the second operand is stored in the associative memory, the subsequent instruction can be executed without any free time as in the above-mentioned embodiment.

In the two embodiments shown in FIGS. 3 and 11, when the store instruction is executed, the store data is used to rewrite the information in the associative memory. However, the present invention is also applicable to invalidating a word whose store address and operand address match when a store instruction is executed.

In this case, the associative memory 320 of FIG. 4 should be deleted from the associative memory when the "1" is applied to the signal line 712 and the word whose store address on the signal line 708 is equal to the address memory section. Just configure it. Also in this case, when the information is stored in the associative memory, the subsequent instruction can be executed without any free time as in the above-mentioned embodiment.

Further, as the associative key, all of the above-mentioned can be used or any combination can be used. In that case, some bit positions of the key component can be used.

〔The invention's effect〕

When the present invention is not used, the address calculation time of the preceding instruction, the operand read time, and the operation time are required from the start of the preceding instruction causing the register conflict to the start of the succeeding instruction.

However, by using the present invention, it only takes time from the input of the associative key to the prediction device to the output of the prediction value. The latter time varies depending on what is used for the associative key, but in the worst case where the instruction address of the preceding instruction is used for the associative key, the time is sufficiently shorter than when the present invention is not used.

[Brief description of drawings]

Figure 1A is an instruction format diagram, Figure 1B is an example of a load instruction, Figure 2 is an example of two instructions that cause a register conflict, and third.
FIG. 4 is an overall configuration diagram of an embodiment, FIG. 4 is a configuration diagram of an associative storage device, FIGS. 5 to 8 are timing chart diagrams, FIG. 9 is a configuration diagram of a register conflict detection device, and FIG. 10 is an operation diagram of a selector. , FIG. 11 is an overall configuration diagram of another embodiment. 100 ... Look-ahead instruction address register, 304 ... Instruction storage device, 104, 106, 108, 110 ... Instruction buffer, 112 ... Instruction register, 114 ... Instruction counter, 324 ... Address adder, 120 ... Operand address register, 326 ... Operand storage device, 126 operand data register, 330 ALU, 118 register file, 320 associative memory, 322 register conflict detection device.

Continuation of the front page (72) Inventor Shigeo Takeuchi 1479 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ultra ELS Engineering Co., Ltd. In-house

Claims (7)

[Claims] 1. Detecting whether or not there is a conflict that the execution result of the preceding instruction is used by the succeeding instruction between the preceding instruction and the succeeding instruction to be executed in parallel with the preceding instruction. When a conflict is detected between instructions, the execution result of the preceding instruction is delayed until the execution result of the preceding instruction is available, and the timing when the succeeding instruction uses it is delayed, and the preceding instruction is re-executed later. , When the subsequent instruction is also re-executed in parallel, before the result of re-execution of the preceding instruction is actually available, the previous execution result of the preceding instruction,
It is used as the execution result of the preceding instruction this time, the subsequent instruction is re-executed, and the preceding instruction is an instruction that operates on an operand in the main memory, and the preceding execution of the preceding instruction is executed. When the re-execution of the preceding instruction and the re-execution of the succeeding instruction are performed when the instruction that updates the memory operand used by the preceding instruction is executed before the re-execution of the preceding instruction. (A) before the execution of the operation designated by the preceding instruction when the preceding instruction of the preceding instruction is re-executed, the operation designated by the preceding instruction is executed using the updated memory operand; (B) The result of the operation using the updated memory operand is used instead of the re-execution of the subsequent instruction using the previous execution result of the preceding instruction, and the subsequent instruction is used. Instruction execution method of performing the re-execution. 2. When a conflict is detected between the preceding instruction and the succeeding instruction, the execution result of the preceding instruction is stored, and the preceding instruction is stored in an operand in a memory that can be designated by the instruction. In the case where an instruction for performing an operation on the preceding instruction is executed after the preceding instruction is executed and before the subsequent instruction is executed, the memory operand used by the preceding instruction is updated. 2. The memory operation operand after the update is stored instead of the stored operation result, and the operation result or the memory operand stored for the preceding instruction is used when the subsequent instruction is re-executed. Instruction execution method. 3. When the preceding instruction is an instruction for performing an operation on an operand in a memory that can be designated by the instruction, when the operation result of the preceding instruction is stored, the address of the memory operand is further stored. Then, when any of the instructions for updating the memory operand is executed after the preceding instruction is executed, a match between the memory address designated by the update instruction and the stored memory address is detected, and the match is detected. 2. The instruction execution method according to claim 1, wherein the storage of the updated memory operand is performed when is detected. 4. A means for detecting whether or not there is a conflict between a preceding instruction and a succeeding instruction to be executed in parallel between the preceding instruction and the succeeding instruction using the execution result of the preceding instruction. When a conflict is detected between the two instructions, means for delaying the timing at which the execution result of the preceding instruction is used by the subsequent instruction until the execution result of the preceding instruction becomes available; Is later re-executed and the subsequent instruction is also re-executed in parallel therewith, before the result of re-execution of the preceding instruction is actually available, the previous execution result of the preceding instruction is
Prediction executing means for re-execution of the subsequent instruction, an arithmetic unit for conflict resolution, and an arithmetic operation for the operand in the main memory, which are used as results of execution of the preceding instruction this time. The instruction to be executed, and when the instruction that updates the memory operand used by the preceding instruction is executed after the preceding execution of the preceding instruction and before the re-execution of the preceding instruction, When the re-execution and the re-execution of the subsequent instruction are performed, the updated memory operand is supplied to the arithmetic unit before the operation designated by the predecessor instruction is executed at the re-execution of the preceding instruction. Means and, instead of the re-execution of the subsequent instruction by the prediction executing means, using the result of the operation by the arithmetic unit using the updated memory operand, Data processing apparatus having a means for re-execution of the instruction. 5. A means for detecting whether or not there is a conflict between the preceding instruction and a succeeding instruction to be executed in parallel with the preceding instruction by using the execution result of the preceding instruction. When a conflict is detected between the two instructions, means for delaying the timing at which the execution result of the preceding instruction is used by the subsequent instruction until the execution result of the preceding instruction becomes available; Is later re-executed and the subsequent instruction is also re-executed in parallel therewith, before the result of re-execution of the preceding instruction is actually available, the previous execution result of the preceding instruction is
Prediction executing means for re-execution of the subsequent instruction, an arithmetic unit for conflict resolution, and an arithmetic operation for the operand in the main memory, which are used as results of execution of the preceding instruction this time. The instruction to be executed, and when the instruction that updates the memory operand used by the preceding instruction is executed after the preceding execution of the preceding instruction and before the re-execution of the preceding instruction, When the re-execution and the re-execution of the subsequent instruction are performed, the updated memory operand is supplied to the arithmetic unit before the operation designated by the predecessor instruction is executed at the re-execution of the preceding instruction. Means and, instead of the re-execution of the subsequent instruction by the prediction executing means, using the result of the operation by the arithmetic unit using the updated memory operand, Instruction re-execution means, means for storing the previous execution result of the preceding instruction in response to the detection of a conflict between the two instructions by the detection means, and the instruction for updating the memory operand Is executed, the execution result stored with respect to the preceding instruction is invalidated, and the memory operand after being updated by the update instruction is written into the storage means as information related to the preceding instruction, The prediction execution means comprises means for reading the previous execution result of the preceding instruction from the storage means and using this as the execution result of the present time of the preceding instruction to re-execute the subsequent instruction. The means supplies the stored memory operand to the arithmetic unit when the memory operand is stored for the preceding instruction when the subsequent instruction is re-executed. Data processing apparatus having a. 6. The prediction execution means synchronizes the stored execution result of the preceding instruction or the data consisting of a memory operand with the execution of the preceding instruction, and with the execution of the following instruction. Irrelevant reading means, and when a conflict is detected by the detecting means during execution of the subsequent instruction, and when the read data is the operation result of the preceding instruction Means for using as an operand of an instruction, the supplying means, when a conflict is detected by the detecting means during execution of the subsequent instruction, and the read data is a memory operand. The data processing apparatus according to claim 5, further comprising means for supplying the arithmetic unit to the arithmetic unit at a certain time. 7. The storage means comprises associative memory for storing the execution result of the instruction ahead of the instruction, using the information associated with the preceding instruction as an associative key, and the prediction execution means is provided when any of the instructions is executed. 6. The data processing according to claim 5, further comprising means for accessing the associative memory by using information related to the instruction as an associative key and reading out a previous execution result of the instruction or a memory operand if already stored. apparatus.