JPH0761137B2 - Input signal discrimination circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal discriminating circuit, and more specifically, it detects the presence or absence of a television video signal as an input signal, and when there is no video signal, Alternatively, when the signal is not a regular video signal, it is discriminated, and the signal after the discrimination relates to an input signal discriminating circuit used, for example, for blocking an audio signal.

Configuration of Conventional Example and Its Problems For example, the simplest method for determining the presence or absence of a video signal is to directly detect the amplitude value of the video signal, but it is difficult to distinguish between a normal video signal and noise. , Practically impossible to use. On the other hand, in a video device having a flyback pulse, such as a television receiver, since the flyback pulse has a phase that matches the synchronization signal, it is necessary to AND the two pulses with an AND circuit or a NAND circuit. Thus, a circuit for determining the presence / absence of a video signal can be constructed relatively easily. However, the above configuration is not possible in a video device that does not have a flyback pulse, for example, a VTR (video tape recorder).

SUMMARY OF THE INVENTION The present invention has been made in order to overcome the above inconvenience, and has an object to provide an input signal discrimination circuit suitable for a VTR or the like that does not have a flyback pulse.

According to the present invention, the period between the upper limit time and the lower limit time is selected to be smaller than the width of the pulse of the input signal such as a horizontal synchronizing pulse, and the upper limit of the sawtooth wave. A level switch type CR oscillator that generates an oscillation pulse whose rising and falling are synchronized with the time point of the value and the time point of the lower limit value, and the sawtooth wave is received in one base of a pair of transistors commonly connected to the emitter, and the other A waveform conversion for generating a rectangular wave whose edge portion is synchronized with substantially the center of the oscillation pulse by applying a voltage approximately equal to the sawtooth wave voltage value located substantially at the center of the oscillation pulse to the base of the transistor Circuit and the rectangular wave extracted as the output of the waveform conversion circuit is used as a comparison input to operate with the input signal as an input to control the oscillation frequency of the level switch type CR oscillator. And AFC circuit for a negative polarity pulse and the oscillation pulse of the input signal is is intended to include a logical circuit to be inputted.

Description of Embodiments FIG. 1 shows an embodiment of an input signal discriminating circuit of the present invention, and FIG. 2 shows an operation waveform diagram of an essential part of FIG.

The operation will be described in detail below with reference to FIGS. 1 and 2.

First, the horizontal oscillation input terminal 13 has a horizontal hold variable resistor.
A charging potential that charges the horizontal oscillation capacitor 18 from the power supply terminal 20 via 19 is applied. This charging potential is added as the base potential of the transistor 24, and when the initial base potential of the transistor 25 that is commonly connected to the emitter of the transistor 24 is V _H , this potential V _H is the resistance 28, 29, 30 and the power supply voltage V It is given by the following formula with _CC .

V _H = ・ (R ₂₉ ＋ R ₃₀ ) / (R ₂₈ ＋ R ₂₉ ＋ R ₃₀ ) …… (1) where R ₂₈ , R ₂₉ , and R ₃₀ are the resistance values of resistors ₂₈ , ₂₉ , and ₃₀ in Fig. 1. Yes, V _CC is the voltage value applied to power supply terminal 20. When the base potential of the transistor 24 reaches the V _H , the transistor 24 is turned on, the transistor 25 is turned off, and the current of the current source 26 flows in the collector of the transistor 24 via the resistor 27. As a result, the transistor 33 is turned on, the transistors 31 and 22 are both turned on, and the collector potential of the transistor 31 becomes the collector saturation voltage value. Since this saturation voltage value is considered to be practically zero volt, the base potential of the transistor 25 at this time is set to
If it is _VL , this potential _VL is given by the following equation.

_VL = V _CC · R ₂₉ / (R ₂₈ + R ₂₉ ) (2) On the other hand, when the transistor 22 turns on, the horizontal oscillation input pin
The electric charge charged in 13 is discharged to the potential of V _L via the resistor 21 and the transistor 22. Horizontal oscillation input terminal
13, that is, when the base potential of the transistor 24 reaches the V _L , the transistor 25 is turned on, the transistor 24 is turned off, the on / off operations of the transistors 33, 31 and 22 are reversed, and the horizontal oscillation capacitor is again provided. 18 charges are executed. By repeating the above operation, a sawtooth wave is generated at the horizontal oscillation input terminal 13. An oscillator that generates such a sawtooth wave is generally called a level switch CR oscillator. This sawtooth wave is shown in Figure 2a. The upper limit of the sawtooth wave is equal to V _H in the above formula (1), and the lower limit is equal to V _L in the above formula (2). By the way, the charging period tc and the discharging period td of the sawtooth wave are given by the following equations.

tc = R ₁₉・ C ₁₈ ln (V _CC −V _L ) / (V _CC −V _H ) …… (3) td ＝ R ₂₁・ C ₁₈ ln (V _H / V _L ) …… (4) where , R ₁₉ is the resistance value of the horizontal hold variable resistor 19, R ₂₁ is the resistance value of the resistor 21, and C ₁₈ is the capacitance value of the horizontal oscillation capacitor 18.

Correspondingly, the collector of the transistor 24 has a second
The pulse shown in FIG. B is output. This pulse is a so-called horizontal oscillation pulse, and its pulse width corresponds to the sawtooth wave discharge period td. This discharge period, that is, the pulse width output to the collector of the transistor 24 is proportional to the product of the resistance value R ₂₁ of the resistor ₂₁ and the capacitance value C ₁₈ of the capacitor 18, as shown in the equation (4). Therefore, for example, when the semiconductor integrated circuit is used, the capacitor
A desired horizontal oscillation pulse width can be selected by changing the capacitance value C ₁₈ of ₁₈ . This horizontal oscillation pulse width (2
.About.3 .mu.m) is chosen to be smaller than that of the horizontal sync pulse (about 5 .mu.m). FIG. 2c shows a pulse waveform generated at the horizontal oscillation pulse output terminal 41.

Further, the sawtooth wave generated at the horizontal oscillation input terminal 13 is applied to the base of the transistor 34. Transistors 34 and 35, emitters connected in common, current source 36 and transistors
The circuit unit composed of 38, 39, 40 is a waveform conversion circuit that converts a sawtooth wave into a predetermined rectangular wave. To the base of the transistor 35, as shown in FIG. 2a, a DC potential V ₃₇ equal to the midpoint of the period from the upper limit value P point (V _H ) of the sawtooth wave to the Q point (V _L ) is added in advance. When the base potential of the transistor 34 is higher than V ₃₇ , the transistor 34 turns on, and conversely, when the base potential of the transistor 34 is lower than V ₃₇ , the transistor 35 turns on. Therefore, the transistor 35
The rectangular wave shown in FIG. That is, the base potential V ₃₇ of the transistor 35 is selected so that the point X at the edge portion coincides with the approximate center of the horizontal oscillation pulse shown in FIGS.

The rectangular wave thus obtained is applied to the base of the transistor 4. Transistors 2,4,5,9,10,11 and resistors 3,6,7
The circuit part composed of is an automatic frequency control circuit, so-called
It is an AFC circuit. Transistor 4 and transistor 5
The potential V ₈ of the DC voltage terminal 8 is applied to the base of the transistor via the resistors 6 and 7, and when the rectangular wave voltage applied to the transistor 4 becomes lower than the base potential of the transistor 5, the transistor 5 is turned on. To do. Now, when the positive horizontal sync pulse shown in FIG. 2e is applied from the horizontal sync pulse input terminal 1, the transistor 2 is turned on, current is drawn from the transistor 4 and the transistor 5, and the transistors 2, 4, 5, The AFC circuit consisting of 9,10,11 and resistors 3,6,7 is activated.

By the way, the AFC circuit outputs the current ΔI _AFC shown in FIG. 2f to the AFC output terminal 12 when the phases of the horizontal oscillation pulse and the horizontal synchronizing pulse match. The output current ΔI _AFC is smoothed by the smoothing capacitors 14 and 15 and the smoothing resistor 16, and is added to the horizontal oscillation capacitor 18 via the resistor 17. As shown in FIG. 2f, when the phases of the horizontal oscillation pulse and the horizontal synchronization pulse match, the sum ΔI _{AFC of} both positive and negative components of ΔI _{AFC in} one cycle becomes zero, and the horizontal oscillation capacitor 18 Is not charged and the capacitor 18 is not discharged.

Now, if the frequency of the horizontal oscillation pulse becomes high, the period of the rectangular wave applied to the base of the transistor 4 becomes short, and ΔI _AFC becomes large on the negative side. Where ΔI
_The direction of the AFC flowing out from the AFC output terminal 12 is positive. Therefore, ΔI _AFC becomes negative, and the charging current of the horizontal oscillation capacitor 18 is drawn through the resistor 17. As a result, the charging period of the horizontal oscillation capacitor 18 becomes longer and the oscillation frequency becomes lower. On the other hand, when the frequency of the oscillation pulse becomes lower than the reference input pulse frequency, the transistor 4
The period of the rectangular wave applied to the base of becomes longer, and ΔI _AFC becomes larger on the positive side. Therefore, ΔI _AFC becomes positive and the resistance
Since it is added to the oscillation capacitor 18 via 17, the charging period of the horizontal oscillation capacitor 18 is shortened, and conversely the oscillation frequency is increased. In this way, the oscillation pulse of the oscillating air can be correctly matched with the phase of the horizontal synchronizing pulse.

Further, the positive horizontal sync pulse shown in FIG. 2 e is inverted into a negative horizontal sync pulse by the inverter 42, and is applied as one input of the AND circuit 44 through the lead line 43. A positive oscillation pulse shown in FIG. 2c output to the horizontal oscillation output terminal 41 is applied to the other input, and the two pulses are compared.

Next, the operation of signal discrimination will be described.

3 to 7 are diagrams used to explain the operation of signal discrimination. In each of the above figures, a shows the state of the horizontal synchronizing pulse and b shows the oscillating pulse. And c is an AND circuit
44 indicates the voltage generated at the output terminal 45 of 44, d is a transistor
46 emitter potential, i.e. capacitor 48 and resistor
A voltage (hereinafter, referred to as a peak value holding voltage) V ₄₇ held at the peak value by 49 is shown. In the signal discriminating circuit of this embodiment, the peak value holding voltage is set in the normal video signal state.
V ₄₇ is intended to be "L", otherwise "H".

First, FIG. 3 will be described. FIG. 3 shows a case where there is a regular video signal. Here, AND circuit 44 is ANDed
If constructed as a circuit, the output terminal 45 will have zero volts as shown in FIG. 3c. Here, the oscillation pulse width τ _OSC is
It should be noted that the horizontal sync pulse width τ _sync is set within the range. This is
In the case of a legitimate video signal, based on the intention that the output terminal 45 be set to zero volt, if the above setting conditions are deviated, the output terminal 45 will receive a “H” pulse. This is because the normal signal discrimination becomes impossible.

FIG. 4 shows a case where noise X is superimposed on the horizontal synchronizing pulse. In this case, at the output terminal 45, a signal in which noise is output only during the horizontal oscillation pulse period is generated as shown in FIG. The peak value holding voltage V ₄₇ is determined by the magnitude of the noise X, and the larger the amount of noise, the larger the voltage V ₄₇ . FIG. 8 shows the above relationship. That is, the peak value holding voltage V ₄₇ becomes a voltage between zero volt and “H” depending on the amount of noise. In addition, in FIG. 4, it is assumed that the voltage is held at V _X.

FIG. 5 shows the case where no horizontal sync pulse is present. Therefore, when the same signal as in FIG. 5a is input,
The pulse shown in FIG. 5c is output to the output terminal 45, and the peak value holding voltage V ₄₇ becomes “H”.

FIG. 6 is different from the normal television signal, but it is assumed that a pseudo, for example, horizontal sync pulse A portion is missing and the frequency is equivalently halved. Since such a signal is not a normal input signal, it must be discriminated as a normal video signal. Also in the case shown in FIG. 6, the peak value holding voltage V ₄₇ becomes “H”, and the same voltage V _{47 in} the case of a normal video signal is “L”.
It is clear that this was determined. As shown in FIG. 6a, it is important that the horizontal synchronizing pulse is set to the negative polarity, and when the normal video signal (shown in FIG. 3) is used.
This becomes even more apparent when compared with. That is,
Assuming that the horizontal synchronizing pulse shown in FIGS. 3 and 6a is positively set, the outputs shown in FIGS. 3c and 6c and the output terminal 45 of the AND circuit 44 are both high. Since the output of level "H" is generated, it is impossible to distinguish between the two. FIG. 7 shows the case where only the noise X arrives,
At this time, the signal generated at the output terminal 45 becomes a pulse in which the noise X is included in the oscillation pulse as shown in FIG. 7C, and the peak equivalency holding voltage V ₄₇ becomes "H". Peak value holding voltage V
₄₇ is added as one input voltage of the voltage comparator 51,
The other input voltage is the reference voltage V
₅₀ is given, both the peak voltage V ₄₇ and the reference voltage V ₅₀ are compared, and a DC voltage is output to the signal discrimination output terminal 52. And the reference voltage V ₅₀ as a boundary, when the holding voltage V ₄₇ is lower than the reference voltage V _50, as a regular signal, in the case of more than the reference voltage V ₅₀ Conversely, as can be determined as a non-video signal, the output A predetermined voltage is output to the terminal 52. In addition,
The voltage output to the signal discrimination output terminal 52 is used, for example, to cut off an audio signal.

EFFECTS OF THE INVENTION As described above, the input signal discrimination circuit of the present invention is a rectangular wave pulse that is automatically derived when obtaining a sawtooth wave,
That is, the horizontal oscillation pulse is configured to match the position of the horizontal synchronization pulse that serves as the reference input of the AFC circuit, and further, the horizontal oscillation pulse is set to fall within the range of the horizontal synchronization pulse width. By providing the AND circuit that inputs the signals in which the polarities of the two pulses are selected, it is possible to distinguish between the normal signal and the false signal with respect to various kinds of input signals.

[Brief description of drawings]

FIG. 1 is an input signal discrimination circuit diagram of the present invention, FIGS. 2a to 2f are operation waveform diagrams of the essential parts of FIG. 1, FIGS. 3 to 7 are diagrams for life of signal discrimination, and FIG. FIG. 4 is a characteristic operation diagram of signal discrimination. 1 ... Horizontal sync pulse input terminal, 8,37 ... DC voltage terminal, 12 ... AFC output terminal, 13 ... Oscillation input terminal, 14, 15 ...
… Smoothing capacitor, 16 …… Smoothing resistor, 17 …… Resistance,
18 ... Horizontal oscillation capacitor, 19 ... Hold variable resistance, 20 ... Power supply terminal, 26, 36 ... Current source, 41 ... Horizontal oscillation pulse output terminal, 42 ... Inverter, 44 ... AND circuit, 45 …… Output terminal, 50 …… Reference voltage application terminal, 51 ……
Voltage comparator, 52 ... Signal discrimination output terminal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-57-113612 (JP, A) JP-A-53-37327 (JP, A) JP-B-54-27215 (JP, B2)

Claims (1)

[Claims] 1. A sawtooth wave whose period between the upper limit time and the lower limit time is selected to be smaller than the pulse width of the input signal, and an upper limit time point and a lower limit time point of the sawtooth wave. A level switch type CR oscillator that generates an oscillation pulse whose rising and falling edges are synchronized with each other, and the sawtooth wave is received by the base of one of a pair of transistors whose emitters are connected in common, and the oscillation is generated by the base of the other transformer. A waveform conversion circuit that generates a rectangular wave whose edge portion is synchronized with substantially the center of the oscillation pulse by applying a voltage that is substantially equal to the sawtooth wave voltage value located approximately at the center of the pulse, and the waveform conversion circuit. And an AFC circuit that controls the oscillation frequency of the level switch type CR oscillator, which is operated by using the output rectangular wave as a comparison input and the input signal as an input,
An input signal discriminating circuit including a logical product circuit to which the negative polarity pulse of the input signal and the oscillation pulse are input.