JPH0762698B2 - Pattern generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus such as a large-scale logic LSI. In particular, in a test pattern generator for logic, a large-capacity memory is independently provided for each pin. The present invention relates to a pattern generator that is suitable for generating.

[Background of the Invention]

As a conventional logic LSI test pattern generator, a stored response type pattern generator (for example, Japanese Patent Publication No. 53-39729) in which pattern data to be generated in advance is stored in a pattern memory is known. .
However, when a large pattern is generated, the capacity of the pattern memory increases almost directly in proportion to the pattern length. Therefore, it is dealt with by providing a loop or jump function that can repeatedly generate the same pattern.

However, large-scale logic represented by recent microcomputers
In LSI, the number of function test patterns to be tested is huge due to the complicated functions, and it is necessary to rewrite the patterns in the pattern memory. For this reason, the transfer time of the divided test patterns cannot be ignored compared with the test time, and a pattern generator capable of generating a long pattern with a small capacity memory is indispensable.

[Object of the Invention]

An object of the present invention is to provide a pattern generator such as a logic test pattern generator capable of generating a long pattern with a smaller amount of hardware.

[Outline of Invention]

The present invention is basically a method of storing pattern data (1 or 0) to be generated in a pattern memory such as a conventional stored response method pattern generator in a time series, as opposed to a method of generating 1 at any arbitrary pin. Alternatively, pattern generation is a method of storing only the position (address) of the change point of the arrangement of the pattern data of 0, and performing the pattern generation by controlling the output pattern inversion when the change point address and the test pattern address match. It is a vessel.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. FIG. 1 is an overall configuration diagram of an embodiment of a pattern generator according to the present invention, and FIG. 2 is a relation between a conventional pattern data memory and a pattern address memory 3 for storing the change point address of the present invention in FIG. And an explanatory diagram showing an example of an output pattern, FIG. 3 is an operation timing diagram when the straight pattern of FIG. 1 is generated, FIG. 4 is an operation timing diagram of the jump of FIG. 1, and FIG. 3 is a truth table of the jump control circuit 6 of FIG.

First, the principle of generating a pattern from the conventional pattern data memory and the principle of generating a similar pattern from the pattern address memory 3 of the present invention shown in FIG.
This will be described with reference to FIG.

By the pattern address 6 indicating the generation order of the test patterns output from the test sequence controller 1 shown in FIG. 1, the pattern addresses A0, A1, A2, A3, ... In the conventional pattern data memory 12 shown in FIG. The stored 1-bit or 1-bit pattern data is sequentially read to obtain an output pattern f as shown in the lower diagram of FIG. As a result, when jumping or looping, this pattern address b is given as an irregular pattern address, so that a random output pattern f is obtained. On the other hand, the pattern generator of the present invention uses the pattern address memory 3 in place of the conventional pattern data memory 12 to change the n-bit pattern addresses A0, A1, of the pattern data of 1, 0 in the pattern data memory 12. A4, A6, ... only address #
0, # 1, # 2, ..., When the pattern address b from the test sequence controller 1 matches the change point address d, the output pattern f is inverted and controlled to obtain similar pattern data. is there.

Next, the configuration of FIG. 1 and its function will be described in detail for the case of generating a straight pattern and the case of generating a pattern during a jump.

In the normal operation mode, the test sequence controller 1 outputs the pattern address b and the pointer address g via the register 2-3 and the register 2-1 respectively. The pattern address b indicates the position of the pattern data to be generated from the conventional pattern data memory 12 shown in FIG. 2 when the straight pattern and the pattern at the time of jump are generated, and the pointer address g is an address valid only at the time of jump. , The address of the jump destination address or the address of the pattern address memory 3 in which the closest change point address is stored. The pointer 11 temporarily stores the pointer address g at the time of jump, and indicates the position of the change point address of the pattern address memory 3. The pointer 11 counts +1 when the change point address d and the pattern address b match, and indicates the position of the next change point address. Further, the output of the comparator 4 for comparing the pattern address b and the change point address d in the normal operation mode causes the flip-flop 5 to perform the inversion operation when the straight pattern is generated when the both coincide with each other, and the pointer 11 Is incremented.

The jump control circuit 6 determines the pattern data output at the time of jump based on the truth table of FIG. 5, and detects the position of the pointer in the pattern address memory 3 and the change point detection signal (match or mismatch signal) output from the comparator 4. The output pattern f of the flip-flop 5 is preferentially determined by e. In the truth table of FIG. 5, when the jump control signal h is generated from the test sequence controller 1 of FIG. 1, the pattern data generated in the clock cycle is determined as follows. That is, when the jump destination address is the change point, that is, the output e of the comparator 4
Is a coincidence (A = B) signal, the pattern data corresponding to the change point address may be output. Therefore, the position of the pointer of the pattern address memory 3, that is, the even lower or lower 1 bit c'of the output c of the pointer 11 Thus, the corresponding output pattern data f of 1 and 0 is output. On the contrary, when the jump destination is not the change point address, that is, when the comparator output e is a disagreement (A ≠ B) signal, the pointer 11 indicates the next closest change point address. May output the pattern before and after the change point address. That is, when the comparator output e is a non-coincidence signal, the corresponding pattern data f of 0 and 1 are output depending on the even and odd positions of the pointer. The jump control circuit 6 shown in FIG. 1 realizes the operation of the truth table shown in FIG. 5 as follows. Determines that the address is not the change point address, and AND gate
8-1, 8-2 and 8-3, 8-4 judge whether the pointer position is even or odd, respectively. Therefore, when the jump destination is the change point address and the pointer is an odd number position, and when the jump destination is not the change point address and the pointer is an even address,
In order to output "0" as the output pattern f, the flip-flop 5 is reset (R), and when the jump destination is the change point address and the pointer is an even position, the jump destination is not the change point address and the pointer is an odd address. At this time, the output pattern f at the time of jump can be obtained by setting (S) the flip-flop 5 to output "1" as the output pattern. FIG. 1 has the above-mentioned configuration and its function.

Next, the operation of FIG. 1 will be described with reference to FIGS. 3 and 4 for the case of generating a straight pattern and the case of generating a pattern during a jump, respectively.

First, before the pattern generation, the change point addresses A0, A1, A4, ... Are stored in advance in the pattern address memory 3 from the test sequence controller 1 via the register 2-2, and the pointer 3 is set to the register 2-1. The pointer address at the start is also set via. When the pattern generation is started at the clock a, the change point address d first output from the pattern address memory 3 is compared with the pattern address b to be generated at that time by the comparator 4, and the pattern address b changes. When it coincides with the point address d, the coincidence signal of the comparator output e passes through the AND gate 10 and the comparator output e as shown in FIG. An output pattern "1" corresponding to the address A0 is obtained. At this time, the pointer 3 is incremented by +1 to indicate the next change point address A1. Then, in the case of a straight pattern, according to the pattern generation program of the test sequence controller 1, for example, as shown in correspondence with the pattern address b in FIG. When the change point address d does not match, there is no clock input to the flip-flop 5, so the previous output pattern data is held. In this way, each time the pattern address b and the change point address d match, the output pattern f is inverted and pattern generation is performed.

Next, in the case of the jump pattern, when the JMP instruction occurs in the middle of the NOP instruction as shown in the diagram of the pattern address b in FIG. 4, the pointer address g and the jump control signal h are sent from the test sequence controller 1. Is output.
This pointer address g is an address corresponding to the position closest to the change point address stored in advance in the pattern address memory 3 of the jump destination or the position of the change point address one cycle (clock a) of the jump control signal h. Is loaded into the pointer 11 in the cycle in which the next jump control signal h is input via the register 2-1. Further, the jump control signal h activates the jump control circuit 6, and as described above in the jump control circuit 6, the pointer 11 determines whether the jump destination is the change point and whether the output pattern is 1 or 0. The output pattern f of the flip-flop 5 is controlled by the lower 1-bit signal c'of the output c. Thus, in the case of the first JMP instruction in FIG. 4, the jump destination is the change point address A4, and when the pointer address # 2 is loaded into the pointer address g, the lower bit c indicating the position of the pointer ′
Becomes an even number and a coincidence signal of A = B is output as the comparator output e. Therefore, the OR gate 9-1 sets the input of the flip-flop 5 via the gates 7-1 and 8-2 of the jump control circuit. S becomes active and pattern data "1" corresponding to address A4 is generated. Also, the second JMP
In the case of an instruction, the jump destination is not the change point address, and the jump destination is the pattern address A9, whereas the jump point is the change point address A10. In this case, the pointer address g is loaded with the pointer address # 5 closest to the changing point address, and the changing point address A10 is output from the pattern address memory 3. At this time, the lower bit e'indicating the position of the pointer becomes an odd number and the comparator output e becomes a non-coincidence signal of A ≠ 13. Therefore, the gates 7-2 and 8-3 of the jump control circuit 6 receive After passing, the set input S of the flip-flop 5 becomes active from the OR gate 9-1 and the pattern address A9
The pattern data “1” corresponding to is generated. In this way, a pattern similar to the conventional method is generated. When the jump control signal h is not input, the operation is the same as that of the straight pattern described above. Although the case of the jump in the forward direction has been described above, it is easy and can be inferred that the same operation is performed in the jump in the reverse direction.

As described above, in the present embodiment, since the conventional pattern data memory 12 is unnecessary and only the change point address is stored to generate the bit pattern, the long pattern generation causes the bit in the pattern address memory 3 to be large. By expanding the width, it is possible to generate a long pattern that is 2 ⁿ (n is the number of expansion bits) times.

〔The invention's effect〕

As described above, according to the present invention, it is not necessary to handle an enormous amount of test patterns and only the pattern position information of the changing points is required. Therefore, the number of changing point addresses to be stored is the same for all patterns This is about 10% of the number, and it is possible to generate a long pattern with a smaller amount of hardware. Further, since the expandability of the pattern can be expanded by the bit width of the change point address, it is possible to easily cope with the pattern length of 2 ⁿ (n is the number of expansion bits) times. Further, since the pattern information handled by the tester may be small, there is an effect that it is very easy to create a pattern manually or by a computer.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of a pattern generator according to the present invention, and FIG. 2 is a relation between a conventional pattern data memory and a pattern address memory for storing the change point address of the present invention in FIG. 1 and an output pattern. Explanatory drawing which shows an example of 3rd
FIG. 4 is an operation timing chart for generating the straight pattern shown in FIG. 1, FIG. 4 is an operation timing chart for the jump shown in FIG. 1, and FIG. 5 is a truth table of the jump control circuit shown in FIG. . 1 ... Test sequence controller, 2-1, 2-2, 2-3
...... Register, 3 ...... Pattern address memory, 4 …… Comparator, 5 ……
Flip-flop, 6 ... Jump control circuit, 7-1, 7-
2, 8-1, 8-2, 8-3, 8-4, 10 ... AND gate, 9-1, 9-
2 …… OR gate, 11 …… pointer,

Claims (1)

[Claims] 1. A means for storing only a change point address of a switching position, and a read address of the change point address instructed to the storage means, with one or a series of 1s or 0s of a pattern sequence as a unit. Reading means, means for comparing the test pattern address output from the test sequence controller with the change point address, flip-flop means for inverting the output pattern by the coincidence signal output from the comparing means, and the reading means Generated by the least significant bit of the read address, the match signal output by the comparison means, and the jump control signal output by the test sequence controller, when the generation pattern is 1, the set input of the flip-flop means is generated. If the pattern is 0, reset the flip-flop means Jump control means for applying a control signal to the force, and read means for reading the address corresponding to the next change point address position stored in the pattern address memory of the jump destination, which is output one cycle before the jump control signal. And a means for performing increment control of the reading means in response to a coincidence signal from the comparator.