JPH0762792B2 - Image display device - Google Patents

Description

The present invention relates to an image display device suitable for computer application equipment and liquid crystal televisions.

(B) Conventional technology Japanese Patent Application Laid-Open No. 60-7 for displaying a conventional liquid crystal display in color
There is, for example, Japanese Patent No. 3580, which is used as a television image. However, video signals from TVs, computers, etc. are sent at a predetermined speed and as serial data even after they have been digitized. Therefore, if this is used as it is, not only the response of the liquid crystal display but also the response including the drive element Poorness of the surface is likely to result in a rough and fluctuating image on the screen. Further, unlike the CRT, the liquid crystal display has a stripe type color filter array (see FIG. 4 (a)) and a mosaic type color filter array (see FIG. 4 ( In spite of the above (see b)), as the video signal processing, only a circuit intended for only one is proposed.

On the other hand, JP-A-59-28192 and JP-A-59-176985 disclose that a liquid crystal display is divided into upper and lower parts to improve the response of the liquid crystal element. Focusing on the handling of the pixel information, using a screen memory,
By temporarily storing the received video signal and reading it with a gap in the writing timing, the writing speed and the reading speed of the memory can be changed, and the screen memory for two screens can be alternately used for writing and reading. It was used for, or the video signal was regularly selected and sent to the driving element. However, these methods require complicated timing control means, large-capacity memory, and deteriorate image quality (particularly, display roughness). Therefore, it is not preferable that the number of display pixels is 500 × 200 dots or more. .

(C) Problems to be Solved by the Invention The present invention has been made in consideration of the above points, and is capable of supporting two types of color patterns and monochrome, and requires a screen memory for one screen. An image display device suitable for a large number of displays is provided.

(D) Means for Solving the Problems The present invention relates to an improvement of Japanese Patent Application No. 60-14038 previously applied,
In particular, before writing in the screen memory, it is provided with a selection means for recombining sequentially transmitted video signals in a predetermined order. More preferably, the screen memory for one screen is used by applying the cycle steal method. It was done.

(E) Action This allows the color arrangement of the liquid crystal display (including monochrome)
Regardless of this, the image transfer rate to the liquid crystal display is slow and the image quality is good.

(F) Embodiment FIG. 1 is a principle block diagram of an image display device of an embodiment of the present invention, FIG. 2 is its timing chart, and FIG. 3 is a screen memory peripheral block diagram.

In FIG. 1, (1) is a twisted nematic liquid crystal display, the electrodes of which are arranged in a matrix, and the screen (or electrode group) is independently driven and divided into two parts, 512 x 128 dots each. (512 x 256 dots on the entire screen)
Have pixels. (2) is a liquid crystal drive circuit of the liquid crystal display (1), which consists of Hitachi's HD44100H series, etc., receives the image signals serially transferred independently for the upper screen and the lower screen, adjusts the timing, and sets the bias. A line register (21) (21) with a driver for driving the given liquid crystal display (1), a column driver (22) (22) for scanning the liquid crystal display (1) line by line (of the above liquid crystal display (Scanning with 1/128 duty), a converter for parallel input / serial output conversion (P
→ S) (23) (23) and a latch (24) for storing pixel information at 1 o'clock.

(3) (3) is a screen memory that can store one screen of pixel information corresponding to dots of the liquid crystal display (1).
It consists of two 92-byte (65536-bit) statically driven random access memories (equivalent to 131072 bits). In addition, for simplification of description, the data per dot is 1 bit (binarization information of turning on or off) as an example, but the data is not limited to this.

(4) is a memory control means for controlling the mode address and timing relating to writing and reading of the screen memories (3) and (3). Of these, (41) and (42) are counters for the first and second address sets, both of which are selectors (4
3) (44) (for example, a multiplexer integrated circuit) is used to address the screen memories (3) and (3), but the second counter (42) is for reading the lower screen,
Since the counter (41) is connected to the selector (43) for writing and shifted by 1 bit for upper screen reading and connected to the selector (44), the reading count is different from the writing count.
It becomes 1/2 speed. Reference numerals (45) and (45) denote initial setting means for inputting a start address to the first and second counters (41) and (42), which include a register and the like, but the counter (41)
When (42) has a preset parallel input like the counter integrated circuit 74HC193, it may be constituted by a decimal switch or a wired logic. And the address of screen memory (3) (3) is hexadecimal number (display corresponding to decimal number is 0, 1 to 9 is 0, 1 to 9, 10 to 15 is A to F) and is 0000 for upper screen. ~ 1F FF and 2000 for lower screen ~ 3F
If it is FF address, the initial setting means (45) (45) respectively
0000 and 2000 are preset or stored. (46) is the first and second counters (41) (42), selectors (43) (4)
The memory timing control circuit outputs the operation timing signal of 4) and the write / read signal (R / W) of the screen memories (3) and (3) to select the mode of the memory.

(5) is an image processing circuit, which receives a video signal from a video, a personal computer, a magnetic image file device, or the like.
It consists of an I / O port or buffer, but may include a tuner, an intermediate frequency amplifier, a color signal separator, a binarization circuit, etc., and is a black and white (B / W) or color signal (R, G, B) and a display signal (D) obtained from a horizontal retrace signal (H), a vertical retrace signal (V), and a dot clock signal (DC) which is a transmission synchronization clock of a binarized video signal. .

(6) is a selecting means for sending the sequentially sent black and white (B / W) or video signals which are color signals (R, G, B) to the screen memory (3) (3) in a predetermined order. A group of gates for selecting the order of color signals (A ₀₁ , A ₀₂ , A ₀₃ , A ₁₁ , A ₁₂ , A ₁₃ , A ₂₁ , A ₂₂ ,
A ₂₃ , OR ₁ , OR ₂ , OR ₃ ) and a signal gate circuit (61) and a gate selection means (62) for designating and switching the signal gate circuit (61). The color arrangement is changed or fixed in one horizontal period (every display signal (D)), and a D flip-flop (621) (621) and a gate (622) for forming a ternary ring counter. (622) (622) (623) are provided, and as described later, when this ring counter does not advance, the color order is
Since it corresponds to RGB, it corresponds to a striped color pattern as shown in FIG. 4 (a), and when the ring counter advances, the color order changes every horizontal period, RGB, BRG, GBR, RGB ...

(7) is a serial / parallel conversion type converter (S → P) for collecting video signals in 8-bit units, and is for writing / reading the screen memories (3) and (3) in 8-bit units. , If the screen memory (3) (3) is a type that writes / reads in 1-bit units, the converter (P → S) (23) (2
Not needed with 3). However, since many commercially available RAMs perform writing / reading in 8-bit or 4-bit units, it is more general to use converters (S → P) (7) (P → S) (23) (23). It is highly likely.

(8) is a control means for controlling such that the entire image display device operates smoothly, and is also provided with a timing signal generation circuit.

The operation of the above-described structure will be described with reference to FIG. 2. The case where the color pattern of the liquid crystal display (1) is a mosaic pattern as shown in FIG. 4 (b) is taken as an example. First, the video signal output from the image processing circuit (8) is input to the selection means (6), but the D flip-flops (621) (621) of the gate selection circuit (62) are connected to the vertical retrace signal (V). Since it has been reset by, the AND gate (A ₀₁ , A ₀₂ , A ₀₃ ) of the signal gate circuit (61) is selected and the RGB
Sent to the converter (S → P) (7) so that the color array of
It is converted into parallel signals of 8 bits each, latched, and output in synchronization with the write / read signal (R / W).
Further, the memory timing control circuit (46) receives the initial signal (IS) by the display signal (D) after the vertical blanking signal (V).
To output the first and second counters (41)
(42) takes in the contents of the initial setting means (45) (45).

By the way, the screen memory (3) and (3) are write / read signals (R / W).
The write (W) read (R) memory mode is specified by the level of, and the write read signal (R / W) is determined so that the memory mode is alternately switched. The address of the screen memory (3) (3) to be written or read is selectively given by the first and second counters (41) (42). Since the first counter (41) is stepped up for each read (R) mode by the timing gate (9a) and the output is guided through the selector (43) at the write timing, the write address is changed at each write timing. Be stepped. The content of the first counter (41) is output through the selectors (44) and (43) every other read timing, or the least significant bit is ignored, so that the speed is half the write timing. The read address is incremented. On the other hand, the second counter (42) is stepped during the write timing at a half cycle of the write timing, and the selectors (44) (43) are alternated every other read timing.
The output is led to the screen memory (3) (3) through.

Therefore, for example, in the first frame, writing is performed step by step starting from the address "0000", and reading is started from the address "0000" and the upper screen pixel information and "200".
The lower screen pixel information starting from the address "0" is read alternately, and the writing of the first screen is completed (the last address is "3FFF").
The pixel information of the upper screen (address is "1FFF") is read at the timing immediately before, and the pixel information of the lower screen (address is "3FFF") is read at the timing immediately after. Furthermore, since the screen memory (3) (3) pixel information is a D flip-flop which is stored in the (621) (621) ternary ring counter consisting of such counts for each of the display signal (D) a gate (A _01, A _The gates (A ₁₁ , A ₁₂ , A ₁₃ ) are selected next to ₀₂ , A ₀₃ ), etc., and are sequentially changed. During the first horizontal period, R → G → B →
What was in the order of R ... Is written next while the order of B → R → G → B ... and the order of the color signals are changed.

As a result, the screen memories (3) and (3) are used in the cycle of write → upper screen read → sequential write → lower screen read, and the write time and read time for one screen become equal, and the converter ( P
→ (S) (23) (23) can be output to the line register (21) after the pixel information of the upper and lower screens has been gathered, so the reading speed is half the writing speed. Further, the continuity of the video signal is maintained on each of the upper and lower screens (since the video signal is serial data, the latter half of the n-1th screen and the first half of the nth screen are continuous, and both of them should be displayed as one display screen. Therefore, the screen is stable even for movies.

In the above description, the pixel information is treated as one set of data buses (BUS) for the screen memories (3) and (3), but it may be set to three sets. FIG. 3 shows this, and the screen memories (30a) (30a) (30b) (30b) (30c) (30c) are separated into three groups so that the data flow becomes three groups. Therefore, converter (S → P) (70) (70) (70) (P → S)
(230) (230) (230) (230) etc. are equipped with 3 sets, line register (210a) (210a) (210b) (210b) (210c)
(210c) is connected every 3 lines of liquid crystal display (10) 3
Separated into a set of registers.

As a result, the screen memory of the first block (30a) (30a)
Can handle only the R signal in the first horizontal period, only the B signal in the second horizontal period, the data bus and the memory block for each color signal, and the address of the screen memory can be common to all three blocks. The timing structure is simple.

Although the above description has been made on the color display of the mosaic pattern, the D flip-flops (621), (621) of the gate selection circuit (62) are set so as not to step (clock off or as shown in FIG. 1). Clear signal is always given), and the fourth
It is possible to perform color display in a stripe pattern as shown in FIG. 10A, and to deal with a monochrome signal (or a case where only a specific one of color signals is used).

As described above, according to the present invention, the color signals of the sequentially transmitted video signals are sent to the screen memory in each horizontal period in the same order as in the previous period or in a predetermined order different from the previous period. Since it has a selection means for selectively executing whether to send it to the screen memory instead,
Pixel information can be easily handled regardless of the color arrangement of the liquid crystal display (for example, a mosaic or stripe color pattern), and the pixel information output from the selection means is written in the screen memory and synchronized with the writing. Since the memory control means for reading out the pixel information from the screen memory and sending it to the liquid crystal display is provided, the color signal after the recombination process is temporarily stored in the screen memory, and the buffering action of this screen memory ensures a long display time. The display quality can be kept good. Also, the screen memory has a relatively small storage capacity of only one screen, and since the display information transfer to the liquid crystal is slow, the image does not flicker, and one screen can be read in the writing time for one screen. There is no unnaturalness in the image.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the image display device according to the present invention.
FIG. 4 is a timing chart of the main part, FIG. 3 is a block diagram of a screen memory peripheral area, and FIG. 4 is a color pattern explanatory view. (1) (10) …… Liquid crystal display, (2) (20) …… Liquid crystal drive circuit, (3) (3) (30a) (30a) (30b) (30b)
(30c) (30c) ... Screen memory, (4) ... Memory control means, (5) ... Image processing circuit, (6) ... Selection means.

Claims (3)

[Claims] 1. A liquid crystal display comprising a dot matrix,
A screen memory that can store one screen of pixel information corresponding to the dots of the liquid crystal display, and the color signals of the sequentially sent video signals are sent to the screen memory in the same order as the previous period for each horizontal period. Selection means for selectively executing recombination in a predetermined order different from the above and sending to the screen memory, and pixel information output from the selection means is written to the screen memory, and pixel information is read from the screen memory in synchronization with the writing. An image display device, comprising: a memory control means for sending out to a liquid crystal display. 2. The selecting means comprises a signal gate circuit for selecting the order of the color signals of the video signal, and a gate selecting means for designating and switching the signal gate circuit. The image display device according to claim 1. 3. The liquid crystal display has upper and lower screens separated from each other in terms of operating conditions, and the memory control means uses write → upper screen read →
The image display device according to claim 1, wherein alternate writing / reading control of the screen memory is performed with writing → lower screen reading as one cycle.