JPH0763095B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a MOS type resonant tunneling element.

[Technical background of the invention and its problems]

Conventionally, in compound semiconductor devices, wells and barriers of potential are artificially created in a crystal by using a technique such as molecular beam epitaxy (MBE), and a resonance tunnel (Resona
We have realized a device with negative resistance by using a phenomenon called nt tunneling).

FIG. 8 shows an example of such a device. In other words, on the n-type GaAs substrate 201, for example, Alx having a thickness of about 50Å
The structure is such that Gal-xAs (X30%) 202, 204 and GaAs layer 203 are sequentially stacked, and an n-type GaAs layer 205 is further stacked. A
Since the band cap of lxGal-xAs is larger than that of GaAs, the band structure is as shown in FIG. 8 (b). In the figure, only the lowest energy level of the conduction band is shown, which corresponds to the potential for electrons. The GaAs region 203 has two potential barriers 202,2.
It is a potential well sandwiched by 04, and according to quantum mechanics, the energy level of the electrons confined in such a potential well is E ₁ , E ₂ …… as shown in the figure.
Is known to take discrete values. The interval between such discrete levels is inversely proportional to the square of the well width W, and is about 100 mV when W is about 50 Å.

When a voltage is applied between 201 and 205 of such a layer structure, as shown in FIG. 8 (c), when one of the energy levels of the region 203 exactly coincides with the energy level of 201, electrons are emitted. Flows from 201 to 205. This is a phenomenon called resonant tunneling. The current-voltage characteristic of such a device is shown in FIG. Here, V ₁ and V ₂ are the levels of E ₁ and E ₂ , respectively.
It is a bias voltage that matches the level of 201. As is clear from the figure, the current-voltage characteristic of this device shows a large non-linearity and has a negative resistance.

Such a device exhibiting negative resistance can be used for a high frequency oscillator and the like. However, since the resonant tunneling device made of a layered structure is formed in the vertical direction with respect to the surface of the semiconductor substrate, it is difficult to draw out the wiring from the GaA2 layer (eg 201) formed in the deep part, It was difficult to achieve high integration. Therefore, realization of a resonant tunneling element that allows a current to flow in the direction along the surface of the substrate is desired. Further, since this element is a two-terminal element, it is difficult to form a logic gate, and thus the application range is limited.

[Object of the Invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device in which a current due to a resonant tunneling phenomenon is caused to flow along the surface of a substrate and the current can be controlled by the third electrode.

[Outline of Invention]

A semiconductor device according to the present invention has source / drain regions formed on a main surface of a semiconductor substrate and spaced apart from each other and formed of a material exhibiting metallic conductivity. The substrate region between the source / drain regions has a source / drain region. A potential barrier is formed between the drain region and the Schottky barrier to form a potential well, and the carrier electrode energy level is controlled by the gate electrode provided on the substrate to cause a current due to a resonance tunnel between the source and drain regions. It is characterized in that it is made to cause.

[Advantages of the Invention] According to the present invention, a three-terminal element in which a resonant tunneling current can be passed in the direction along the substrate surface and the current can be controlled by the third electrode has been realized. As a result, high integration has become possible, and high-level logic functions can be realized with a minimum number of elements, resulting in high integration and high speed.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 (a) is a structural sectional view showing a first embodiment of the present invention. For example, the acceptor concentration is 10 ¹⁵ -10 ¹⁶ cm
^-For example, a thickness of 1000Å on a P-type silicon substrate 101 of about ^-3
Source 10 consisting of about platinum silicide (ptsi)
2. The drain 102 'is provided separately from each other. In addition, the channel length L is 0.1 μm or less, for example 0.05 μ, through the gate insulating film (SiO ₂ ) 103 having a thickness of about 100 to 300 Å.
m electrodes 104 are provided. This gate electrode is, for example,
N-type polysilicon is used. Reference numerals 105 and 105 'denote interfaces between ptSi (102, 102') forming the source / drain and the substrate 101. In this portion, a potential barrier for holes, which is a so-called Schottky barrier, is formed, which is positive with respect to the substrate. When a potential is applied to the source / drain, this barrier becomes high and no current flows between them. Then, a CVD SiO ₂ film 107 is provided on the surface, and barrier metal layers 109 and 109 ′ and Al wirings 108 and 108 ′ are connected to the source / drain 102 and 102 ′ through contact holes. Here, the barrier metal layers 109 and 109 'are made of, for example, Ti-
The alloy of W is used to prevent the alloy reaction between Al and PtSi.

The energy bands of the electrons on the surface of the silicon substrate of this device are schematically shown in FIGS. 1 (b) to (e). That is, the state where the source (102) and the drain (102) are set to substantially the same potential and the gate (104) is given a positive potential is shown in (b) to (d), and (e) is The case where a potential sufficiently higher than that of the source is applied to the drain is shown. FIG. 1 (b) shows a state where the gate voltage V _G is equal to the flat band voltage. 102b and 102b are the Fermi levels of the source / drain, and 106b is the Fermi level of the silicon surface region 106. Also, 106b 'and 106b "are shown at the bottom level of the conduction band and the top level of the low electron band of the silicon surface region 106, respectively.

FIG. 1 (c) shows the gate voltage as a threshold value V of a normal MOSFET.
_It shows the case where it is equal to _TH . A normal MOSFET means a device in which the source / drain portions are formed of N-type silicon instead of PsSi in FIG. 1 (a). In this device, no current flows between the source and drain even if V _G = V _TH . The reason will be described below.

The channel region 106 is the source / drain region (102,102 ')
Are separated by potential barriers (Schottky barriers) 105c, 105'c formed at the interfaces 105, 105 'of PtSi and Si. Further, since the distance L between the potential barrier is 0.1 μm or less, the electron levels in the region 106 are discrete as shown by E ₁ , E _{2 in} FIG. ing.

The position Eg of each level measured from the bottom of the well changes depending on the channel length L, and the approximate calculation shows that the position Eg ₁ of E ₁ at L = 0.05 μm is 1.1 meV. The following table shows other examples.

For the above reason, even if V _G = V _TH , the energy level E ₁ of the electron at the bottom is higher than the Fermi level 102C of the source, and no electron is injected. Therefore, the source
No current flows between the drains. Figure 1 (d) shows V _G > V
_{In the TH} state, it is equivalent to the so-called diving deblation state. In this figure, V _G = V _G1 , exactly E _1, and the Fermi level 102d of the source coincide with each other.
At this time, a slightly positive voltage (V _D
If V _S ) is added, a current due to the resonance tunnel phenomenon flows from the source to the drain. Drain voltage is
If it is sufficiently higher than the source, it becomes as shown in Fig. 1 (e), and the electron level 1 of the source is lower than the gate voltage lower than V _G1.
Resonant tunneling current can be made to flow by matching 02e with E ₁ .

The current-voltage characteristics of such an element are shown in FIG.

The characteristics of FIG. 2 are largely different from those of the conventional element shown in FIG. 9 in the following points. That is, the conventional element is a two-terminal element and exhibits a negative resistance with respect to the voltage applied between the two terminals. However, in the element according to the present invention, the voltage applied to the gate electrode which is the electrode of FIG. The current flowing between the source and the drain is controlled by, and a negative region appears in the mutual conductance gm = (∂I _D / ∂V _G ).

FIG. 3 shows an example of a method for manufacturing the element shown in FIG. First, as shown in FIG. 3A, a silicon substrate 301
A gate electrode 303 processed into a predetermined shape is formed on the gate oxide film 302. For this gate electrode, for example, polysilicon heavily doped with phosphorus (10 ²⁰ to 10 ²¹ cm ⁻³ ) is used. The width of the gate electrode, that is, L is, for example, about 500Å, that is, 0.1 μm or less. Next, as shown in FIG. 3 (b), when oxidation is performed in a wet oxygen atmosphere at 850 ° C., while the oxide film 304 of 200 to 300 Å is grown in the region where the impurity concentration on the surface of the silicon substrate 301 is relatively low. , Polysilicon 303 containing a high concentration of phosphorus has 1000 on the surface.
A thick oxide film 305 of ~ 1500Å grows. Then, the entire surface is etched with a dilute HF solution or the like to etch the oxide film by 300 to 400 Å to obtain a structure in which only the surface of the polysilicon 303 is covered with the oxide film 305 '(FIG. 7C). When Pt (platinum) is vapor-deposited at 500Å and annealed at 550 ℃ for about 15 minutes, the exposed silicon surface 306,30
Approximately 1000 Å of PtSi 307, 307 'is formed only on 6'.
Then, if unreacted Pt is removed with, for example, aqua regia, the structure of FIG. 3 (d) is obtained. CVD SiO ₂ (10
7), TiW layer (109), Al (108), etc. are sequentially formed to complete the device of the present invention shown in FIG. 1 (a).

FIG. 3e shows a plan view of this device. The shaded area in the figure
The source / drain regions of PtSi are shown. Further, 308 is a field region, and 309 is a contact hole portion. However, Al wiring is not shown in this figure.

In the above example, only the source / drain of Pt silicide was explained, but it is not limited to this material, and any other silicide or metal thin film can be used as long as it is a material that forms the Schottky barrier as shown here. It goes without saying that it is okay.

FIG. 4 shows a second embodiment of the present invention and an example of its manufacturing method. In the same figure (a), the SiO ₂ film 405 is formed on the surface of the polysilicon gate electrode by, for example, 200 to 200 by the same process as the embodiment of FIG.
300Å Shows the formed state. Next, the silicon surface is anisotropically etched by RIE to form trenches 406 and 406 'in the source / drain regions as shown in FIG. 4 (b).
Then, by the same method as the example of FIG.
Are formed only on the exposed portion of the silicon surface to serve as the source / drain. At this time, if the thickness of PtSi is set to 1500 to 2000Å, the interface 408, 408 'between Ptsi and Si comes to the position 700 to 1000 inward from the original silicon surface, so that the side wall of the silicon groove (406, 406'). In the portions 406b and 406b ′, the interfaces 409 and 409 ′ between PtSi and Si are formed so as to penetrate under the gate electrode 403. This structure has the following advantages over the structure shown in FIG.

That is, in the structure of FIG. 1 (a), the edge of the gate electrode 104 is separated from the edge of PtSi 102, 102 ', so that the width of the potential barriers 105c, 105c' of FIG. There was a problem that the value decreased, but this was solved in the structure of FIG. 4 (c), and a sufficiently large resonance tunnel current was obtained.

The etching of the Si substrate in this embodiment is described only for the case of vertically etching using RIE, but this may be etched with a taper angle. Needless to say, isotropic etching may be used.

Now, such a device has a very wide range of new applications. An example thereof is shown in FIG. FIG. 5 (a) shows the element of the present invention in abbreviated symbols, and FIG. 5 (b) shows
A circuit combined with a load resistor is shown. Fig. 5 (b)
As shown in Fig. 5 (c), V _{G1 is} input to point A of the circuit
If an AC signal of frequency f is applied to the bias voltage of
The output waveform appearing at point B is as shown in FIG. 5 (d). It can be seen that the output waveform has a frequency of 2f. That is, the circuit of FIG. 6 (b) is a circuit having an advanced function of frequency multiplication, although only one active element is used.

Here, as described above, the level of E ₁ is affected by the drain voltage. FIG. 6 shows that when V _D is substantially equal to the source potential (V _D V _S ), when V _D is sufficiently larger than the source (V _D >
V _{S −} ) shows the respective V _G −I _d characteristics.

The operation of the circuit shown in FIG. 5 will be described with reference to FIG.
First, it is assumed that the input terminal A is Low and the output terminal B is High. When the potential of the terminal A gradually rises and approaches V _G1 which causes a resonant tunnel of E ₁ when V _D > V _S , a current flows,
The potential of the output terminal B starts to drop. When the gate voltage further rises and becomes equal to the gate voltage V _G1 which causes a resonance tunnel in V _D V _S , the output B is at the lowest level, that is, L.
reach ow. Next, the potential of A rises higher than V _G1 and V _G V _G1 ″
Then, the current decreases again and the output B becomes High. After that, since the forward and reverse operations are periodically repeated, frequency multiplication as shown in FIGS. 5C and 5D is performed.

FIG. 7 shows another application example of the device of the present invention. That is, the gate electrode (FIG. 1 (a), 104) of this device is used as the floating gate 601, and two control gates 602, 603 are connected in terms of the floating gate capacitance.
This is a circuit with one load resistance (Fig. 7b) using an element (Fig. 7a) having a. Here, the two control gates 602 and 603 are connected to the floating gate 601 with the same capacitive coupling coefficient. FIG. 6 (c) shows
The output voltage of the circuit of FIG. 6B is shown as a function of the floating gate potential V _F. Here, V _G1 is equal to the gate voltage which gives the peak of the resonant tunneling current shown in FIG.

Now, the input voltage V _A , V _B entering the A, B2 terminals is high level (H)
And low level (L). If the device is designed so that V _F = V _G1 when only one of them is H, then V _F > V _G1 when V _A = V _B = H and when V _A = V _B = L V _F <V _G1 , and in either case V _C can be H. Figure 7 (d) shows shows a relationship between V _A, V _B and V _C, V _C is in a result of taking an exclusive OR of V _A and V _B.

Up to now, at least 7 to 8 active elements were required to form an exclusive OR with a MOS or bipolar element, but with the element of the present invention, only one such advanced logic is required. I was able to realize the function.

In addition, the basic structure of this device is very similar to that of MOSFET, and the structure is such that the resonant tunneling current flows in the surface direction of the semiconductor, so the circuit layout is simple and no extra lead wiring is required. It has characteristics that are extremely advantageous for high integration. Not only that, a circuit that previously required a large number of elements can be realized with a small number of elements, so power consumption is reduced, and since the number of wires that connect the elements is also reduced, delays in wiring are reduced and circuit speed is increased. Can be realized.

Further, since this element can be formed on a silicon substrate, it can be combined with a SiMOS / LSI formed on the same substrate to realize a circuit having more advanced functions.

In the above-mentioned embodiments, only the structure using the P-type substrate is described, but of course, the N-type substrate may be used. Also P
Needless to say, the impurity concentration of the mold may be out of the range shown in the embodiment. Further, the surface of the substrate may be channel-doped with impurities of the same conductivity type or the opposite conductivity type of the substrate. Further, although the electrode material of the gate is described only in the case of polysilicon, in any of the embodiments,
Of course, a material such as metal or silicide may be used. Although PtSi has been taken as an example of the material for forming the Schottky barrier, metal films such as Pt, Pd, Ni, Mo, W, Nb, Ta, and Ti,
You may use these silicides. A similar structure may be formed by using AlxGa _1-x As, InSb, or another compound semiconductor substrate. Furthermore, MIS structure (metal-insulating film-
A gate electrode structure other than a semiconductor) may be adopted. That is, a Schottky gate structure in which a metal or a silicide is directly provided on the semiconductor substrate may be adopted.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is an operation characteristic diagram thereof, FIG. 3 is a diagram showing a manufacturing method example, FIG. 4 is a diagram showing another embodiment and a manufacturing method example, and FIG. Shows an application example, FIG. 6 shows a characteristic diagram thereof, FIG. 7 shows another application example, FIG. 8 shows a conventional example, and FIG. 9 shows its characteristic diagram. In the figure, 101,301,401 ... P-type semiconductor substrate 102,102 ', 307,307', 407,407 '... Pt silicide region

Claims (3)

[Claims] 1. Sources spaced apart from each other on a main surface of a semiconductor substrate.
In the substrate region between the source and drain regions, a potential barrier is provided between the source and drain regions to form a potential well, and a potential well is formed in the substrate region between the source and drain regions. An energy level is controlled to generate a current due to a resonance tunnel between the source / drain regions, and the source / drain regions are formed of a material exhibiting metallic conduction,
Further, the semiconductor device is characterized in that a potential barrier by a Schottky barrier is formed between the material and the substrate region. 2. The shortest distance between the source and drain is 0.1.
The semiconductor device according to claim 1, wherein the semiconductor device has a thickness of not more than μm. 3. The material forming the source / drain is
The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to partially overlap with the gate electrode in a region below the gate electrode.