JPH0764096B2 - Recording device - Google Patents

Description

The present invention relates to a recording device, and more particularly to a recording device in which variations in characteristics existing in a dot output section are corrected.

[Prior Art] There are various printer heads that obtain an output image in a dot representation format. Specific examples include a wire printer head, an electrostatic printer head, an ink jet printer head, a thermal printer head, an LED array printer head, and the like. Among them, LED is 1mm as dot generating element
LED array printer heads in which eight to several tens of LEDs are lined up have been attracting attention in recent years because they can obtain extremely high resolution.
If this is used in place of the optical scanning mechanism of the conventional electrophotographic copying machine, the LEDs lined up in a straight line are selectively turned on according to the video signal, and a latent image is formed on the surface of the photoconductor almost in contact with this. Further, it is possible to configure a printer device that obtains a visible image through the processes of development and transfer to paper. It is known that in such a printer device, a portion where the LED is turned on can be made into a black visible image or a white visible image by changing the charging condition and the toner.

FIG. 1 is a circuit diagram showing a conventional LED array printer head drive circuit. In order to print out one screen image, there are a main scan in which LEDs arranged in a straight line are electrically scanned, and a sub-scan in which a photosensitive surface is moved in a direction perpendicular to the main scan. In the figure, the data enable signal "DATA-EN"
Numeral 7 gives a synchronization to this main scanning and a video signal "VIDE".
Determines the period during which the O "5 is effectively printed. Specifically, when the data enable signal 7 goes to 1, the counter 1 and the decoder 4 are energized. The counter 1 starts counting the main scanning clock signal "CLK" 2 and outputs a count value output signal 3. At the same time, the decoder 4 outputs this output signal 3
The latch pulse signals 41 to 4n are output in the order of the values 0 to _{n- 1} . On the other hand (hereinafter referred to as latch) La Tutsi prefectural Pufu Rotsu flop FF ₁ is in to ff _n data input terminal D is inputted in common video signal 5, Ratsuchiparusu signal 4 ₁ to 4 _n is this in a predetermined order Sampled and stored in each latch FF _{1 to} FF _n . The LED array printer head 6 has n light-emitting elements LED ₁ ～LED _n are adjacent.
The drivers D _{1 to} D _n that drive these individually are LEDs ₁ to
This is for controlling on / off of the current flowing through the LED _n . For example, when the latch FF ₁ stores a dot pixel signal of ₁ , a current is passed through the LED ₁ to cause it to emit light, and
When the dot pixel signal in which FF ₁ is 0 is stored, the current of LED ₁ is cut off to erase it. R _{1 to} R _n are current control resistors of LED ₁ to LED _n . In such a configuration, when main scanning printing is performed, the photosensitive surface is also sub-scanned.
At this time, since the latches FF _{1 to} FF _n hold the stored dot pixel signals in the next main scan until the latch timing, this holding time is the same for all LEDs. Then, if the sub-scanning is performed for a predetermined length during this period, a latent image for one line is formed on the photosensitive surface. When this is developed and transferred to paper, a visible image consisting of black in the areas exposed to the LED and white in the areas not exposed to the light is obtained.

However, even if the same current is applied to the LEDs, the brightness of the emitted light varies. At present, this variation is remarkable for each LED. Therefore, as in the prior art,
When these LEDs are driven in a fixed form, it is not possible to prevent uneven density in the visible image of the printed result due to uneven light emission of the LEDs. Moreover, this phenomenon is not unique to the configuration using the LED array printer head. For example, in the case of the wire printer head that is now widely used, it is a phenomenon that naturally occurs if the pin head mechanism is worn or the electrical characteristics of the actuator are not uniform. However, in the wire dot printer, since the number of dots in the dot is small and the accuracy of the output image is not required so much, it is often the case that this has been solved by the adjustment of an expert. However, in applications where the number of output dots is enormous and the output image is also required to have high accuracy, this variation in characteristics cannot be ignored. In addition, the LED array printer head configured with a high density cannot replace the dot elements having non-uniform characteristics, which causes a so-called poor yield. In order to deal with this, a method of connecting LED array printer heads of an appropriate length to each other can be considered. However, even in this case, some effect is expected from the viewpoint of yield. It is also possible to match the currents flowing through the LEDs, but since the number of LEDs is enormous, it is usual that the current control resistors also consist of array resistors, so this method is also impractical.

[Problems to be Solved by the Invention] In view of the above problems, the present invention highly accurately improves density unevenness due to variations in characteristics of a plurality of recording elements by repeatedly using less than the number of recording elements. It is an object of the present invention to provide a recording device that can do this.

[Means for Solving the Problem] In order to achieve such an object, the recording apparatus of the present invention is driven according to a given digital image signal and has n groups each of which has m elements (n × m) recording elements (n and m are integers of 2 or more), input means for inputting a digital image signal, and the (n × m) recording elements, each group consisting of m elements. A driving circuit that sequentially drives each group and repeats the orbital operation for each group at least n times; a timing circuit that forms a timing signal from a clock synchronized with the input digital image signal; and (n × m) In order to correct the variation in the driving characteristics of the recording elements, the driving time correction value for each element is read from the memory and the memory that stores the (n × m) recording elements respectively. Had m A correction circuit that sequentially corrects the drive time of the storage element by the drive circuit for each group according to a positive value in response to the timing signal, and repeats the correction operation for each group at least n times, and according to the timing signal. And a switching unit that switches a group of storage elements driven by the drive circuit at least n times.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a circuit diagram showing the LED array printer head drive circuit of the first embodiment. Here, the same reference numerals or symbols are attached to those having the same functions as those shown in FIG. Other configurations will be described below. In the figure, 8 is a memory which outputs the data D ₀ , D ₁ for time control using the output signals 3 _{1 to} 3 ₃ (count value) of the counter 1 as an address input, and 9 is the read data D ₀ , from the memory 8. Main scan clock signal 2 only for the time until D ₁ becomes sufficiently stable
Delay circuit to delay the delay time, 10 ₁ to 10 ₄ are AND gates A _{1 to} A ₄
Is a time control circuit for alternately controlling the LED _{1 to} LED ₄ and LED _{5 to} LED ₈ groups via LED, and individually controlling the lighting time of the LEDs therein. The individual lighting time is set by the latch pulse signal.
4 ₁ to 4 ₄ are obtained by a configuration in which the common read data D ₀ and D ₁ from the memory 8 are sequentially set to the time control circuits 10 ₁ to 10 ₄ . In the embodiment, eight LED elements are divided into two groups of four. This is a structure for convenience of explanation, and it is practical to control n LED elements for m groups. The output Q _{2 of the} counter 1 is the upper bit of the count value. Therefore, the period when the count value is 0 to 3 becomes the LO level and the period when the count value is 4 to 7 becomes the HI level. This state is shown in the operation timing chart, "Q ₂ ", shown in FIG. While the output Q ₂ is LO, the output of the inverter driver 11 becomes HI and the transistors Tr ₁ and Tr ₂ are turned on. In this case LED ₁ ~LED ₄ is by connexion lighting control to the driver D ₁ to D _4. Further, while the output Q ₂ is HI, the output of the driver 12 becomes HI and the transistors Tr ₃ and Tr ₄ are turned on. At this time, lighting of LEDs _{5 to 8} is controlled by drivers D _{1 to} D ₄ . Since the count value of the counter 1 is counted from 0 to 7, the memory 8 which receives the output signals 3 ₁ to ₃ 3 of this count value as an address input outputs unique read data to the LEDs _{1 to 8} Become.

The Figure 4 shows a circuit configuration example of a time control circuit 10 _1. The same applies to the other 10 ₂ to 10 ₄ . In the figure, input signals to the down counter 101 are read data D ₀ and D ₁ from the memory 8 for initializing the count value, a latch pulse signal 4 ₁ for selectively energizing the initial setting, and the read data. This is the delayed clock signal "DCLK" that waits for the output to stabilize sufficiently and then actually gives the initial setting timing. This delayed clock signal is also a clock signal when the down counter 101 performs the reverse counting later. Unless the value of the initial setting is not "0" the output terminal Q _A, 1 of the signal to any one of Q _B is output. At this time, the output signal of the NOR gate 102 is 0,
The reverse count energizing terminal T of the down counter 101 is energized. Further, the signal Q of 1 inverted by the inverter 102 is the time control circuit 1
It is output from 0 ₁ . Further, the counter starts counting from the next delayed clock signal of the down counter 101, and when the count value reaches "0", the signals at the output terminals Q _A and Q _B both become 0, and the NOR gate 102 The output signal becomes 1. At this time, the reverse counting energizing terminal T of the down counter 101 is deenergized and the subsequent counting operation is stopped. At the same time, the output signal Q of the time control circuit becomes 0, and this state is maintained until the next initialization is performed.

The circuit operation of FIG. 2 will be described below in accordance with the operation timing chart of FIG. The main scanning clock signal "CL
The phase of K'2 and the delayed clock signal "DCLK" delayed by a predetermined time are shown. Main scanning is performed in synchronization with the data enable signal "DATA-EN" 7 and the 1st and 1 + 1th.
The second main scan is shown. Video signal "VIDE
"O" 5 is 1,0, when it says about the 1st main scan.
It is an 8-dot pixel signal of 0,0,0,1,1,1 and can be read in the same manner for the 1 + 1th pixel after one clock interval. In the embodiment, the case where a black visual image is obtained for a video signal of 1 and a white visual image is obtained for a video signal of 0 is shown. Ratsuchiparusu signal ₄₁ to ₄ to the output lower bits obtained by decoding the counter 1 is obtained by twice during the main scanning. And subjected the relationship between Ratsuchiparusu signal ₄₁ to ₄ and the counter 1 counts the drawings. The output upper bit Q ₂ of the counter 1 is addressed to the upper bit of the memory 8 so that the read data D ₀ and D ₁ have eight unique values during the main scanning period. Also, the output higher bit Q ₂ of counter 1 is LED ₁ to LED ₄
And LED ₅ to LED ₈ are time-divisionally activated, so LED _{1 is} eventually
~ LED ₈ will receive its own time control.

Specifically, the latch FF ₁ stores the video signal “VIDEO” at the rising edge of the first latch pulse signal 4 ₁ ,
The output signal "FF ₁ -Q" becomes 1 at this point. The output signal of the latch FF ₂ "FF ₂ -Q" The first Ratsuchiparusu signal
4 The _second rise is zero. On the other hand, the time control circuit 10 _1,
To a time selected by the first Ratsuchiparusu signal 4 ₁ reads data D 0 address of memory 8 _0, D ₁ is initialized. The timing for the actual setting is the delayed clock signal "DCLK".
The output signal "10 ₁ -Q" of the time control circuit 10 ₁ becomes 1 at this time. Also in the same manner time control circuit 10 _{and second} output signal "10 ₂ -Q" becomes 1 during a period which is selected in the first Ratsuchiparusu signal 4 _2. In the embodiment, since the brightness of LED ₁ is weak, its initial setting value is set to 3, and other values are set.
The brightness of LED _{2 to} LED ₈ is standard, and its initial setting value is 2. Down counter 101 in the time control circuit
The count value of the delay clock signal "DCL
It is decremented by 1 each time "K" occurs. Therefore, its output signal "1
"0 ₁ -Q" returns to 0 at the rising edge of the third delayed clock signal, and the output signal "10 ₂ -Q" returns to 0 at the rising edge of the second delayed clock signal, and the following initial settings are made respectively. Up to 0
Hold the level of. The next default setting is performed in each second Ratsuchiparusu signal 4 _1, 4 _2. As described above, in the device of the embodiment, the main scanning period is divided into two, and the same time control circuit is used for controlling the drive time of different LEDs. Therefore, the maximum controllable time is 1/2 main scanning period.
In other words, this 1/2 main scanning period is determined with the shortest condition such that the photosensitivity is sufficiently exposed, at least within this period. The same applies to the case of multi-division. And gate
Since the A ₁ output of latch FF ₁ and the time control circuit 10 ₁ is input, and when the output of the latch FF ₁ is 1 gate A
The output of ₁ is subject to the time limit. During the period when it is the output of the AND gate A _1, the driver D ₁ is energized and the current flows through the LED ₁ . On the other hand, since the output of the latch FF ₂ is 0, there is no time limit in this case. It can be seen that the output of the latch FF ₂ is limited in time only when the lighting of the LED ₆ is controlled. In this way, when the LED ₁ is that it is lit, and emits light at all times 3 periods of the clock component to the luminance is low, also the other LED ₂ ~LED ₈ always Therefore luminance relatively strong It emits light for a period of two clocks. Of course, this time control may be complementary control. Complementary control is 1/2 in terms of the embodiment.
This is the control that determines the time during which the LED is not turned on during the main scanning period. Specifically, the period of 1/2 main scanning is 4
There clock component, LED ₁ is the period of de-energizing the lighting for the luminance weak one clock worth. LED ₂ ~
Since the brightness of LED ₈ is relatively strong, the period for turning off the lighting is 2 clocks. Therefore, the data 1 is read from the address 0 of the memory 8 and the data 2 is read from the addresses 1 to 7. To change the embodiment to such a configuration, the output lines of the time control circuit 10 ₁ to 10 ₄ may be taken from the output terminal Q of Figure 4. Further, whether the drive time is controlled by any of the above-mentioned methods is considered under the condition that the number of data read bits of the memory 8 is minimized.

The purpose of the embodiment is to obtain a uniform dot photosensitive image on the photosensitive surface as a result of such individual control of the lighting time. If control is assumed such that sub-scanning is stopped during the main scanning period, controlling the light emission time of the LED has the effect of making the photosensitive amount of the unit photosensitive surface uniform.
Further, under the control such that the sub-scanning is simultaneously performed, a difference in the size of the exposed area occurs as a result, and when the visible image is viewed macroscopically, it is possible to use the effect that the density is made uniform.

As described above, effective correction with a simple configuration which is the object of the present invention can be shared by controlling a plurality of LED array printer heads having an appropriate number of elements in a matrix. The purpose is to significantly reduce the number of circuits (LED driver, time control circuit, etc.). In this way all LEDs stored in memory 8
At the same time, all of the correction data of
An inexpensive printer head drive device in which the number of elements of circuits that can be shared is extremely small is realized.

The image quality of the visible image was improved by the configuration and control of the embodiment described above. It is also obvious that the control of the driving time can be applied to the other printer heads described in the prior art. In FIG. 2, the data write line 13 is connected to the memory 8 from a microcomputer (not shown).
It shows a configuration capable of writing data to the. Of course, I wrote the correction data for each head.
When the ROM is used as the memory 8, the data write line is unnecessary. Not only in the LED array printer head, but also in other printer mechanisms and printer elements, it is inevitable that their characteristics change with time. According to the present invention, as a means for easily correcting such a change in characteristics,
The memory 8 may be provided so that the contents can be easily rewritten via a microcomputer or direct manual operation. With such a configuration, it is possible to correct the above-mentioned change with time and to add +1 to the entire contents of the memory 8.
Alternatively, it is possible to easily increase or decrease the density of the visible image by performing uniform processing such as -1.

[Effect of the Invention] According to the present invention, when (n × m) recording elements are driven for each group of m elements,
m) A digital image signal, in which a driving time correction value for each element for correcting the variation in the driving characteristics of the recording elements is read out from the memory for each group and sequentially input from the input means by the correction value. The driving time of the recording elements is corrected at the timing synchronized with the above, and the corrected driving for each group of m elements is repeated at least n times to correct the (n × m) recording elements. Since the driving is realized, it is possible to highly accurately improve the density unevenness due to the variation in the characteristics of the plurality of printing elements by using the correction circuit and the driving circuit having a configuration smaller than the number of printing elements.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a conventional LED array printer head drive circuit, FIG. 2 is a circuit diagram showing an LED array printer head drive circuit according to an embodiment of the present invention, and FIG. 3 is an implementation shown in FIG. An operation timing chart of the LED array printer head drive circuit of the example, and FIG. 4 is a block diagram showing an example of the time control circuit configuration. Here, 1 ... Counter, 2 ... Main scanning clock signal,
3 ... Count value output signal, 4 ... Decoder, 4 ₁ to 4 _n ...
Latch pulse signal, 5 ... Video signal, 6 ... LED array printer head, 7 ... Data enable signal, 8 ...
... Memory, 9 ... Delay circuit, 10 ₁ to 10 ₄ ... Time control circuit, 11 ... Inverter driver, 12 ... Driver, 13 ...
… Data write line, FF _{1 to} FF _n …… Latch flip flop, A _{1 to} A ₄ …… And gate, D _{1 to} D _n …… Driver, LE
D _{1 to} LED _n ...... LED light emitting element, R _{1 to} R _n ...... Current limiting resistors.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-59-194875 (JP, A) JP-A-52-45825 (JP, A) JP-A-57-115358 (JP, A) JP-A-56- 127469 (JP, A) JP-A-58-48562 (JP, A)

Claims (1)

[Claims] 1. A (n × m) recording element (n, m is an integer of 2 or more) which is driven according to a given digital image signal and has n groups each consisting of m elements.
An input means for inputting a digital image signal, and the (n × m) recording elements are sequentially driven for each group of m elements, and the driving operation for each group is repeated at least n times. A drive circuit, a timing circuit that forms a timing signal from a clock that is synchronized with the input digital image signal, and each element for correcting variations in drive characteristics of the (n × m) recording elements. In response to the timing signal, the drive is performed in response to the memories that store the correction values of the drive time corresponding to the (n × m) recording elements and the m correction values read from the memory. A correction circuit that sequentially corrects the drive time of the storage element by a circuit for each group and repeats the correction operation for each group at least n times; and the drive circuit according to the timing signal. A group of memory elements driven by the road, the recording apparatus characterized by comprising a switching means for switching at least n times.