JPH0765891B2 - Optical position detector - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an optical position detecting device for detecting a spot-like optical position projected on a light detecting surface of a semiconductor optical position detecting element.

[Technical Background of the Invention and its Problems] As a conventional optical position detecting device, for example, there is one as shown in FIG. 4 (“Semiconductor position detector and its application” Electronic Material, February 1980, p119).

In FIG. 4, reference numeral 1 denotes an optical position detecting element, which has a p-type layer 3 formed on the surface of an n-type Si substrate 2 having a high specific resistance to form a photodetecting surface by a pn junction. The light detection surface is formed in a rectangular shape in plan view.

On the p-type layer 3, electrodes 4 and 5 for taking out the _first photocurrent I ₁ and the second photocurrent I ₂ , respectively, are provided at two positions separated by an interval length 1 along the two opposite sides. Are formed.

On the other hand, on the back surface of the Si substrate 2, an n ⁺ layer (not shown) serving as a contact layer is formed on the entire surface, and the electrode 6 is formed on the entire surface or a part thereof.

A positive voltage + Vcc is applied to the electrode 6, and the pn junction on the photodetection surface is reverse biased by this positive voltage + Vcc.

In order to process the _first and _second photocurrents I ₁ and I ₂ extracted from the respective electrodes 4 and 5, the optical position detection element 1 is further connected to a signal processing circuit including the following devices. Has been done.

That is, 71 and 72 are current-voltage conversion circuits, 73 is an addition circuit, 74 is a subtraction circuit, and 75 is an inverting circuit. Each of these devices is mainly composed of an operational amplifier.

Reference numeral 76 is a general-purpose divider, and 77 is a DC / DC converter. The DC / DC converter 77 obtains + Vcc voltage and −Vee voltage for driving the divider 76 and the like.

Then, x between the electrodes 4 and 5 of the optical position detecting element 1
Assuming that spot-shaped light is projected at the position (0xl), the first photocurrent extracted from each of the electrodes 4 and 5.
I ₁ and the second photocurrent I ₂ relatively change according to the light projection position x, and are respectively represented by the following equations.

I ₁ = I ₀ · (l−x) / l (1) I ₂ = I ₀ · x / l (2) where I ₀ is the total photocurrent generated by light irradiation (I ₁ +
Equal to I ₂ ).

The first and second photocurrents I ₁ and I ₂ are the current-voltage conversion circuit.
At 71 and 72, they are converted into voltages of Rf · I ₁ and Rf · I ₂ , respectively.

In the adder circuit 73, both voltages Rf · I ₁ and Rf · I ₂ are added, and this is inverted by the inverting circuit 75 to obtain the sum voltage Rf · (I ₁ +
I ₂ ) is made.

On the other hand, in the subtraction circuit 74, the difference between the two voltages Rf · I ₁ and Rf · I ₂ is calculated to generate the difference voltage Rf · (I ₂ −I ₁ ).

In the divider 76, the difference voltage Rf · (I ₂ −I ₁ ) becomes the sum voltage Rf ·
It is divided by (I ₁ + I ₂ ), and an output like the following equation is obtained.

(Vref / 2) · (I 2 -I 1) / (I 1 + I 2) = [(x / l) -1/2] · Vref ... (3) Vref herein is the constant reference voltage.

In this way, the position signal that does not depend on the light irradiation amount is obtained from the divider 76, and the light projection position x is detected.

However, in the above optical position detection device, the signal processing circuit requires current-voltage conversion circuits 71, 72, an addition circuit 73, a subtraction circuit 74, and an inverting circuit 75, which are operational amplifiers for sum / difference calculation. General-purpose divider 76 and + Vc
Since the DC / DC converter 77 that generates the c voltage and the −Vee voltage is required, the number of devices and the number of parts cannot be reduced to make the device compact, resulting in high cost and reduced reliability. There was a problem of inviting.

[Object of the Invention] The present invention has been made based on the above circumstances, and an object of the present invention is to provide a light position detection device which can be compactly configured, has improved reliability, and is inexpensive. .

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a surface layer of a semiconductor substrate region of one conductivity type and a layer of opposite conductivity type, which forms a bonding layer serving as a photodetection surface. An optical position detection element having electrodes for taking out first and second photocurrents that relatively change according to a light projection position between the two positions at two positions separated from each other; A first current corresponding to the photocurrent, a second current corresponding to the second photocurrent, and a first current obtained by adding the first current to twice the current of the second current.
And a current conversion means for generating a second sum current obtained by adding a second current to a current that is twice the first current and the first and second currents and the first and second currents. Logarithmic conversion means for logarithmically converting the sum current and outputting it as a voltage,
A first differential pair that differentially amplifies a voltage obtained by logarithmically converting the first current and a voltage obtained by logarithmically converting the first sum current to generate a first differential output current and a second differential output current. A circuit and a second logarithmic-converted voltage of the second current and a second logarithmic-converted voltage of the second sum current for differential amplification to generate a third differential output current and a fourth differential output current. By having a differential pair circuit and a calculation unit that calculates the current output corresponding to the light irradiation position between the two positions of the light position detection element by the first to fourth differential output currents,
The optical position detecting element and each device serving as its signal processing circuit can be integrated in one chip, and the device can be made compact.

Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 and 2 are views showing an embodiment of the present invention.

It should be noted that, in FIG. 1, the same or equivalent members and parts as those in FIG. 4 are designated by the same reference numerals as those described above, and a duplicated description will be omitted.

First, the structure will be described. In FIG. 1, 7, 8, 9, and 11 are
These four transistors 7, 8, 9, and 11 are npn transistors, respectively, and constitute a first current mirror circuit.

The transistor 7 in the first current mirror circuit is
The base and the collector are connected together, and the collector is connected to the electrode 4 in the optical position detecting element 1. The transistor 7 functions as an input transistor, and the other 3
The individual transistors 8, 9 and 11 function as output transistors. Of the three output transistors, the transistor 11 is a multi-emitter transistor having two emitters.

The first photocurrent is applied to the collectors of the output transistors 8 and 9.
A _first current I ₁ ′, which is approximately equal to I _1, is generated, and the collector of the other output transistor 11 has a current that is twice the _first current I ₁ ′.
2I ₁ ′ occurs.

The first photocurrent I ₁ and the first current I ₁ ′ are I ₁ ′ = I ₁ · Hfe / (Hfe + 5), where Hfe is the base ground current amplification factor of the npn transistors 7, 8, 9 and 11. )… (4)

With almost the same configuration as described above, four npn transistors 12, 13, 1 are provided for the other electrodes 5 in the optical position detecting element 1.
A second current mirror circuit is configured by using 4 and 15.

In the second current mirror circuit, the transistor 12 functions as an input transistor, and the other three transistors 1
3, 14, 15 function as output transistors. Of the three output transistors, the transistor 13 is a multi-emitter transistor.

A second photocurrent is applied to the collectors of the output transistors 14 and 15.
A _second current I ₂ ′, which is approximately equal to I _2, is generated, and the collector of the other output transistor 13 has a current twice the second current I ₂ ′.
2I ₂ 'occurs.

The second photocurrent I ₂ and the second current I ₂ ′ are I ₂ ′ = I ₂ · Hfe / (Hfe + 5), where Hfe is the base ground current amplification factor of the npn transistors 12, 13, 14, and 15. )… (5)

The collector of the transistor 9 in the first current mirror circuit and the collector of the transistor 13 in the second current mirror circuit are connected in common, and the common connection line receives a current 2I ₂ ′ that is twice the _second current. A first sum current (I ₁ ′ + 2I ₂ ′) is obtained by adding the current I ₁ ′ of ₁ .

In addition, the transistor in the first current mirror circuit
The collector of 11 and the collector of the transistor 14 in the second current mirror circuit are commonly connected, and the common connection line has a second current 2I ₁ ′ that is twice the _first current.
A _second sum current (I ₂ ′ + 2I ₁ ′) obtained by adding I ₂ ′ is generated.

The npn transistors 16, 17, 18 and 19 are connected to the collectors of the output transistors in the first and second current mirror circuits as current converting means, respectively.

The npn transistors 16, 17, 18, and 19 have bases and collectors connected to each other, and a positive voltage Vt is commonly applied to their connection points.

Each npn transistor 16, 17, 18, 19 utilizes the diode characteristic between its base and emitter to make the first and second currents I ₁ ′ and I ₂ ′ and the first and second sum currents (I 2). ₁ '+
2I ₂ ′) and (I ₂ ′ + 2I ₁ ′) are logarithmically converted, respectively.

The above currents are logarithmically converted and output as voltage values Va, Vb, Vc, and Vd to the emitters of the transistors 16, 17, 18, and 19.

The emitters of the logarithmic conversion transistors 16 and 17 are composed of two npn transistors 29 and 31 via a source follower composed of a p-channel JFET and constant current sources 21 and 22, 23 and 24, respectively. Is connected to each input terminal of the differential pair circuit.

The source followers 21 and 22, 23 and 24 prevent the base currents of the transistors 29 and 31 forming the differential pair circuit from flowing into the logarithmic conversion transistors 16 and 17 and causing an error. It is arranged. Therefore, the current values of the constant current sources 22 and 24 are set to be sufficiently larger than the base currents of the transistors 29 and 31 forming the differential pair circuit so that an equal voltage shift occurs between the input and output. There is. The above also applies to the source follower described later.

Voltages Va and V obtained by logarithmically converting the first current I ₁ ′ and the first sum current (I ₁ ′ + 2I ₂ ′) by the first differential pair circuits 29 and 31.
b is differentially amplified to generate the first differential output current Ia and the second differential output current Ia.
A differential output current Ib of is generated.

The emitters of the logarithmic conversion transistors 18 and 19 are p-channel JFETs and constant current sources 25 and 26, and 27 and 28, respectively.
Is connected to each input terminal of the second differential pair circuit composed of the two npn transistors 32 and 33 via the source follower constituted by.

Voltages Vc, V obtained by logarithmically converting the second current I ₂ ′ and the second sum current (I ₂ ′ + 2I ₁ ′) by the second differential pair circuits 32, 33.
d is differentially amplified to generate a third differential output current Ic and a fourth differential output current Ic.
Differential output current Id of is generated.

34, 35 and 36 are npn transistors, and the transistor 36 is
The base and collector are connected to function as an input transistor, and the other two transistors 34 and 35 function as output transistors. These transistors 34, 35,
36 constitutes a third current mirror circuit.

A positive voltage (Vst + Vbe) is applied to the collector of the input transistor 36 via the resistor Rb.

The collector of the output transistor 34 is the first differential pair circuit 2
The collectors of the other output transistors 35 are connected to the common emitter points of 9, 31 and the common emitter points of the second differential pair circuits 32, 33.

A current given by the following equation flows through the collectors of the output transistors 34 and 35.

Iref = Vst / Rb (6) Then, this current is set as the constant current Iref in the first differential pair circuits 29 and 31 and the second differential pair circuits 32 and 33, respectively.

37, 38, 39, 41 are pnp transistors, 42, 43 are resistors,
These four transistors 37, 38, 39, 41 and the two resistors 42, 43 enable a highly accurate fourth current mirror circuit 40.
Is configured.

The collector of the transistor 29 in the first differential pair circuit 29, 31 and the collector of the transistor 32 in the second differential pair circuit 32, 33 are commonly connected to the input terminal 44 of the fourth current mirror circuit 40. There is.

In addition, at the output terminal 45 of the fourth current mirror circuit 40,
The collector of the transistor 31 in the first differential pair circuit 29, 31 and the collector of the transistor 33 in the second differential pair circuit 32, 33 are connected, and the output terminal 45 thereof is
It is connected to the inverting input terminal (−) of the current-voltage conversion circuit 46 composed of an operational amplifier.

At the input side of the fourth current mirror circuit 40, the sum of the first differential output current Ia and the third differential output current Ic (Ia +
Ic) flows, and a current of the same value flows on the output side.

Therefore, the output terminal 45 of the fourth current mirror circuit 40 is
From the current (Ia + Ic) of the sum of the first and third differential output currents Ia and Ic to the current-voltage conversion circuit 46 of the next stage, from the second and fourth differential output currents Ib and Id. The current obtained by subtracting the current (Ib + Id) that is the sum of is output. As will be described later, the projection position of light is detected using this output.

Thus, the fourth current mirror circuit 40 constitutes a calculating means for calculating a current output corresponding to the light projection position from the first to fourth differential output currents Ia, Ib, Ic, Id. There is.

A positive voltage of Vst / 2 is applied to the non-inverting input terminal (+) of the current-voltage conversion circuit 46. The current-voltage conversion circuit 46 converts a current corresponding to the light projection position into a voltage and outputs the voltage.

Each of the current mirror circuits, the logarithmic conversion means, the differential pair circuits, and the like which compose the optical position detecting element 1 and the signal processing circuit can be integrated into one chip by a bipolar IC.

FIG. 2 partially shows an example of this one-chip bipolar IC, and shows a portion in which the optical position detecting element 1, the npn transistor 7 and the p-channel JFET 21 are incorporated.

In FIG. 2, 51 is a p-type Si substrate (substrate), which is a p-type
An n ⁻ epitaxial layer 52 is formed on the Si substrate 51.

the n ^- the required site of the epitaxial layer 52, a p-type impurity is selectively diffused p ⁺ isolation diffusion region 53 is formed, n ^- epitaxial layer 52 is separated by the p ⁺ isolation diffusion region 53 Island 52a, 52b, 52c are formed. 54 is a n ⁺ buried layer, such as reduction of the collector resistance of the transistor can be achieved by the n ⁺ buried layer 54.

First, the optical position detection element 1 is formed on the island 52a. N ^- epitaxial layer 52 constituting the island 52a
Corresponds to the n-type substrate region 2 in FIG.

The island 52a has two p positions separated by a required distance.
The p-type regions 55 and 56 are diffused to form the two p-type regions 55,
The p-type layer 3 is formed between 56 by ion implantation of boron (B). A pn junction between the n ^- epitaxial layer 52 forming the island 52a and the p-type layer 3 constitutes a photodetection surface.

57 is an n ⁺ contact region.

The npn transistor 7 is formed on the island 52b. In the island 52b, 58 is a p-type base diffusion region and 59 is an n ⁺ emitter diffusion region.

Further, a p-channel JFET 21 is formed on the island 52c.

A source region 61 and a drain region 62, which are a pair of p-type regions, are formed on the island 52c so as to face each other at a required interval. A p-type channel region 63 is formed by ion implantation of boron (B) between the source region 61 and the drain region 62, and n ⁺ is formed on the channel region 63.
A gate region 64 is formed.

P-type regions 55, 56, 58, 61, 62 in each island 52a-52c
Are simultaneously formed in the p-type impurity diffusion step, and the n ^{+ -type} regions 57 and 59 are simultaneously formed in the n-type impurity diffusion step.

Although only one npn transistor 7 and one p-channel JFET 21 are shown in FIG. 2, the other transistors and JFETs in FIG. It can be built in other islands, and the whole device can be made into one chip.

Next, the operation will be described.

When spot-like light is projected at the position of x between both electrodes 4 and 5 of the light position detection element 1, the electrodes 4 and 5
As shown in the equations (1) and (2), the first and second photocurrents I ₁ , whose values relatively change according to the light projection position,
I ₂ is taken out.

The first photocurrent I ₁ flows through the input transistor 7 in the first current mirror circuit, and its output transistor 8,
The first current I ₁ ′ shown in the equation (4) is generated in the collector of the transistor 9 and the second current I ₁ ′ is generated in the other output transistor 11.
Times the current 2I ₁ 'occurs.

On the other hand, the second photocurrent I ₂ flows to the input transistor 12 in the second current mirror circuit, and the collectors of the output transistors 14 and 15 of the second photocurrent I ₂ respectively have the second current I ₂ ′ shown in the equation (5). Occurs, and the other output transistor 13
Double the current 2I ₂ ′ is generated.

The first current I ₁ ′ generated in the output transistor 9 and the current 2 twice the second current I ₂ ′ generated in the output transistor 13
'Out with, the first sum current _{(I 1' I 2 + 2I} 2 ') is made.

In addition, the second current I ₂ 'generated in the output transistor 14
A second sum current (I ₂ ′ + 2I ₁ ′) is produced with the double current 2I ₁ ′ of the first current I ₁ ′ generated in the output transistor 11.

First current I ₁ ′, first sum current (I ₁ ′ + 2I ₁ ′), second
The sum current (I ₂ ′ + 2I ₁ ′) and the second current I ₂ ′ of each of the transistors 16, 17, 18, constituting the logarithmic conversion means,
19 and is logarithmically converted to a voltage value Va at each emitter,
Vb, Vc, Vd are output.

These voltage values Va, Vb, Vc, Vd are expressed by the following equations, respectively.

Va = Vt− (kT / q) ・ ln (A ₁ I ₁ ′ / Is) Vb = Vt− (kT / q) · ln [A ₁ (I ₁ ′ + 2I ₂ ′) / Is] Vc = Vt− ( kT / q) ・ ln [A ₁ (2I ₂ ′ ＋ I ₂ ′) / Is] Vd ＝ Vt− (kT / q) ・ ln (A ₁ I ₂ ′ / Is)… (7) where k: Boltzmann Constant T: Absolute temperature q: Electron charge Is: Reverse saturation current of transistor base-emitter junction A ₁ :: Hfe / (Hfe + 1) In equation (7) above, the first current I ₁ ′ was logarithmically converted. The voltage Va and the voltage Vb obtained by logarithmically converting the first sum current (I ₁ ′ + 2I ₂ ′) are converted into the first differential pair circuit via the source follower.
The signals are input to 29, 31 and differentially amplified, and a first differential output current Ia and a second differential output current Ib are generated in each output line.

Also, the voltage V obtained by logarithmically converting the second sum current (I ₂ ′ + 2I ₁ ′)
The voltage Vd obtained by logarithmically converting e and the second current I ₂ ′ is input to the second differential pair circuit 32, 33 via the source follower,
After being differentially amplified, the third differential output current Ic is output to the output line.
And a fourth differential output current Id is produced.

The differentially amplified first to fourth differential output currents Ia, Ib, Ic,
Id is expressed by the following equation.

Ia = Iref / [1 + exp [(q / kT) ・ (Vb-Va)]] Ib = Iref / [1 + exp [(q / kT) ・ (Va-Vb)]] Ic = Iref / [1 + exp [(q / kT) ・ (Vd−Vc)]] Id = Iref / [1 + exp [(q / kT) ・ (Vc−Vd)]]
(8) The above formula (7) is substituted as the voltages Va to Vd in the above formulas, and the first and second currents I ₁ ′ and I ₂ ′ in the formula (7) are substituted into the above formula (4). , (5), the above equation (8) becomes as follows.

_{Ia = Iref · (I 1 +} 2I 2) / 2 (I 1 + I 2) Ib = Iref · I 1/2 (I 1 + I 2) Ic = Iref · I 2/2 (I 1 + I 2) Id = Iref · (2I ₁ + I ₂ ) / 2 (I ₁ + I ₂ ) ... (9) Next, the first to fourth differences represented by the above equation (9) are calculated by the calculating means composed of the fourth current mirror circuit 40. The dynamic output currents Ia, Ib, Ic, and Id are processed as follows to obtain the calculated output current If.

If = Ia + Ic− (Ib + Id) = Iref · (I ₂ −I ₁ ) / (I ₁ + I ₂ ) ... (10) The operation output current If is input to the inverting input terminal (−) of the current-voltage conversion circuit 46. , And is converted into a voltage, and the following output Vout is obtained from the current-voltage conversion circuit 46.

Vout = Vst / 2 + Rf · Iref · (I ₂ −I ₁ ) / (I ₁ + I ₂ )… (1
1) Substituting the equations (1) and (2) into the Vout of the equation (11) as the first and second photocurrents I ₁ and I ₂ , and the equation (6) as the constant current Iref. Substituting gives the following equation:

Vout = [1/2 + (x / l-1 / 2) 2.Rf / Rb] .Vst (12) If Rb = 2Rf is set here, the above formula (12) becomes as follows.

Vout = Vst · x / l (13) Since the values of Vst and l are appropriately set, the light projection position x can be detected by measuring the output voltage Vout of the current-voltage conversion circuit 46.

And in such a detection operation of the projection position x of light,
The optical position detecting element 1 and each element constituting the signal processing circuit are incorporated in one chip, and minute signal processing of the _first and _second photocurrents I ₁ and I ₂ is performed in the chip. For this reason
While the S / N ratio is improved, the leakage current compensation of the optical position detection element 1 can be performed in the same chip, the detection accuracy is improved, and the reliability of the device is improved.

Next, FIG. 3 shows another embodiment of the present invention.

In this embodiment, the electrodes 4 and 5 of the optical position detecting element 1 are connected to the input transistors 7 and 12 of the first and second current mirror circuits via a constant voltage buffer.

65 and 66 are p-channel JFETs, 67 and 68 are operational amplifiers, and a positive voltage is applied to the non-inverting input terminal (+) of each operational amplifier 67 and 68.
Vp constant voltage sources 69 and 70 are connected to each other.

The electrode 4 in the optical position detecting element 1 is connected to the source of the JFET 65, and its drain is connected to the input transistor 7 of the first current mirror circuit.

The inverting input terminal (−) of the operational amplifier 67 is connected to the source of the JFET65, and the output terminal of the operational amplifier 67 is connected to the gate of the JFET65. The gate of the JFET 65 is driven by the operational amplifier 67, and its source potential is held at the constant voltage Vp.

Also for the electrode 5 side of the optical position detection element 1, JFET66
And the operational amplifier 68 is connected in the same manner as described above.

In the case of the above-described embodiment (FIG. 1), when the values of the _first and _second photocurrents I ₁ and I ₂ extracted from the optical position detection element 1 change, the first and second currents are changed. The emitter-base voltages of the input transistors 7 and 12 in the mirror circuit change, and the bias voltage of the optical position detecting element 1 changes.
Therefore, when the light projection position is toward the end of the light detection surface, the difference between the _first and _second photocurrents I ₁ and I ₂ becomes large, and thus an error is likely to occur in the detection of the light position.

However, in the embodiment of FIG. 3, even if the values of the _first and _second photocurrents I ₁ and I ₂ are changed, the photo-position detecting element 1 is always biased with a constant voltage (Vst-Vp). Therefore, the above-mentioned error is prevented from occurring.

[Effects of the Invention] As described above, according to the present invention, the signal processing circuit is configured such that the first and second photocurrents extracted from the optical position detection element are converted into the first and second currents and the first and second photocurrents. , A current converting means for generating a second sum current, and the first and second currents and the first,
Logarithmic conversion means for logarithmically converting the second sum current and outputting it as a voltage, and first and fourth logarithmic conversion means for differentially amplifying each logarithmically converted voltage to generate first to fourth differential output currents. The signal processing circuit is composed of the second differential pair circuit and the calculating means for calculating the current output corresponding to the light projection position from the first to fourth differential output currents. It can be integrated in one chip. Therefore, there is an advantage that it can be configured compactly, the reliability of the device is improved, and an inexpensive optical position detection device can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the optical position detecting device according to the present invention, and FIG.
FIG. 3 is a longitudinal sectional view partially showing an example of being made into a chip, FIG. 3 is a main part circuit diagram showing another embodiment of the present invention, and FIG. 4 is a circuit diagram showing a conventional optical position detecting device. 1: optical position detecting element, 2: semiconductor substrate region, 3: p-type layer, 4, 5: electrode, 7, 8, 9, 11: n constituting the first current mirror circuit
pn transistors, 12, 13, 14, 15: npn transistors forming a second current mirror circuit that constitutes a current converting means together with the first current mirror circuit, 16, 17, 18, 19: constituting a logarithmic converting means npn transistors, 29, 31: npn transistors forming a first differential pair circuit, 32, 33: npn transistors forming a second differential pair circuit, 40: fourth current mirror circuit forming arithmetic means , 46: Current-voltage conversion circuit.

Claims (1)

[Claims] 1. A bonding layer serving as a light detection surface is formed by a surface portion of a semiconductor substrate region of one conductivity type and a layer of opposite conductivity type.
First and second positions, which are relatively spaced apart from each other in the opposite conductivity type layer, and which change relative to the projection position of light between the two positions.
An optical position detecting element provided with an electrode for extracting the photocurrent, a first current corresponding to the first photocurrent, a second current corresponding to the second photocurrent, and a second current corresponding to the second current. Current conversion means for generating a first sum current obtained by adding a first current to a double current and a second sum current obtained by adding a second current to a current twice the first current; Logarithmic conversion means for logarithmically converting the first and second currents and the first and second sum currents and outputting them as voltages, a voltage obtained by logarithmically converting the first current and a voltage obtained by logarithmically converting the first sum current. Differentially amplifying the first differential output circuit to generate a first differential output current and a second differential output current, and a logarithmically converted voltage of the second current and a second sum current. A second differential amplifier that differentially amplifies the converted voltage to generate a third differential output current and a fourth differential output current. A differential pair circuit, and a calculation means for calculating a current output corresponding to a light projection position between the two positions of the light position detection element, using the first to fourth differential output currents. Optical position detector.