JPH0766030B2 - How to diagnose logical packages - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a diagnostic method for a logic package composed of parts including large-scale logic.

[Background of the Invention]

As the logical scale of logic packages increases due to the use of logic LSIs, it becomes more difficult to create diagnostic data for the entire package logic, and logical or physical division is performed, and diagnosis is performed for each division unit. The method of doing is known.

1. Method of logically dividing and diagnosing All flip-flops are a method of logically dividing and diagnosing a logical structure that enables scan-in / scan-out, but there are restrictions in terms of logical structure. Not easy to apply to logic.

2. Physically dividing and diagnosing method A tester device that has a probing function for all component pins is a prerequisite. It is a method of diagnosing connection defects between components and defect of individual components by probing. As the logic scale increases, there is a problem that components cannot be fully diagnosed and there is a problem in probing technology.

[Object of the Invention]

An object of the present invention is to add a logic capable of scan-in and scan-out to a component pin of a component mounted on a logic package, and divide into a diagnosis between components and a diagnosis of a single component to diagnose a logic package. To provide.

[Outline of Invention]

By adding a flip-flop logic capable of scan-in and scan-out to the above-mentioned component pin inside or outside of a large-scale logic component constituting the logic package, without using the constraint of the logic structure or using a special tester device, Enables split diagnosis.

Example of Invention

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a logic schematic diagram of a logic package of one embodiment of the present invention. In the figure, 1 is a pin of the logic package,
2 is an LSI including a large-scale logic, 3 is an LSI pin, 4 is a reception flip-flop corresponding to an LSI input pin, 5 is a transmission flip-flop corresponding to an LSI output pin, and 6 is a reception The clock indicates a clock for the reception flip-flop 4, and the transmission clock 7 indicates a clock for the transmission flip-flop 5. 8
Scan control signal, package scan control circuit 9 and scan out signal 10 and LSI scan control circuit 11 are write (scan) to the reception flip-flop and the transmission flip-flop corresponding to the input pin and output pin of the LSI. In) and reading (scan out).

FIG. 2 is a gate expansion type of reception and transmission flip-flops and a symbol diagram of the flip-flops.

FIG. 3 shows the peripheral logic and scan logic of the LSI input pins and output pins in the LSI. There are 5 transmitting flip-flops corresponding to the output pin 13 of the LSI and 4 receiving flip-flops corresponding to the input pin 15, and the receiving clock of 6 stores the information from the input pin 15 in the receiving flip-flop 4. It is for the purpose of the transmission clock of 7 is LS
It is for storing the information from the transmission gate 14 receiving the signal from within I in the transmission flip-flop. Writing (scan-in) to the transmission flip-flop 5 and the reception flip-flop 4 is performed by the address decode circuit 20 and the scan-in control circuit 21 to scan 19 addresses and 17 scan addresses.
This is possible by issuing 18 scan clocks after specifying the scan data of. With 20 address decoding circuits
Reading (scan-out) by the 22 scan-out control circuit is possible by designating 19 scan addresses.

The reception gate 16 sends the information of the reception flip-flop 4 into the LSI.

The diagnostic method between LSIs is shown in FIG. 24,25,26 LSI
Indicates that the transmitting and receiving flip-flops shown in FIG. 3 are provided, and the IC of 27 has a small logic scale and does not have the transmitting and receiving flip-flops. 27 ICs and 24,2
The diagnostic procedure between 5,26 LSIs is shown below.

I) The transmission clock 7 is turned off and the reception clock 6 is turned on.

II) IC27 and LSI24,25,2 for transmission flip-flop
6 Scan in the data that enables the detection of the connection failure.

III) Scan out the reception flip-flop 30 and compare with the expected value.

The diagnostic method in the LSI is shown in FIG. 31st LSI is second
The transmitter and receiver flip-flops shown in the figure are provided. Test data to be diagnosed at the single level of LSI31 is created so as to satisfy the following conditions.

I) Test data is created separately for the diagnosis of the logic circuit section 32 and the diagnosis of the scan circuit section 33.

II) The test data of the logic circuit section 32 is the reception clock 6,
Make a test pattern from the input pin of the LSI with the transmission clock 7 turned on.

III) Create a test pattern so that only one pin changes from test to test.

a) Diagnosis method of the scan circuit unit 33 I) Turn off the reception clock 6 and the transmission clock.

II) After scanning 1 into all the receiving flip-flops and the transmitting flip-flops, scan out the above flip-flops and test whether all are 1.

III) After scanning in 0 to all flip-flops in II), scan out and test whether they are all 0.

b) Method of diagnosing logic circuit section 32 I) Turn off the reception clock 6 and turn on the transmission clock 7.

II) Scan the logic value of the first test pattern of the test data for diagnosing the logic circuit section 32 at the single level of the LSI 31 into all the reception flip-flops corresponding to the input pin of the LSI.

III) Scan out all transmission flip-flops corresponding to the LSI output pin and compare with the expected LSI output pin value of the test data.

IV) After the second test pattern, the changed logical value is scanned in to the corresponding reception flip-flop only for the LSI input 1 pin that has changed due to the switching of the test pattern.

V) Same as III).

Repeat VI) IV) and V) until the final test pattern.

By implementing the present invention, diagnosis of logical packages can be performed.
It can be divided into diagnosis between LSI and IC and diagnosis inside LSI.

〔The invention's effect〕

According to the present invention, package diagnosis can be performed separately for large-scale logic component diagnosis and large-scale logic component diagnosis, and when performing large-scale logic component diagnosis, the large-scale logic component alone can be used. The test data for the diagnosis to be performed can be used, and the test data can be easily created when the test data for diagnosing between the large-scale logic components is created because the logic inside the large-scale logic component is not required. From the above, there is an effect that the computer processing time for creating the test data of the logical package can be reduced to 1/5 or less and high quality test data can be easily created.

[Brief description of drawings]

FIG. 1 is a schematic logic diagram of a logic package according to an embodiment of the present invention, FIG. 2 is a logic diagram of a flip-flop and a symbol diagram of the flip-flop, and FIG. 3 is a schematic diagram of a circuit added to an input pin and an output pin of an LSI. 4 and FIG. 4. FIG. 4 is a connection relationship diagram between the LSI and the IC, and FIG. 5 is a logical connection relationship diagram within the LSI. 1 ... Logic package, 2 ... LSI 3 ... LSI pin 4 ... Reception flip-flop 5 ... Transmission flip-flop 6 ... Reception clock, 7 ... Transmission clock 8 ... Scan control signal 9 ... Package scan control Circuit 10 …… Scan out signal 11 …… LSI scan control circuit 12 …… Flip-flop symbol Figure 13 …… LSI output pin, 14 …… Transmit gate 15 …… LSI input pin, 16 …… Receive gate 17 …… Scan data 18 …… scan clock, 19 …… scan address 20 …… address decode circuit 21 …… scan-in control circuit 22 …… scan-out control circuit

Claims (1)

[Claims] 1. At least a plurality of large-scale logic components are mounted and have external connection pins, and scan-in and scan-out can be performed in the plurality of large-scale logic components corresponding to input pins and output pins of the large-scale logic components. Equipped with various flip-flops,
A method of diagnosing a logic package having logic for enabling scan-in and scan-out of the flip-flop from the external connection pin, wherein test data is stored in a flip-flop corresponding to an output pin in the large-scale logic component. After scanning in, the flip-flop corresponding to the input pin of the next large-scale logical component of the large-scale logical component is scanned out to diagnose the logical component group existing between the large-scale logical components. How to diagnose logical packages.