JPH0766036B2 - Integrated circuit test method and test apparatus - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an integrated circuit (IC) using an electron beam test apparatus.
The present invention relates to an integrated circuit test method for easily and highly accurately detecting the presence / absence of a failure in an integrated circuit under test and its location, and a test apparatus used directly for carrying out the test method.

[Description of conventional technology]

With the scale and complexity of integrated circuits increasing, the gate / pin ratio has reached a level of thousands, and today's large-scale integrated circuits that perform tests by exchanging signals only from external pins ( It has become impossible to detect failures inside LSIs by using the (LSI) test equipment and the failure simulation method based on this. Although the fault simulation method is a diagnostic method that has a very simple process of single stuck-at fault, since the calculation time is proportional to the cube of the number of gates, it becomes an LSI with several K gates or more.
It becomes virtually infeasible.

The electron beam test equipment (EBT) that appeared as a response to this is a powerful tool because it can observe the internal operation of the LSI, but in order to put it into practical use, it is a method of recognizing the thousands of wirings observed. -Association between each wiring pattern and the node on the circuit diagram- must be established. For that purpose, it is indispensable to utilize the design resources of LSI.
Stand-alone devices like the BT are unwieldy.

By the way, BET has two uses. One is to use it for "fault diagnosis" to investigate the failure location and cause of the faulty integrated circuit (IC), and the other is to use it for "motion analysis" to evaluate the internal operating state of the IC. is there. In the early stages of IC development, most of the prototypes are immovable ICs that contain many failures. Therefore, EBT
Should be used for failure diagnosis first, but conventional EB
T was mostly a so-called strobe SEM used for the purpose of "motion analysis". Strobe SEM is
Like the oscilloscope, it is a tool for observing repetitive waveforms that change at high speed, so it can perform precise measurements, but it takes time to perform the measurements. Therefore, the device is originally unsuitable for failure diagnosis in which an unspecified number of wiring potentials are measured and a failure location is detected. In addition, since accurate measurement cannot be performed with the protective film on the surface of the IC, it was not applicable to tests on the manufacturing line such as non-defective product selection test. For this reason, it was actually used only as an auxiliary means for IC research and development.

As mentioned above, the fault simulation method can no longer be used, and the EBT expected to replace it is almost a stand-alone strobe SEM.
The technology that can be used for fault diagnosis of large-scaled and complicated LSIs, especially logic LSIs that have a low number of repetitions and have complicated wiring, is conventional.

[Object of the Invention]

In order to solve these problems, the present invention solves these problems by testing a method of testing an integrated circuit using an electron beam, which improves the ability to diagnose and detect a fault with a small number of tests, and a test of an integrated circuit directly used to implement the testing method. A device is provided.

The first purpose is to provide a so-called electron beam test apparatus for measuring the surface wiring potential of an integrated circuit using a scanning electron microscope.
By connecting to a CAD (Computer Aided Design) system on an electronic computer, design data of the integrated circuit (DUT: Device Under Test) is used for comparison judgment of measurement results, and the existence of a fault location is found in wiring units. To be able to do so.

The second purpose is the discovery of stuck-at faults (faults where the logic value is fixed and does not change to "0" or "1" that appears characteristically when the wiring is short or open) that are often seen in the early stages of development. In order to facilitate the above, the diagnostic result is output in the form of a logical time chart.

The third purpose is to enable testing of an integrated circuit having an insulating protective film (passivation film) on the surface.

The fourth purpose is to measure an integrated circuit including a sequential circuit, measure and collate only once after applying a large number of test signals, and check if there is a ripple effect or residual effect of the failure. The purpose of the present invention is to provide a non-defective product screening test method with a high detection rate that detects the presence or absence of

[Explanation of Structure and Operation of Invention]

FIG. 1 is a block diagram showing an example of an electron beam test apparatus for executing a test method for an integrated circuit according to the present invention.
Test signal on the host computer 10 (TP: Test Patter
n) Transfer the TP series created by the creation program 13 to the test signal supply device 6 via the control computer 3. this
The TP series may be a TP for logic simulation for performing the function check of the IC1 to be tested, or may be a large number of random TP series generated regardless of the function of the IC. Further, the creation location may be on the control computer 3 instead of on the host computer 10 or may be provided by another generator, that is, a test signal generator in another test apparatus. The test signal supply device 6 has a function of continuously supplying the input TP series to the test target IC1 through the IC socket 23 at a predetermined timing, and at each set time, at each signal value at that time. Must be provided with a function capable of stopping while holding.

The test target IC1 may have a protective film on its surface, but first consider the case without a protective film. In the first test method according to the present invention, the number of observation areas on the surface of the IC1 to be tested is limited to a small number. The observation area is set by the following method.

Based on the results of the test using the LSI test equipment, select the measurement points on the circuit diagram centering on the problematic points predicted in the design and process. Next, start the observation area determination program 12, enter the terminal name of the gate you want to measure on the circuit diagram and the wiring net number 36 (see Fig. 4), and enter the wiring position with the corresponding net number on the terminal display 2. Is displayed, so the observation area is determined so that these are included efficiently. When the observation area is determined, this program informs the control computer 3 of the center coordinates of the area and drives the motor 25 to move the XY stage 22 to that position.

The TP series is sequentially applied to the test IC1, and each state is maintained for a certain period of time. For each TP, the scanning circuit 4 operates and raster-scans the electron beam 21 over the entire observation area, and the image binarization circuit 5 in synchronization with it operates to be detected by the secondary electron detector 24. The potential contrast signal is binarized under a certain threshold value, and the logical value (0 or 1) of each sample point is obtained. Wiring logical value measurement program 15
These measured logic values are transferred to the host computer 10 via the control computer 3 and stored in the measured logic value file 7. Depending on the number of sample points, an A / D converter is placed instead of the binarization circuit, and the analog voltage contrast signal is transferred to the host computer via the control computer only by digitizing it, and the special signal is sent on the host computer. It may be binarized by using the binarization program prepared in. However, it is faster and more efficient to use the binarization circuit.

The number of sample points is determined according to the observation area size and the wiring width. One guideline is the number of 2-3 sample points within one wiring width. Considering an IC with a wiring width of 3 μm as an example, when the area size is 500 μm square, 512 × 512 is an appropriate number of sample points.

FIG. 2 shows a measured potential map 40 obtained as a result of the measurement. This is a time-series signal consisting of "0" or "1" obtained by taking in a two-dimensional potential contrast signal measured by the scanning electron microscope 20 through the image binarization circuit 5 at a constant timing. Are two-dimensionally arranged at intervals according to the timing, and a small rectangle with a middle coating is placed on the point of "0" for visualization. Reference numeral 41 is a wiring pattern having a low level logical value. To create a "Measurement logic map" 42 (Fig. 3) from the measurement potential map 40, use the measurement logic map creation program 16 on the host computer 10.
After starting up and correcting the rotation and the magnification, the measured potential map is filtered by a median filter or the like to remove noise. Next, the periphery of the wiring is extracted and the wiring is replaced with a rectangle. At that time, design rules such as wiring width and wiring pitch obtained from the layout information 33 in the design database 30 are useful. As described above, the "measurement logic map" 42 including the wiring rectangle 43 having the logic value 0 is created as shown in FIG.

The "design logic map" 44, which is the object of comparison and verification, is CAD
It is created from circuit description information 32, wiring figure information 34, and simulation information 35 obtained from the design database 30 connected to the system 11. In this method, the wiring patterns of the uppermost layer are arranged in a frame corresponding to the observation area, and "colored" according to the logic expected value obtained as a result of the logic simulation. For example, the color of the wiring figure having the expected value “0” and the wiring figure having the expected value “1” is changed, or the type of the drawn line is changed. Fig. 4 shows the structure of the design database. This design database contains a logic simulator 31, circuit description information 3
2. At least five items of layout information 33, wiring pattern information 34, and simulation information 35 are required. In addition, 3
There must be a mutual link between 2,33,34. Here, the node on the logic circuit and the wiring figure on the mask pattern are associated with each other through the net number 36 which is a common identification number of the wiring. Design logic map 44
Shows a wiring figure in which the logical value of the simulation result is superimposed in the frame indicating the corresponding observation area. FIG. 5 shows an example of the design logic map 44. In order to easily discriminate the logical value, the graphic of the logical value 1 is displayed by, for example, a dotted line as indicated by 45, and the graphic of the logical value 0 is displayed by, for example, a solid line as indicated by 46.

Next, the “measurement logic map” 42 and the “design logic map” 44 are superposed. Since the XY stage 22 has a positioning error of about ± 20 μm, the latter is 50 μm on each side compared to the former.
If taken to be somewhat large, the former will always be included in the latter. EBT measurement must always be performed at several fixed magnifications, and if the correct correction amount for each magnification is obtained, then no matter what observation area and which magnification map is obtained, the measurement logic map 42 The design logic map 44 can be superposed only by translation.

The following methods are available for superimposing. From the measurement logic map 42 and the design logic map 44, select one wiring of an appropriate length (one that does not touch the edge of the area at both ends), perform parallel movement assuming that they overlap, and make a measurement logic map. For the other wiring that appears, find the total length of overlap. When the overlap length is maximum, it is determined that the overlaps have been made correctly. The result 47 of superposition is shown in FIG. However, if the overlap ratio defined by the overlap length / total wiring length is, for example, 80% or less, it is judged as a measurement logic map failure and
Outputs "measurement error".

Only one superimposition is required for each TP series. If the superposition is successful, the logic value for each test signal is checked for each wiring, and if the expected value and the measured value do not match, the wiring pattern is shaded to facilitate discrimination.
48 is a wiring pattern whose measured value is 1 against expected value 0, 49
Shows a wiring figure whose measured value was 0 with respect to expected value 1. With respect to the wiring that has a logic mismatch even once with respect to the applied TP series, the net number and both logic values are output in the form of time chart 50 as shown in FIG. In FIG. 7, 51 is a measured value and 52 is an expected value. This makes EB
T can be used as a logic analyzer. The stuck-at fault can be confirmed very easily by the output in the time chart format. Since the fault diagnosis EBT is mainly intended for detecting stuck-at faults, its function can be maximized by using this output method.

In the second test method according to the present invention, an IC covered with an insulating film for surface protection is used as a test object. When the insulating film is overlaid on the wiring, in the DC mode, a phenomenon occurs in which the potential contrast is ablated with a time constant of 1 to 2 seconds due to a charge-up effect in which electrons are captured and charged in the insulating film. . Therefore, although it is not possible to perform steady observation, if the image data is collected within a time shorter than the above time constant, for example, 0.5 seconds each time TP is changed, it is possible to obtain the logical value of the wiring with the changed potential. is there. Therefore, first of all, if the initial logical value of all the wirings appearing in the observation area is obtained and the logical value changed for each TP is rewritten,
It is possible to obtain the change in the logical value of all wirings with respect to. The initial logical value can be obtained by taking in the image data on the first screen where the electron beam scanning is started and binarizing it. Therefore, even when the surface protective film is provided, the comparison with the simulation result and the logical time chart output are possible as in the first test method. Of course, the binarization error is increased as compared with the case where the protective film is not provided, but the amount is practically no problem. According to an experiment conducted by the inventors, this measurement was performed with an insulating film of 1 μm.
It is possible even when it is about m, so Si on the surface
Even with a protective film such as O ₂ or PSG, it is possible to measure the wiring logical values of at least the upper two layers.

The drawback of EBT is that it can observe the inside of the LSI, but the test time is long. If the observation area size is 500 μm square, the total area is 20 × 20 = for a 10 mm square chip.
It will be 400. Even if a large machine is used as the host computer, the measurement / verification time per area requires about 30 seconds, so the test time is 200 minutes per TP. Therefore, it is necessary to reduce the number of TPs targeted for image data collection as much as possible. By the way, in a test in a manufacturing line where a large amount of integrated circuits are produced using the technology that has been established in both design and process, the location of the failure is unspecified and even if
It is necessary to be able to detect faults in a few places and few. To do so, the test equipment used here must have the ability to apply a large amount of TP at high speed and the ability to detect even a failure that has occurred in any of the TPs. Therefore, in the third test method according to the present invention, in order to apply to the non-defective product selection test in the manufacturing line, after applying a TP series of a certain length to the IC to be tested, TP is applied in the final applied state. It is basically fixed and the whole surface of the IC is measured and collated. Here, it is assumed that the IC under test is a sequential circuit. If it is a sequential circuit, a series of
If a logical mismatch occurs for the TP in the middle when applying the TP series, the effect should remain somewhere in the circuit until the end. Therefore, for the purpose of failure detection of sequential circuits, EBT
Image data collection by 1 after applying all TP series
You only have to do it once. Unlike conventional LSI test equipment, the effect can be detected even if it does not appear on the external output terminal.
The detection rate is significantly improved. In the case of combinational circuits,
The influence of the failure that occurred on the TP in the middle does not remain when the TP is changed, but the number K to the number + where the failure diagnosis is a problem today
It is not possible that the K-gate LSI is only a combinational circuit, so it need not be considered.

If you want to make a fault diagnosis, stop the TP at half N / 2 of the total TP number N for the IC where the fault is found, and perform the same measurement. If a failure is already found there, the same measurement is performed at half of that (N / 4). If no failure is found at the N / 2 pattern, measure at 3N / 4. In this way, if the test is repeated by the dichotomy method, the failure location can be located by the number of log ₂ N.

[Explanation of effects]

The test method of the integrated circuit according to the present invention is aimed at the failure diagnosis in the DC mode by the EBT. The features that penetrate the whole are: 1) It is not necessary to perform failure simulation that is becoming infeasible because it takes a huge amount of calculation time to perform LSI fault diagnosis, and only logic simulation is sufficient. The fact that fault diagnosis methods can analyze multiple faults, which cannot be handled at all, is itself a major innovation in the field of fault diagnosis of integrated circuits.

The reason for conducting the test in DC mode is that 0 fixed / 1 fixed and degenerate failures that occur in the early stages of development (mainly due to design mistakes,
This is because most of them can be detected even in the DC mode.
Testing in DC mode instead of AC mode not only simplifies the device, but it also provides the following benefits:

i) Image quality is good (S / N is high) ii) Low voltage measurement accuracy is not a problem iii) Measurement is possible even if the surface has a protective film iv) Measurement of lower layer wiring potential is explained in order below. It is natural that i) can be continuously irradiated with an electron beam in the DC mode. Damage caused by irradiation does not pose a problem if the pressure voltage of the electron beam is low, for example, 1 KV or less. ii) is an essential problem for EBT. The biggest problem with EBT is its low voltage measurement accuracy,
The absolute voltage error reaches 0.5V due to the "local electric field effect" in which the trajectory of the secondary electrons jumping out from the measurement point is affected by the potential fluctuation around the measurement point. Therefore, when measuring the voltage waveform in the AC (strobe) mode like the strobe SEM, it becomes a big problem. However, in the logical value measurement in the DC mode, it suffices to be able to make a binary judgment of 0 or 1 with respect to a certain threshold value, so it does not matter as long as a device having a logical amplitude of 1 V or more such as TTL or MOS is used.

iii) and iv) are problems related to voltage measurement through an insulating film. In AC (strobe) mode, if there is an insulating film on the wiring, it is equivalent to measuring the voltage via capacitance, and you will see the differential waveform. In the situation where the capacitance varies depending on the place and each element, accurate waveform measurement is difficult. In order to reduce the effect of the capacitance, data may be sampled within a time shorter than the time constant of waveform change. Therefore, a high-speed phase scanning method that changes the phase of the pulse beam at high speed has been proposed, but there is a problem that the energy analyzer cannot follow it. Therefore, the strobe SEM has an IC with a protective film on its surface.
The measurement of is not practical. However, as already mentioned, this point does not matter if the logical value measurement is in DC mode. The ability to test ICs with a protective film is an indispensable condition for applying to the non-defective product selection test on the manufacturing line.

As described above, the present invention provides an epoch-making failure diagnosis technique independent of the scale in the field of integrated circuit failure diagnosis that has become almost impossible with the increase in the size of the integrated circuit. It also provides highly accurate failure detection technology for testing on the manufacturing line, and its impact on the semiconductor industry is extremely large.

[Brief description of drawings]

FIG. 1 is a configuration example of an electron beam test apparatus, FIG. 2 is a measurement potential map, FIG. 3 is a measurement logic map, FIG. 4 is a design database structure, FIG. 5 is a design logic map, and FIG. 6 is measurement.・ As a result of superposition of both design logic maps, Fig. 7 shows the logic time charts. 1 ... IC to be measured, 2 ... Terminal display, 3 ... Control computer, 4 ... Scanning circuit, 5 ... Image binarization circuit, 6 ... Test signal supply device, 7 ... Measurement logical value file, 10 …… Host computer, 11 …… CAD system, 12 …… Observation area determination program, 13 …… Test signal creation program, 14 …… Design logic map creation program, 15 …… Wiring logic value measurement program, 16 …… Measurement Logical map creation program, 17 ... Logical value matching program,
20 …… Scanning electron microscope, 21 …… Electron beam, 22 …… XY
Stage, 23 …… IC socket, 24 …… Secondary electron detector,
25 …… motor, 30 …… design database, 31 …… logic simulator, 32 …… circuit description information, 33 …… layout information, 34 …… wiring figure information, 35 …… simulation information, 36 …… wiring net number, 40 …… Measured potential map, 41
...... Wire pattern with logical value 0, 42 …… Measurement logic map, 43…
… Wiring rectangle, 44 …… Design logic map, 45 …… Logic value 1 figure, 46 …… Logic value 0 figure, 47 …… Measurement and design both logic map overlay results, 48 …… Logic mismatched figure (Measured value 1 against expected value 0), 49 ... Logically mismatched figure (measured value 0 against expected value 1), 50 ... Time chart, 51 ...
… Measured value, 52 …… Expected value

Claims (4)

[Claims] 1. A two-dimensional analog image signal measured by a scanning electron microscope by sequentially applying a test signal sequence of a fixed length from a test signal supply circuit to a measurement target integrated circuit DUT installed in the scanning electron microscope. A two-dimensional distribution of measured logical values, which is obtained by taking in the image at a fixed timing via the image binarization circuit and converting the image signal on each grid point into a logical value of "1" or "0". "Measurement logic map" is created, and each grid point in the measurement logic map is taken from the logic expected value of each wiring obtained by performing logic simulation based on the wiring graphic information of the DUT. Create a “design logic map” showing a two-dimensional distribution of expected power values, and compare and compare the measurement logic map and the design logic map.
By extracting the wiring that the measurement logical value and the design logical value are different by collating, the measurement logical value and the design logical value of the wiring that the measurement logical value and the design logical value are different, on one coordinate axis A method for testing an integrated circuit, comprising outputting as a logical time chart in which the two logical values and the test signal application time are taken on the other coordinate axis. 2. Each time a test signal applied from a test signal supply circuit is sequentially changed to a DUT having an insulating film attached to its surface, a wiring image in which a potential change observed through the insulating film is generated again. The method for testing an integrated circuit according to claim 1, wherein the image signal is sampled within a time before it disappears. 3. A measurement logic map obtained by applying a test signal sequence of a fixed length from the test signal supply circuit to a DUT including a sequential circuit, and then fixing the test signal in the final applied state, The method for testing an integrated circuit according to claim 2, wherein the design logic map is compared and collated. 4. A means for continuously supplying a test signal to a scanning electron microscope and a measurement target integrated circuit DUT arranged in the scanning electron microscope at a predetermined timing by a test signal supply circuit through an IC socket. , An image binarization circuit, design data storage means of the measurement target integrated circuit DUT, a two-dimensional analog image signal measured by the scanning electron microscope at a constant timing via the image binarization circuit A measurement logic map creating means for capturing and converting the image signal on each grid point into a logic value of "1" or "0" and creating a "measurement logic map" showing a two-dimensional distribution of measurement logic values, Means for obtaining a logic expected value of each wiring by logic simulation based on the wiring figure information of the DUT read from the design data corresponding to the measurement logic map, and also the logic expected value of each wiring. And a design logic map creating means for creating a "design logic map" showing a two-dimensional distribution of logic expected values that each lattice point in the measurement logic map should take, comparing the measurement logic map and the design logic map.・
A means for extracting a wiring whose measurement logic value and said design logic value are different by collating, a circuit net number of a wiring whose measurement logic value and said design logic value are different, said measurement logic value and said design logic value And a means for outputting with the time associated with the test signal application time, a test apparatus for an integrated circuit.