JPH0766040B2 - Programmable logic array tester - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic array tester capable of easily making various logic circuits by write scanning.

“Prior Art” The applicant of the present invention is “Japanese Patent Application No. 52-145399 (Japanese Patent Application Laid-Open No. 54-78047).
No.) ”, a programmable logic array tester is proposed. The outline of the tester proposed previously is shown in FIG. In FIG. 9, reference numeral 1 denotes a device under test, that is, a programmable logic array (hereinafter referred to as FPLA). 2 is a pattern generator which gives a test pattern to the input terminal IN of this FPLA 1 and 3 is a pattern signal which is given to the FPLA 1 from the pattern generator 2 and the expected value for every program term is obtained for each pattern signal. An expected value calculator obtained by calculation is shown. Each expected value obtained from the expected value calculator 3 is given to the logical comparator 4, and the logical comparator 4 causes the FPLA1
The response output obtained from the output terminal OUT and the expected value are compared, and it is determined whether they match or not, and it is tested whether or not the writing is performed correctly.

"Problems to be Solved by the Invention" In the prior art shown in FIG. 9, when the number of input terminals of FPLA1 is ⁿ , the number of pattern signals given to the input terminal IN is 2 ⁿ . Therefore, as the number of input terminals n increases, the number of patterns increases, and in this respect, there is a drawback that the test time becomes long.
In addition, since the expected value pattern corresponding to the program term in FPLA1 is calculated by the expected value calculator 3 (microcomputer) for each pattern, the calculation takes time, and this also has a drawback that it takes time. is there.

In particular, with the increase in capacity of FPLA, FPLAs such as 72 program terms, n = 24 input terminals, and 16 bits of internal feedback have come to be made recently.
If it is tested with a conventional tester, even if a 1-step test is performed in 1 microsecond, it takes about two and a half years to test the condition of all program terms. Therefore, it is practically impossible to test a large capacity FPLA.

[Means for Solving Problems] In the present invention, a part of pattern generation and expected value calculation is performed by a dedicated circuit so that the test can be completed in a short time.

The schematic structure of the tester according to the present invention is shown in FIG. In the figure, 1 indicates the FPLA to be tested. As is well known, the FPLA1 has an AND array 1A, an OR array 1B, and a program term selector 1C, and an input terminal IN is derived from the AND array 1A and an output terminal OUT is derived from the OR array 1B.

2 shows an FPLA tester according to the present invention. According to this invention
The FPLA tester 2 stores the data written in the FPLA1 at the time of writing, and outputs a response output of the FPLA1, that is, an expected value from the written data, and a pattern generator 3 that generates a pattern signal for outputting the expected value. The pattern scanner 4 receives the pattern signal output from the pattern generator 3 and generates a modified pattern signal based on the pattern signal, and the two-bit counters 4A and 4B constituting the pattern scanner 4.
Chip selectors 5 that select 4 to 4N and operate as counters when the chips are selected,
A latch circuit 6 that takes in an expected value from the pattern generator 3,
A logical comparator 7 for comparing the expected value fetched in the latch circuit 6 with the response output output from FPLA1, a display 8 for displaying the comparison result of the logical comparator 7, and a latch circuit 6 for enabling and disabling. It can be configured by a shift register 9 for storing a condition signal that is controlled to be enabled and a clock source 11 that scans the pattern scanner 4.

The pattern generator 3 can be configured by a microcomputer and can output a pattern signal and an expected value pattern from the write data stored at the time of writing.
It also operates as a controller that controls each part.

That is, as another control function of the pattern generator 3, a control signal can be sent to the program term selector 1C provided in the FPLA 1 to selectively control one of the 72 program terms to the enable state. This control gives the mode select signal MD to the selector 1C, and switches to the program term select state by this mode select signal MD. By applying the control pulse CP in the program term select state, 72 program terms are switched to the enable state one by one. This program term select function is especially added in the FPLA manufacturing company so that writing of FPLA can be performed separately for each program term.

The characteristic structure of the present invention is that the pattern scanner 4, the latch circuit 6, and the condition signal storage shift register 9 are provided.

"Simple operation description" In other words, in the program term selector 1C, for example,
When a program term is selected, a pattern signal corresponding to the connection state between the selected program term and the input terminal IN (program state of the AND array 1A) is output from the pattern generator 3, and the pattern signal is scanned. 2 bit counters 4A to 4N constituting the container 4 are preset and latched.

On the other hand, when this pattern signal is given, the expected value pattern output from the output terminal OUT is calculated from the write data in the pattern generator 3, and this expected value pattern is latched in the latch circuit 6. The expected value pattern latched by the latch circuit 6 is given to the logical comparator 7, and the logical comparator 7 compares the response output of the FPLA 1 with the expected value pattern. Here, the feature of the present application is that in the pattern scanner 4, the 2-bit counters 4A to 4N are sequentially selected by the chip selector 5,
The point is that the selected 2-bit counters 4A to 4N are sequentially operated as counters to scan the pattern signals. With this pattern scanning, the state of each intersection of one program term and the input line can be scanned and tested.

For pattern scanning, for example, if the total number of input terminals is 24 and the internal feed back is 16 bits, and the number of inputs is 40, then 20 2-bit counters are counted by 4 counts each and the pattern signal is scanned to scan one pattern term. It will take 4 counts x 20 = 80 counts to test the condition. If you have 72 program terms, 72 x 80 =
All tests can be completed with 5760 counts. When one count is set to 1 microsecond, the test time is about 6 milliseconds. Actually, in order to obtain the pattern signal and the expected value pattern corresponding to the program for each program term in the pattern generator 3, one test takes about 0.6 seconds. In reality, the power supply voltage applied to FPLA is changed and the test is repeated three times. Therefore, one FPLA can be tested in about 2 seconds. The reason why the test time can be shortened in this way is that not all the pattern signals are calculated and generated, but the pattern scanner 4 scans the patterns in synchronization with the clock from the initial pattern. Because.

[Detailed Description of the Invention] The structure of the FPLA to be tested in the present invention will be described with reference to FIG. In FIG. 2, 1A, 1B and 1C respectively indicate the AND array and OR array program term selectors as described in FIG. AND array 1A, for example 72 pieces of program term Y ₀ to Y ₇₁ (sometimes referred to as a product term line), 80 input lines X ₀ to X ₇₉ are arranged and formed so as to cross the program term Y ₀ Write the program depending on whether or not to connect Y ₇₉ to input lines X _{0 to} X ₇₉ at each intersection. 1D indicates an OR array driver group. With this driver group 1D, the program terms Y _{0 to} Y of the AND array 1A
Each potential of ₇₁ is amplified and the potential is transmitted to each program term of the OR array 1B. 1E ₁ ~1E ₂₀ shows a 2 bit decoder. In this example, a case where 20 2-bit decoders are used is shown. 2 8 2 bits decoder 1E ₁₃ ~1E ₂₀ in the bit decoder 1E ₁ ~1E ₂₀ is crowded preparative response output of Oaarei 1B taken out to the register 1F, fed back to the input side of the signal as an internal feedback signal It is a decoder that does.

1G indicates the output buffer, register 1F and output latch circuit
Performs the operation of giving the output of OR array 1B to 1H. The contents latched in the output latch circuit 1H can be taken out to the output terminals O _{0 to} O ₁₅ .

The register 1F outputs the internal feedback signal captured by the register 1F to the terminal JOUT by applying a clock signal to the clock terminal CK.
Can be taken out as a serial signal. Also input terminal
By applying a serial signal to JIN from the outside and driving it with a clock signal, it is possible to write data to the register 1F from the outside.

The AND array 1A has, for example, as shown in FIG. 3, 72 program terms Y _{0 to} Y ₇₁ , 80 input lines X _{0 to} X ₇₉ , program terms Y _{0 to} Y _71, and input lines X _{0 to} X. _{It is} constituted by the semiconductor cell Q connected to each intersection of ₇₉ . 72 for the OR array 1B
Book program terms Y _{0 to} Y ₇₁ and 48 output lines Z _{0 to} Z
₄₇ and a semiconductor element Q connected to each intersection. When the semiconductor element Q is programmed to the connection state by writing, it changes to the diode D as shown in FIG.

Writing is performed point by point by a serial signal as shown in FIG. That is, the program term Y ₀ to Y ₇₁ sequentially selects, data A to be written to the respective program term Y ₀ to Y ₇₁
Performs writing by ₀ to A _71. In the figure, "1" is written as data.

It will now be described two bits decoder 1E ₁ ~1E _20. Two
Bit decoder 1E ₁ ~1E ₂₀ has an input terminal and four output terminals of the two respectively, enter the four output terminals lines X ₀ to X ₃
Connect to. The part marked with a black circle in the figure is called a program point, and shows the state in which the input line and the program term are connected.

The decoder 1E inputs the input signals A and B into (L, L) (H, L) (L, H)
When changing in the order of (H, H), signals as shown in FIG. 7 are given to the input lines X _{0 to} X ₃ . It can be seen that the L logic of the signals applied to the input lines X _{0 to} X ₃ sequentially moves as shown in FIG. By this movement, the intersection of the input lines X _{0 to} X ₃ and the program term can be scanned to check the state, and this operation is referred to as pattern scanning here.

The program term Y ₀ shown in FIG. 6 has no connection points for the input lines X _{0 to} X ₃ . Therefore, no matter how the output of the decoder 1E changes, that is, whichever of the input lines X _{0 to} X ₃ is given the L logic, the program term Y ₀ is always held in the active state. As a result the input signal A and the relationship B without Oaarei 1B output line Z ₀ to Z ₄ of the output signal H as hereinbefore programmed Oaarei 1BB in (the output line in this example are shown in five), H, H, L and H are output. Such a setting state is called don't care.

The program term Y ₁ has connection points only for input line X ₀ . In this state, when the input signals A and B are L and L, the input line X ₀ has L logic. Therefore, at this time, the output lines Z _{0 to} Z ₄ of the OR array 1B are all L logic, and A + B = O is established. When the input signals A and B are in other states, the input line X ₀
Is held in the H logic, the output lines Z _{0 to} Z ₄ are H, L, H, H, L as programmed in the OR array 1B (H logic is applied to the connection point of the OR array 1B when the program term is active). Is output) is output. That is, the program term
Y ₁ constitutes an A + B logic circuit (OR circuit).

In the case of the program term Y ₂ , only the input line X ₁ has a connection point. Therefore, when A = L and B = H, the program term Y ₂
Becomes inactive, and the outputs of the OR array 1B are all L. For other inputs, the signals H, L, L, L, H as programmed are output to the output lines Z _{0 to} Z ₄ . In other words, the program term Y ₂ constitutes a + B logic circuit, that is, an OR circuit in which one is an inverting input terminal.

In this way, each program term Y _{0 to} Y ₁₅ constitutes a logic circuit represented by the logical formulas listed in the right column of FIG.

"Embodiment" The embodiment shown in FIG. 8 will be described after understanding the above description.

In FIG. 8, portions corresponding to those in FIG. 1 are designated by the same reference numerals. The pattern scanner 4 has 20 2-bit counters N
It consists of o.1 to No.20. Of the 20 2-bit counters, the output terminals of the 2-bit counters No. 1 to No. 12 are directly connected to the input terminals I ₀ , I _{1 to} I ₂₂ , I ₂₃ of FPLA1.
The output terminals of the 2-bit counters No. 13 to No. 20 are
A parallel signal is input to the 16-bit shift register 12 and the pattern signal input from the 2-bit counter 4 is input to the FP by driving the shift register 12 with the clock signal P ₁ .
Transfer to the register 1F built into LA1 and transfer to the 2-bit decoder 1E
Input as an input signal of _{13 to} 1E ₂₀ .

First, for example, the data programmed in the program term Y ₀ is given to the pattern scanner 4 by a pattern signal for keeping the program term Y ₀ in an active state. That is, a pattern signal satisfying the condition that the L logic is not output to the input line having the connection point with the program term Y ₀ is calculated from the write data in the pattern generator 3, and the pattern signal is obtained. To the input terminal of FPLA1 via.

At the same time as the initial pattern signal is latched to the pattern scanner 4, the 2-bit counter of the pattern scanner 4 is constructed.
No. 1 is selected by the chip selector 5 and operated as a counter. When the 2-bit counter No. 1 operates as a counter, for example, input signals A and B are input to the input terminals I ₀ and I ₁ in the order of (L, L) (L, H) (H, L) (H, H). Is given,
The position of the L logic given to the input line is gradually moved, and it is tested whether or not the intersection of the input line and the program term Y ₀ is connected. When the counter No.1 is quaternary and returns to the initial state
The No. 2 bit counter is selected and operates as a counter. In this way, each 2-bit counter are sequentially Chitsupuserekuto has been clock counting operation the count outputs 2 bits decoder 1E ₁ ~1E ₂₀ to give the program term Y ₀ and the input lines write data as programs crossing by Test if connected to term Y ₀ .

Here, the program term Y ₀ changes between an active state and an inactive state according to the pattern signal output from the pattern scanner 4 during the pattern scanning. That is, the sixth
As explained in the figure, in the state where the 2-bit decoder gives L logic to the input line having the connection point, the program term Y ₀ becomes inactive and the outputs of the OR array 1B all become L logic. In other states, that is, when the program term Y ₀ is in the active state, the OR array 1B outputs the response signal as programmed to the OR array 1B. Therefore, the latch circuit
The programmed data, that is, the expected value, is sent from the pattern generator 3 to the 6A to the or array 1B which alternates with the program term Y ₀ , and latched. Are compared by the logical comparator 7A.

Here, in conjunction with the pattern scanning of the pattern scanner 4, a condition signal (the condition signal is the fifth condition) in which the program term Y ₀ currently selected by the pattern signal becomes inactive.
(In agreement with the write data shown in the figure) is stored in the register 9, and this condition signal is given to the enable terminal E of the latch circuit 6A, the L logic signal is given to the connection point, and the program term Y ₀ becomes When the condition becomes inactive, the latch circuit 6A is controlled to the non-enabled state by the condition signal to convert all the outputs to the L logic so as to match the response output of the all L logic output from the OR array 1B. .

Further, the expected value corresponding to the response output taken in the register 1F incorporated in the FPLA1 is transferred from the pattern generator 3 to the register 6B. Each time the pattern signal is scanned by one step, the response output fetched in the register 1F is read, the read response output is compared with the expected value fetched in the register 6B by the comparator 7B, and the coincidence or non-coincidence is displayed on the display 8 To display.

A condition signal for making the program term Y ₀ inactive is given from the register 9 to the enable terminal E of the register 6B,
Register 6B when the program term becomes inactive
Are all set to L logic so as to match the output of register 1F.

The condition signal output from the register 9 is, for example, the random access memory provided in the register 9 from the pattern generator 3.
The condition signal transferred to 9A and read into the random access memory 9A is read by the address counter 13 as a parallel signal by 4 bits, for example, and the read condition signal is converted into a serial signal by the parallel-serial converter 9B. The converted condition signal converted into the serial signal is converted into the latch circuit 6A and the register 6B.
Supply to the enable terminal of.

[Effect] As described above, according to the present invention, the pattern signal having the condition that the program terms Y _{0 to} Y ₇₁ are selected one by one by the program term selector IC and the selected program terms are set in the active state. Is initially set in the pattern scanner 4, and the pattern scanner 4 is constructed from that state.
20 No. 1 to No. 20 2-bit counters are selected, each is counted and the pattern is scanned, and the state of each intersection of the input lines X _{0 to} X ₇₉ which intersects the program term by this scanning Is tested to see if it matches the write condition.

Therefore, according to the present invention, the program terms are tested one by one, so that the number of program terms and the input line X ₀ to
Since it is only necessary to generate pattern signals and perform logical comparison by the number of intersections determined by the product of the number of X _79, the number of test steps can be greatly reduced.

That is, when the conventional test method in which the program terms are not separated one by one is adopted, the number of comparison tests is 2 ⁸⁰ when the number of input lines is 80. On the other hand, according to the present invention, when the number of program terms is 72 and the number of input lines is 80, it is sufficient to perform the comparison operation 72 × 80 = 5760 times, so that the test time can be greatly shortened in this respect. .

Further, according to the present invention, the pattern generator 3 obtains a pattern signal from the data written in the respective program terms Y _{0 to} Y ₇₁ , and the pattern scanner 4 performs the pattern scanning based on the pattern signal. The scanning speed of the given pattern signal can be selected to be high, and the test time can be shortened also in this respect.

Further, since the pattern generator 3 has only to perform the operation of obtaining the pattern signals for the number of program terms, the number of pattern signals generated by the calculation can be greatly reduced. As a result, even if the calculation for obtaining the pattern takes some time, its effect is small.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the outline of the present invention,
2 is a block diagram for explaining the internal structure of the large-capacity FPLA, FIG. 3 is a connection diagram for explaining the detailed structure of the internal structure of the large-capacity FPLA, and FIG. 4 is a diagram before and after programming. FIG. 5 is a connection diagram for explaining the state, FIG. 5 is a diagram for explaining write data, and FIG. 6 is a connection diagram for explaining a structure of a 2-bit decoder and an AND array or an OR array built in the FPLA. FIG. 7 is a diagram for explaining logical values for explaining the operation of the 2-bit decoder, and FIG. 8 is a block diagram showing a more detailed embodiment of the present invention.
FIG. 9 is a block diagram for explaining a conventional FPLA tester. 1: FPLA, 1A: AND array, 1B: OR array, 1C: Program term selector, 1D: OR array driver, 1E _{1 to} 1E
₂₀ : 2 bit decoder, 1F: register, 1G: output buffer,
1H: output latch, Z: FPLA tester according to the present invention, 3: pattern generator, 4: pattern scanner, 5: chip selector, 6:
Latch circuit, 7: Logical comparator, 8: Display, 9: Condition signal storage register, 11: Clock source.

Claims (1)

[Claims] 1. A. 2-bit unit input terminal, a decoder for converting an input signal input to the unit input terminal into a bit signal of a number larger than 2 bits, and a plurality of decoders connected to the output side of the decoder. Unit input line, a plurality of program terms provided to intersect with this unit input line, and each unit input line and each program term provided at each intersection of the unit input line and the program term A semiconductor element to be programmed in a conductive and non-conductive state between, a plurality of output lines provided to intersect each program term, provided at the intersection of each output line and each program term, A semiconductor element that programs each output line and each program term into a conductive or non-conductive state, and a program term that controls each of the program terms to an enable state. A tester, which includes a selector and tests as a device under test a programmable logic array composed of a plurality of unit input terminals, a decoder, and a plurality of unit input lines, B. A program provided for the device under test An operation of applying an enable control signal to the term selector to control each of a plurality of program terms existing in the device under test to an enable state, and a program in the enable state each time each program term is controlled to an enable state. From the write data programmed in the conductive state between the term and the unit input line to the input line programmed in the conductive state
The operation to calculate and output the initial pattern signal that activates this program term without giving logic and the response output that the device under test outputs from the pattern signal given to the device under test are calculated, and this calculated value is the expected value. C. Latch the initial pattern signal output from this pattern generator, apply this initial pattern signal to the input terminal of the device under test, and divide it for each unit input line. Then, the pattern scanner for performing scanning to sequentially apply L logic to each input line is compared with D. The response output output from the output line of the device under test and the expected value output from the pattern generator. A programmable logic array tester, comprising: a logic comparator that determines pass / fail of an element under test;