JPH0766352B2 - Virtual computer system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a virtual computer system, and more particularly to processing of an address translation buffer holding address translation information of a host computer or guest virtual computer.

[Conventional technology]

In a virtual machine system, after a virtual machine execution start instruction (hereinafter referred to as SIE instruction) is executed by a host control program, the operation of the virtual machine (hereinafter referred to as VM) is usually started. For example, IBM's 370 / XA architecture is known as such a virtual machine architecture. This is detailed in JP-A-57-212680.

Figure 2 shows the instruction format of the SIE instruction. SIE instruction is B2
And a VM state descriptor (hereinafter referred to as SD) positioned by the D2 field is specified as an operand. Second
In the figure, 58 is a SIE instruction, 59 is a main memory area, and 60 is a VM state descriptor (SD).

The instruction execution unit of the central processing unit (hereinafter referred to as CPU) is the SIE
Main memory (hereinafter referred to as MS) for executing instructions
Set the information specified in each field of SD to SD to the hardware resource of CPU, and operate CPU as guest VM. At this time, the hardware resources to be set include a guest mode register, PSW, control register (CR), general-purpose register (GR), prefix and MS extend register, as shown in FIG. On the other hand, the host state is stored in the CPU. In this way, SD describes the architecture of the guest VM as seen from the guest instructions.

The guest VM initiated by the SIE instruction emulates the guest program until an interrupt event or interception occurs. An interrupt event is, for example, a case in which host processing such as input / output interrupt or external interrupt is required. Interception occurs, for example, at the time of executing an instruction that requires host processing. In some privileged instructions, whether or not to generate interception can be specified in the interception mask field in SD. When an interrupt event or interception occurs, the guest VM terminates, the CPU enters host mode, the state at the start of SIE instruction execution is restored, and the instruction counter in the PSW shows the SIE
Indicates the next instruction after the instruction.

One of the important technical issues in virtual computer systems is
This is a method of expressing the "main memory" of the guest. In the guest VM started by the SIE instruction, the page storage mode and the priority storage mode are used.

FIG. 3 shows the address space mapping in page storage mode. Guest virtual address (GV) 61
Is translated into a guest absolute address (GA) 62 by guest address translation. Check that this GA62 is within the MS extent specified in SD. The MS origin is added to GA to obtain the host virtual address (HV) 63. HVs are translated to host absolute address (HA) 64 by host address translation.

In preferred storage mode, the guest's absolute address is considered the host's absolute address.

The CPU has an address translation buffer to perform address translation at high speed. In either mode, a pair of GV and HA is registered in the address translation buffer (TLB) entry. Therefore, by referring to TLB in GV, HA can be immediately obtained.

TLB in virtual machine system with the above architecture
The structure is described in detail in JP-A-57-212680. There, a 1-bit guest field is provided in each entry of the TLB, and it is set to "0" when the address translation information of the host is registered and "1" when the address translation information of the guest VM is registered. This enables the host entry and the guest entry to be identified, and the address translation information of the host and one guest VM is held in the TLB at the same time.

[Problems to be solved by the invention]

In the conventional technique, the number of guest VMs that can be held in the TLB is controlled to one, and therefore, when a certain guest VM is executed, the TLB cannot hold the entries of other guest VMs. JP-A-57
According to Japanese Patent Laid-Open No. 212680, when execution of a guest VM is terminated by an interrupt event or interception, the guest VM
All guest entries for are disabled. Therefore, when the guest VM is started again by the SIE instruction,
When the page corresponding to the entry registered in the TLB at the time of ending the guest VM last time is accessed, a new address translation occurs, which causes an extra overhead in the instruction processing performance.

Figure 4 illustrates this, in the prior art guest VM
The guest entry in the TLB is always purged at the end of execution of the guest program (at the end of execution of the guest programs I and II in FIG. 4).
Guest VM (Guest Program) that is the same as Program I)
When II) is restarted, the TLB purge at the end of execution of the guest program I is unnecessary, and an extra overhead occurs in the instruction processing performance.

An object of the present invention is to provide a virtual computer system in which purging of TLB guest entries is carried out only when it is truly necessary to improve instruction processing performance. Here,
The true need to purge TLB guest entries is when two consecutively started guest VMs are different.

[Means for solving problems]

According to the present invention, at the end of execution of a guest VM, until the next execution of the guest VM is started, guest VM identification information (referred to as VMID) representing the guest VM is stored as a last guest VM identification information register ( LAST-VMID register) and guest VM
Act guest that stores the VMID of the guest VM at the start of execution
VM identification information register (called ACT-VMID register) and L
A means for comparing the AST-VMID register and the ACT-VMID register and a TLB guest entry purging means for holding or purging the guest entry of the TLB corresponding to the comparison result are provided.

[Work]

When a guest VM is started by executing the SIE instruction in the host management program, the value of the LAST-VMID register that holds the VMID of the guest VM that was executed last time and the guest that is about to start
Compare the value of the ACT-VMID register that stores VM.
Then, when the two match, the guest entry of the TLB is kept as it is and the execution of the guest VM is started. When the two do not match, all guest entries in the TLB are purged and the guest VM starts running. The LAST-VMID register
VMID is set, for example, at the end of execution of the guest VM,
It is held during the execution of the host program.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and particularly shows only a part of the central processing unit (CPU) of the virtual computer system that is related to the TLB reference.

In FIG. 1, the instruction execution unit 1 has a guest VM mode
Register (G mode register) 5, valid bit (V
Bit) register 6, ACT-VMID register 7, guest segment, table origin register (GSTO register) 8, host segment table origin
Register (HSTO register) 9, real mode (R mode) register 10, and TLB reference address register 11
Are connected. ACT-VMID register 7 is
Connected to T-VMID register 12.

As mentioned above, when the SIE instruction is executed in the host program, the guest VM starts executing. As the guest VM identification information, an SD address, a value of the VMID field in the SD, and the like are conceivable. Below, an example in which the SD address is the guest VM information (VMID) will be described.

The instruction execution unit 1 sets the G mode register 5 to "1" as the processing of the SIE instruction, sets the SD address in the ACT-VMID register 7, and sets the CR1 field value (MS origin) in SD to GST.
Set in O register 8. When the G mode register 5 is "0", the CPU operates as a host computer, and when it is "1", it operates as a guest virtual computer. When the execution of the guest VM is terminated by an interrupt event or interception in the guest program, the G mode register 5 is reset to "0" by the instruction execution unit 1. The GST register 8 is used for guest address translation and identifies the guest address space. The HSTO register 9 is used for host address translation and identifies the host address space. The HSTO register 9 and the GSTO register 8 are updated when the instruction execution unit 1 executes the LCTL instruction (instruction for rewriting the control register) in the host program and the guest program, respectively.

The R mode register 10 indicates whether the TLB reference is performed by a virtual address or a real address. The instruction execution unit 1 sets the address register 11 and the R mode register 10 and issues a TLB reference request, for example, when referring to the TLB 3 by reading an instruction or reading an operand.

TLB3 is set associative in this embodiment. That is, addressed by column address,
One or more entries selected by the column address are called rows. In this embodiment, the number of columns is 51
Although the TLB configuration has a total of 512 entries with 2, the number of rows is 1, the method of the present invention can be easily inferred for other configurations. The address is a 31-bit address of bits 1-31. The column address is bits 11-19 of the address. The TLB 3 decodes the column address part 24 of the address register 11 by the address decoder 14 and selects one entry to refer to.

Each entry of TLB3 includes a valid field (V), guest field (G), real address field (R), control field (C), segment table origin field (STO), virtual address field (VA),
It consists of an absolute address field (PA). In FIG. 1, the number of bits in each field is shown in parentheses.

The V field is a 1-bit field indicating whether the entry is valid or invalid. It is "1" when the entry is valid, and "0" when it is invalid.

The G field is a 1-bit field indicating whether the entry is the address translation information of the host or guest VM. It is "0" for the host and "1" for the guest VM.

The R field is a 1-bit field indicating whether the entry is referenced by a real address or a virtual address. When it is "0", it refers to the real address, and when it is "1", it refers to the virtual address.

The C field is a 1-bit field indicating that the entry is address translation information using a common segment. This field becomes "1" when the common segment bit of the referenced segment table entry is "1" in host address translation in host mode and guest address translation in guest VM mode.

The STO field represents the segment table origin when the address of the entry is translated. In the IBM370 / XA architecture, bits 1-25 of the STO represent an address and this field is 25 bits.

The VA field is a 10-bit field that stores bits other than the column address of the page frame address of the TLB reference, that is, bits 1-10.

The PA field stores 19 bits of the page frame address section of the absolute address.

The TLB hit determination unit 4 includes comparison circuits 15 to 18, an AND gate 20,
It is composed of an OR gate 19 and a negation gate 21. Comparison circuit 15
Is the G field output 46 of TLB3 and the output 32 of G register 5
Are compared, and if they match, "1" is output. The comparison circuit 15
Generate TLB hit condition specific to VM system. That is, in the host mode (G mode register 5 is “0”) and the G field 46 of the read TLB entry is “0”, or in the guest VM mode (G mode register 5 is “1”) and the read TLB entry is G field 46 is "1", TLB
It becomes a condition of hit. The OR gate 19 generates a TLB hit condition regarding the address space. That is, when the TLB entry is the common segment (the C field of the TLB is "1") or the STO value of the TLB entry matches the current STO output 44, "1" is output to the OR gate 19. The current STO
As the output 44, either the GSTO output 36 or the FSTO output 37 is selected by the selector 22 corresponding to the G mode register 5. The AND gate 20 produces the TLB hit signal 56 and the NOT gate 21 produces the TLB miss signal 57. TLB hit signal 56 and TLB PA field output 51
Is transferred to the cache controller. TLB miss signal 57
Is transferred to the address translation unit.

The TLB write control unit 2 controls TLB registration and TLB entry invalidation by address translation. G at the time of TLB registration
Field, R field, STO field, VA field are G mode register 5, R register 10,
The STO select output 44 and the address register 11 value are stored. Also, the C and PA fields are
The value transferred from the address conversion unit is stored. Also,
The V field is the VMID of the currently running guest VM (ACT-V
MID register 7) and the VMID of the guest VM that was executed last (LSA
When the ST-VMID register 12) matches, the comparison circuit 13 is set to "1".
Then, at that time and when V register is "1", V of TLB3
"1" is stored in the field.

When starting the execution of the guest VM, the instruction execution unit 1 sets the G mode register 5 to "1", compares the ACT-VMID mode register 7 and the LAST-VMID register 12, and when they match, that is, the comparison circuit 13 When it is "1", the guest VM is immediately executed, and when there is a mismatch, that is, when the comparison circuit 13 is "0", the V field of the guest entry of TLB3 is set to "0", and then the guest VM is executed.

When the execution of the guest VM ends, the instruction execution unit 1 resets the G mode register 5 to "0", restores the CPU state to the state when the SIE instruction was executed, and sets the VMID of the VM that has finished execution to AC.
The T-VMID register 7 to the LAST-VMID register 12 are stored. However, the PSW instruction address counter indicates the instruction following the SIE instruction. At this time, the guest entry of TLB3 is kept as it is.

With the above configuration, the guest entry of TLB3 can be purged after detecting a mismatch between the VMID of the newly executed VM and the VMID of the previously executed VM. Generally, the host management program manages multiple guest VMs and
Issue the E command to start the guest VM. As mentioned above, when dispatching from the host to the guest VM or from the guest VM to the host VM, all entries in the TLB are saved.
Therefore, when a guest VM is terminated and then continuously executed, it is possible to prevent unnecessary purging of the guest entry of the TLB, and to suppress the address translation activation in the guest VM to the necessary minimum number. .

〔The invention's effect〕

According to the present invention, in a virtual computer system, a guest
Guest VM and TLB guest VM that retains the VM identification information from the end of execution to the start of execution of the guest VM and starts with SIE instruction
By making it possible to identify the VM of the entry, unnecessary purging of the TLB guest VM entry when the guest VM started by the SIE instruction and the VM of the TLB guest VM entry match is eliminated, and the processing performance of the guest VM is improved. realizable. Moreover,
In the present invention, the processing of not purging the TLB guest VM entry is executed at the time of starting the execution of the guest VM (at the time of executing the SIE instruction).
It is possible to avoid unnecessary purging processing by performing only the above.

[Brief description of drawings]

FIG. 1 is a diagram showing a portion particularly related to TLB and TLB reference in a central processing unit of a virtual machine system in an embodiment of the present invention, and FIG. 2 is a diagram showing SIE instructions and VM state descriptors, Figure 3 is a diagram showing address translation in guest VM, 4
The figure shows that the guest VM is executed by the SIE instruction during execution of the host program. 1 ... Instruction execution unit, 2 ... TLB write control unit 3 ... TLB, 4 ... TLB hit determination unit 5 ... Guest mode register, 7 ... ACT-VMID register, 8 ... Guest STO register, 9 ... … Host STO register, 11 …… Address register, 12 …… LAST-VMID register, 56 …… TLB hit signal, 57 …… TLB miss signal, 58 …… SIE instruction, 59 …… Main memory, 60 …… Status descriptor.

Claims (1)

[Claims] 1. A central processing unit for supporting at least one guest virtual computer and a main storage device, wherein a state descriptor of the guest virtual computer is stored in the main storage device, and a guest virtual computer execution start command is issued. The state descriptor of the main memory device is specified, the central processing unit is set to the state indicated by the state descriptor, and the execution of the guest virtual computer is started, and the central processing unit is the host computer or the guest virtual computer. Is provided with a plurality of address translation buffers for holding the address translation information, and each entry of the address translation buffer is a field indicating whether the entry holds the address translation information of the host computer or the guest virtual computer (hereinafter referred to as guest An entry holding the address translation information of a virtual computer is called a guest computer entry. In a virtual computer system configured to refer to the address translation buffer during execution of the host computer or guest virtual computer, the guest virtual computer identification information is stored at least from the end of execution of the guest virtual computer to the next A means for holding until the execution start of the guest virtual computer is provided, and when the execution of the guest virtual machine is started, the held guest virtual machine identification information is compared with the identification information of the guest virtual machine to be executed, and if there is a mismatch The virtual computer system is characterized in that the guest computer entry in the address translation puffer is purged, and if the entries match, the purge is prohibited, and then the guest virtual computer is started to execute.