JPH0766364B2 - Memory common area access control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a low-speed transfer bus when a memory storing exclusive control information between processors is accessed by two kinds of buses, a high-speed transfer bus and a low-speed transfer bus. The occupancy request of the high-speed transfer bus is obtained after obtaining the occupancy permission, and the occupancy time of the high-speed transfer bus is shortened to improve the efficiency of memory access.

[Industrial application field]

The present invention relates to a memory common area access control method,
In particular, it relates to a memory common area access control method when accessing a memory by a bus having two types of transfer rates.

In the field of information processing, a memory is commonly accessed by a plurality of processors. In a multiprocessor system in which processors are tightly coupled, when one processor is accessing a predetermined common area, another processor or another device does not access the same common area,
Exclusive control information indicating permission / prohibition of access is provided in the memory or the like corresponding to each common area. When the processor or the device accesses the common area, the access is made by observing the state of the exclusive control information.

[Conventional technology]

Conventionally, as a method of shortening the access time of the memory having the above-mentioned common area, there are a method of speeding up the memory access and a method of making the bus occupation time as close as possible to the memory access time. The former is accomplished by technological development of a memory device, and the latter is achieved by using a high-speed transfer bus to access the memory, and a low-speed transfer bus when high speed is not required as much as the memory.

The conventional data processing system is configured as shown in FIG. The memory 1 having the exclusive control information group 1-1 is
The processors 3-1 to 3-m are connected via the high-speed transfer bus 2, and the processors 3-i to 3-m are connected to the processors 5-1 to 5-n (for example, input / output) via the low-speed transfer bus 4. Control device).

The system is provided with bus occupation request adjusting circuits 7-1 and 7-2, and the bus occupation request adjusting circuits 7-1 and 7-2 are provided.
-2 determines the priority of the device requesting the bus.

The bus occupancy request adjusting circuit 7-1 of the high-speed transfer bus 2 realizes the speedup of the bus by limiting the bus occupancy period by each processor only to the period during which each processor is actually accessing the memory.

Therefore, for example, when the processor 3-2 accesses the common area of the memory 1, the other processors 3-1 and 3-2 to 3-3
The following method is used to realize exclusive control with -m.
The exclusive control information has a 1-bit configuration to make the explanation easier to understand. When the bit is '1', the memory common area is being used by another processor, and when it is '0', the memory common area is the other processor. Is not in use.

Before the processor 3-2 accesses the common area,
A dedicated instruction for checking the exclusive control information, that is, an instruction generally called a "test and set instruction" is executed. This instruction is an instruction to read the above-mentioned exclusive control information in one memory access and at the same time set "1" to the exclusive control information area. Processor 3-2
The state of exclusive control information access by the above will be described with reference to FIG. Since this instruction is performed once in the memory access period (access cycle) as shown in FIG. 5B, the processor 3-2 operates the high speed transfer bus 2 as shown in FIG. 5A during that period. Occupy in. Therefore, other processors are the same between the time when the processor 3-2 reads the exclusive control information as shown in FIG. 5 (c) and the time of writing "1" as shown in FIG. 5 (d). The exclusive control information of No. 1 cannot be read, and the processor 3-2 occupies the high-speed transfer bus 2 as shown in FIG.

Of course, if the read exclusive control information is "0", the processor 3-2 can start accessing the common area. As described above, if the processor 3-2 writes "1" in the exclusive control information area, other Processor cannot access the common area any more. When a series of accesses to the common area is completed, the processor 3-2 writes "0" in the exclusive control information area to open the common area to another processor.

If the exclusive control information read by the "test and set instruction" is already "1", the processor 3-2 knows that the common area is already being used by another processor. , The processor 3-2 executes the test and set instruction again after a fixed time,
Check whether exclusive control information is '0' after the use of the common area by other processors is completed. In this way, exclusive control at the time of accessing the memory common area of the processors 3-1 to 3-m can be realized.

On the other hand, the bus occupation request adjusting circuit 7-2 that adjusts the priority of the low-speed transfer bus 4 requested by the processors 5-1 to 5-n is provided by the processors 5-1 to 5-n. When 4 is occupied, the bus is not opened unless a predetermined series of accesses is completed.

The state of exclusive control information access by the processor 5-1 will be described with reference to FIG. For example, before the processor 5-1 accesses the common area, in order to read the exclusive control information, the low-speed transfer bus is first occupied as shown in FIG. 6 (a). Thereafter, only in the memory access cycle (FIG. 6 (c)) for reading the exclusive control information, the high-speed transfer bus is occupied as shown in FIG. 6 (b), and the processor 5-1 is connected via the bus coupling circuit 8. Exclusive control information is taken in.

The processor 5-1 continues to occupy the low-speed transfer bus 4, and performs read access as shown in FIG.
If the exclusive control information is "0", "1" is written again in the exclusive control information area via the bus coupling circuit 8 as shown in FIG. 6 (e). Also in this case, the high-speed transfer bus is occupied as shown in FIG. 6 (b) only in the cycle in which the memory is actually written. After that, the processor 5-1 accesses the common area. After writing "1" to the exclusive control information area, the low-speed transfer bus 4 may be released once.

According to this method, the processor 5-1 reads the exclusive control information and writes "1" until the processor 5-1
Keeps occupying the low-speed transfer bus 4 during this period,
It is possible to prevent other processors 5-2 to 5-n from reading the same exclusive control information.

Therefore, exclusive control at the time of accessing the memory common area among the processors 5-1 to 5-n can be realized.

[Problems to be solved by the invention]

The conventional memory common area access control method described above is
Exclusive control between processors 3-1 to 3-m and processor 5
It was possible during each exclusive control between -1 to 5-n. Therefore, in the conventional method, for example, the processor 3
-2 and the processor 5-1 were unable to provide a common area for exclusive control.

This state will be described with reference to FIG. Processor 5-1
While the exclusive control information is written via the bus coupling circuit 8 after reading the exclusive control information by temporarily occupying the high-speed transfer bus as shown in FIG. 7 (b). As shown in FIG. 7 (d), the processor 3-2 occupies the high-speed transfer bus by the test and set instruction, reads the same exclusive control information as shown in FIG. 7 (e), and reads "1". There is a possibility of writing.

The processor 3-2 determines that the common area can be used because the read exclusive control information is "0" at that time. At the same time, the processor 5-1 also determines that the common area can be used because the read exclusive control information is "0". As a result, both processors 3-2 and 5-1 simultaneously use the common area, and the common area is shared. There is a problem that exclusive control of the area becomes impossible.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory common area access control method suitable for accessing the memory common area from the above conventional situations.

[Means for solving problems]

In the present invention, as shown in the principle diagram of FIG. 1, a memory (1) storing exclusive control information between processors and a memory (1) connected to the memory (1) via a high-speed transfer bus (2). The first processor (3-1 to 3-m), which is connected to the first processor (3-1 to 3-m) via the low-speed transfer bus (4), and the memory (1). And second processors (5-1 to 5-n) connected via the high-speed transfer bus (2) and the low-speed transfer bus (3),
High-speed transfer bus occupation request adjusting means (7-1) for adjusting the occupation request for the high-speed transfer bus (2) and low-speed transfer bus occupation request adjusting means (7- for adjusting the occupation request for the low-speed transfer bus (4). 2), a control unit (6-) for controlling the high-speed and low-speed bus occupation requests to the first processor (3-1 to 3-m).
i-6-m), and the first processor (3-1-3-1)
3-m) accesses the exclusive control information, the control means (6-i to 6-m) first informs the low-speed transfer bus occupation request adjusting means (7-2) to the low-speed transfer bus (4). Is output to occupy the low-speed transfer bus (4) to block access requests from the second processors (5-1 to 5-n) to the low-speed transfer bus (4). The occupancy request of the high speed transfer bus (2) is output to the high speed transfer bus occupancy request adjusting means (7-1).

[Action]

When the processors 3-i to 3-m access the exclusive control information of the memory 1, the control circuits 6-i to 6-, respectively.
When the control circuit, for example 6-i, outputs a bus occupation request for the low-speed transfer bus to the bus occupation request adjusting circuit 7-2 and permission for occupation is obtained, the bus occupation request adjusting circuit 7-1 performs high speed operation. Outputs an exclusive request for the transfer bus to enable exclusive control.

〔Example〕

FIG. 2 is a circuit diagram of an embodiment to which the present invention is applied, and will be described below with reference to the time chart of FIG. When the processor 3-m tries to access the common area of the memory 1, the CPU 30-m executes the test and set instruction. At this time, the bus request signal BRQ and the LOCK signal indicating the test and set instruction are sent to the control circuit 6-m as shown in FIG.

In the following description, it is assumed that all signals are output as logic "1".
Both signals BRQ and LOCK are input to the AND circuit 11-1 together with a signal indicating that the bus occupation request signal BRQB is not output to the bus occupation request adjusting circuit 7-1. Therefore, the AND circuit 11-1 outputs a logic "1" in the above state and sends the bus occupation request signal BRQA to the bus occupation request adjusting circuit 7-2 via the OR circuit 12-1. The bus occupancy request adjustment circuit 7-2 outputs a permission signal BGA when permitting use of the bus.

This permission signal BGA is applied to the FF circuit 10-2 and the FF circuit 1 of the control circuit.
It is input to 0-3. The FF circuit 10-3 outputs the busy signal BSYA with its output terminal Q being logic "1". On the other hand, FF circuit
10-2 outputs a logic "0" to the terminal and a logic "1" to the Q terminal.
And The logic "0" of the terminal is input to the AND circuit 11-1 and cancels the signal BRQA of the OR circuit 12-1.

The logic "1" at the Q terminal of the FF circuit 10-2 is the AND circuit 11-4.
Entered in. The other input of the AND circuit 11-4 is to detect that the bus request signal BRQ and the LOCK signal are logic '1', that is, the LOCK state during the bus request.
Input from. As a result, the AND circuit 11-4 outputs a logic "1" when the above logic "1" is established, and the OR circuit 12-
The bus occupancy request signal BRQB is sent to the bus occupancy request adjusting circuit 7-1 via the No.

When the bus occupation request adjusting circuit 7-1 outputs the permission signal BGB, the FF circuit 10-2 is cleared and the bus occupation request signal BRQB.
Cancel. Further, the permission signal BGB is Q of the FF circuit 10-1.
The terminal is set to logic '1' and the busy signal BSYB is sent to the bus occupation request adjusting circuit 7-1. Processor 3-m in this state
Accesses the exclusive control information area of the memory 1, reads the exclusive control information, and writes (MACC) a value "1" indicating that the common area is in use.

The AND circuit 11-2 reads the memory 1 in the MACC state in the UNLOCK state, that is, not the test and set instruction,
When writing, the output of the busy signal BSYB of the FF circuit 10-1 is prohibited, and the FF circuit 10-2 is supplied via the OR circuit 12-2.
-3 Output of busy signal BSYA is prohibited.

In the other end inputs of the OR circuits 12-1, 12-2, 12-3 used in the above description, signals input from a device requesting a bus separately from the present invention are described as other signals.

Although the access control of the common area of the memory has been described in the processor 3-m, it goes without saying that it is not hindered by other processors.

〔effect〕

As is apparent from the above description, according to the present invention, in order to access the common area of the memory, the processor connected to the high-speed transfer bus once occupies the low-speed transfer bus, so It is possible to prevent erroneous reading of exclusive control information by the connected processor, and it is extremely effective when the processors connected to different transfer buses access the common area of the memory as described above.

[Brief description of drawings]

1 is a block diagram of the principle of the present invention, FIG. 2 is a circuit diagram of an embodiment to which the present invention is applied, FIG. 3 is a signal time chart according to the present invention, and FIG. 4 is a configuration diagram of a conventional data processing system. 5 is a time chart showing an exclusive control information access state of the conventional processor 3-2, FIG. 6 is a time chart showing an exclusive control information access state of the conventional processor 5-1 and FIG. 7 is a conventional system. 9 is a time chart when the exclusive control information accesses of the processors 3-2 and 5-1 overlap. In the figure, 1 is a memory, 2 is a high-speed transfer bus, and 3-1 to 3-1.
3-m and 5-1 to 5-n are processors, 4 is a low-speed transfer bus, and 6-i to 6-m are control means.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toshiharu Oshima 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kiyo Sudo 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 56) References JP-A-60-68448 (JP, A)

Claims (1)

[Claims] 1. A memory storing exclusive control information between processors, a first processor connected to the memory via a high speed transfer bus, and a first processor and a low speed transfer bus. A second processor connected to the memory via the high-speed transfer bus and the low-speed transfer bus; a high-speed transfer bus occupancy request adjusting unit for adjusting an occupancy request for the high-speed transfer bus; In a system configuration including a low speed transfer bus occupation request adjusting means for adjusting an occupation request for a low speed transfer bus, the first processor is provided with a control means for controlling the high speed and low speed bus occupation requests, and the first processor is When accessing the exclusive control information, the control means first causes the low speed transfer bus occupancy request adjusting means to occupy the low speed transfer bus. Is output to occupy the low-speed transfer bus to block an access request from the second processor to the low-speed transfer bus, and then to the high-speed transfer bus occupancy request adjusting means to request the high-speed transfer bus occupancy request. A shared area access control device for a memory, which is controlled to output.