JPH0766632B2 - Digital audio player - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention detects an error in digital audio data reproduced in time series from a magnetic tape or the like, and reproduces the digital audio data based on the result of the detection. The present invention relates to a digital audio reproducing apparatus which corrects data and outputs it to a subsequent circuit.

[Prior Art] Conventionally, this kind of digital audio reproducing apparatus such as an 8 mm video tape recorder and a compact disk player has an error detecting circuit for detecting digital audio data reproduced in time series from a magnetic tape in a correction processing unit. The detection circuit detects an error in the audio data by using the CRC code of the input audio data, and generates a 1-bit correct / incorrect flag indicating the correctness, that is, an error flag. After the detection, the audio data is transmitted to the correction circuit to correct the error, and the corrected audio data is transmitted to the subsequent circuit.

The correction process of the correction circuit is performed by one of the following two methods.

(1) A method of transmitting an error flag of an error detection circuit together with audio data to a correction circuit and correcting the audio data by referring to the error flag by the correction circuit.

(2) Only the audio data is transmitted to the correction circuit, and the data pattern of the audio data in which the error flag is generated at this time is changed to a preset error pattern, for example, a pattern in which all bits are set to 1. A method to identify and correct erroneous audio data.

The method of (1) above is based on, for example, 42 of “Sanyo Technical Reville VOL.17 No.2” (issued in August 1985).
It is described on page 69.

[Problems to be solved by the invention]

By the way, when the correction process is performed by the method (1), the amount of data transmitted from the error detection circuit to the correction circuit is
Compared to the case where the correction process is performed by the method (2), the number of error flags is increased, and it is necessary to provide a memory (RAM) dedicated to the error flag, so that the memory capacity in the device and the number of bus lines are large. The problem is that the circuit scale becomes large.

On the other hand, when the correction process is performed by the above method (2),
One of the data patterns formed by audio data
One of them is set in advance as an error pattern, so that audio data having the same correct data pattern as the error pattern may be erroneously corrected, and the error pattern is not used in the data pattern to prevent erroneous correction. In this case, there is a problem that the information amount of audio data decreases and the quality deteriorates.

[Means for solving problems]

The present invention has been made in consideration of the above points, and detects an error in digital audio data reproduced in time series, and corrects the audio data based on the result of the detection to perform a subsequent circuit. In the digital audio reproducing apparatus for outputting to the digital audio reproducing apparatus, an error detecting circuit for detecting an error of reproduced audio data and generating a correct / incorrect flag, and the audio data inputted through the detecting circuit are inputted, and the input data is converted into one of the digital audio data. The first latch circuit for holding the sample period and the maximum value data of the inversion logic of the highest bit showing the positive or negative of the output data of the second latch circuit one sample period before the output data of the first latch circuit are generated. An inverting circuit and the maximum value instead of the output data of the first latch circuit when the correctness / incorrectness flag is an error flag Data is output to the second latch circuit, and output data of the second latch circuit is input, and the maximum value data is discriminated from the positive, negative and contents of the input data to input error data. A digital audio reproducing apparatus comprising a correction circuit for detecting and correcting the error data.

[Action]

Therefore, the error flag is not transmitted to the correction circuit as in the method (2) described above, and the digital audio data in which an error is detected has the correct audio data immediately preceding the audio data. ， Maximum value data of the maximum value opposite to negative is transmitted to the correction circuit.

And the digital audio data has a high correlation with the data before and after, and moreover, the maximum value is small,
The correction circuit identifies the maximum value data as error data from the positive, negative and contents of the input data, detects the input of the error data and corrects the data.

In this case, the maximum value data as the error data becomes the opposite sign data according to the positive or negative of the immediately preceding digital audio data, so that the positive maximum value data is assigned to the data of the peculiar pattern of the error data, for example. No need to
All the data patterns including the positive and negative maximum value data can be used for the digital audio data, and the amount of information is not reduced.

〔Example〕

Next, the present invention will be described in detail with reference to FIG. 1 showing one embodiment thereof.

In FIG. 1, (1) is an input terminal to which N-bit digital audio data reproduced in time series from a magnetic tape or the like is input in the bit serial, and (2) is a serial / parallel connected to the input terminal (1). This is an exchange circuit and outputs the input audio data in N-bit parallel. MSB and LSB in the figure are the highest N bits,
The line of the lowest bit is shown.

(3) is an error detection circuit connected to the conversion circuit (2), which detects an error in the input audio data by using a CRC code of the data, and when the error is detected, "1", positive At the same time, a 1-bit error flag of "0" is generated and the generated error flag is output to the flag latch circuit described later.

(4) is a flag latch circuit to which the error flag of the detection circuit (3) is input. Based on the first latch pulse signal of the input terminal (5), the detection circuit (3) detects an error in the next audio data. The input error flag is held and output for one sample period until the detection is completed.

(6) is a first latch circuit for data connected to the detection circuit (3), and based on the first latch pulse signal of the input terminal (5), the audio data input through the detection circuit (3) is It is delayed for one sample period and output.

(7) is N 2-bit selectors (7a), ..., With two input terminals (a) and (b) and a switching control terminal (s).
An information selection circuit consisting of (7n), each selector (7a)
Each bit of the audio data output from the latch circuit (6) is input to the input terminals (b) of (7n) to (7n) and the error flag "1" output from the latch circuit (4) to the switching control terminal (s). Based on "0", when the error flag is "1", it is switched to one input terminal (a), and when the error flag is "0", it is switched to the other input terminal (b).

(8) is a second latch circuit for data connected to the output terminals of the selectors (7a) to (7n). Based on the first latch pulse signal, one sample of the N bit output data of the selector circuit (7) is output. Hold for a period and output.

(9) is an inverting circuit composed of N inverters (9a), ..., (9n), and the highest bit of the output data of the latch circuit (8) is input to each of the inverters (9a) to (9n), N-bit positive or negative maximum value data obtained by inverting the logic of the most significant bit of the output data of the latch circuit (8) by each inverter (9a) to (9n), that is, all bits are "1" or "0". Maximum value data is formed, and each bit of the formed maximum value data is output from the inverters (9a) to (9n) to the input terminals (a) of the selectors (7a) to (7n).

Reference numeral (10) is a correction circuit to which the output data of the latch circuit (8) is input, and compares the positive and negative signs of the output data of one sample period before and the input output data, and the input output data. The error data is identified and corrected based on the contents of (1), and the corrected N-bit audio data is output.

Reference numeral (11) is a third latch circuit for data to which the output data of the correction circuit (10) is input, and the input data is delayed and held for one sample period based on the second latch pulse signal of the input terminal (12). Output.

Reference numeral (13) is a fourth data latch circuit which is connected in cascade to the latch circuit (11) and delays and outputs the input data for one sample period based on the second latch pulse signal.

(15) is an N-input AND gate to which each bit of the output data of the latch circuit (11) is input, and (16) is an N-input NAND gate to which each bit of the output data of the latch circuit (11) is input, ( 17) is an inverter that inverts and outputs the most significant bit of the output data of the latch circuit (11), and (18) is an AND gate to which the output signal of the inverter (17) and the output signal of the AND gate (15) are input. , (19) is an AND gate to which the signal of the highest bit of the latch circuit (11) and the output signal of the NAND gate (16) are input, and (20) is the output signal of both AND gates (18) and (19). It is the input OR gate.

(21) is an AND gate (15), (18), (19) and a NAND gate (16), an inverter (17), an OR gate (2
0) is a flag reforming circuit formed by the latch circuit (1
Correction circuit (10) based on the output data of 1) and (13)
The error flag is recreated based on the audio data output from.

Then, the audio data input to the input terminal (1) by bit serial is output from the conversion circuit (2) to the detection circuit (3) in bit parallel. At this time, the audio data is AC signal data. In the audio data output from the circuit (3), the most significant bit indicates whether the data is positive or negative. When it is positive, it becomes "1", when it is negative, it becomes "0", and all bits are "1". The range varies from the positive maximum value of "0" to the maximum negative value of "0", that is, the range of all data patterns formed by N bits.

Further, the detection circuit (3) detects an error in the audio data by using the CRC code of the input audio data, and at this time, based on the detection result,
A one-bit error flag indicating right or wrong is generated, and the error flag is input to the latch circuit (4).

When no error is detected, that is, when the latch circuit (4) outputs an error flag of "0", each selector (7a) to (7n) is held in the input terminal (b),
At this time, the detected audio data output from the detection circuit (3) is input to the latch circuit (8) via the latch circuit (6) and the selection circuit (7).

By the way, since the latch circuits (6) and (8) operate simultaneously by the first latch pulse signal, when the audio data of the detection circuit (3) is input to the latch circuit (6), the latch circuit (8). The audio data of one sampling period before is output from.

Therefore, each inverter (9a) to (9n) of the inverting circuit (9)
The most significant bit of the output data of the latch circuit (8) one sample period before is always input to.

Then, when an error is detected by the detection circuit (3) and an error flag of "1" is output from the latch circuit (4),
Each of the selectors (7a) to (7n) is switched to the input terminal (a). At this time, the selection circuit (7) replaces the audio data output from the latch circuit (6), that is, the audio data in which an error is detected. The N-bit data output from the inverting circuit (9) is input to.

Now, if the audio data one sample period before the audio data in which the error is detected is positive data, that is, if the most significant bit is "1", the negative maximum of all the bits "0" showing the minimum value. Value data is output from the inverting circuit (9), and conversely, if the audio data one sample period before the audio data in which the error is detected is negative data, that is, the highest bit is "0", The maximum positive value data of all bits "1" indicating the maximum value is output from the inverting circuit (9).

Therefore, when the audio data in which an error is detected is output from the detection circuit (3), the maximum value data having the opposite sign to the audio data one sample period before is output to the latch circuit (8) instead of the audio data. ) Is entered.

Then, the audio data and the maximum value data output from the latch circuit (8) are input to the correction circuit (10), and the correction circuit (10) outputs one sample period before when the input data is the maximum value data. Since it is the maximum value data of the opposite sign of the data input to, it is identified that the input data is the alternative data of the audio data in which the error is detected, and the data before and after the input data is identified. Correction processing is performed using the data of. For uncorrectable data, the input maximum value data is output as it is.

By the way, in the case of audio data in which no error is detected, the data input to the correction circuit (10) becomes data having a correlation with the previous and subsequent data, and has the opposite sign of the data input one sample period before. The maximum value of data is rarely input to the correction circuit (10), and it is rare for audio data for analog audio signals up to 1/4 of the sampling frequency when audio data is formed. .

Therefore, the correction circuit (10) performs the correction process more accurately than the conventional method (2) by referring to the error flag and using all the N bit patterns as the audio data pattern.

Then, the data corrected by the correction circuit (10) is transmitted to the interpolation circuit or the like via the latch circuits (11) and (13), and at this time, an error flag is necessary for the interpolation process and the like. In this embodiment, the error flag is reformed by the reforming circuit (21) based on the output data of the correction circuit (10).

That is, if the correction process fails to correct,
The maximum value data that has been input is output from the correction circuit (10) to the latch circuit (11).

When the output data of the latch circuit (11) becomes positive or negative maximum value data, the output signal of the AND gate (15) or the output signal of the NAND gate (16) becomes "1".

On the other hand, data of the output data of the latch circuit (11) one sample period before is output from the latch circuit (13).

Then, the most significant bit signal of the output data of the latch circuit (13) and the signal obtained by inverting the signal by the inverter (17) are input to the AND gates (19) and (18), respectively, and the AND gate (18) , (19) and gate (1
5) Since each output signal of the NAND gate (16) is input, the maximum positive or negative value data of the opposite sign to the data one sample period before from the latch circuit (13), that is, the maximum value data that has not been corrected. Is output,
The output signal of the AND gate (18) or (19) becomes "1", and the OR gate (20) outputs an error flag indicating whether the output data of the latch circuit (13) is correct or incorrect.

Therefore, the correction circuit (10) can perform correction processing based on only the input data without transmitting the error flag generated by the detection circuit (3) to the correction circuit (10). Since the memory capacity and the bus line are reduced, the circuit scale becomes small. At this time, the audio data in which an error is detected by the detection circuit (3) is processed by the correction circuit (10) one sample period before. Since the maximum value data of the opposite sign to the data is input, the correct audio data and the maximum value data in place of the audio data in which the error is detected are accurately used by using the positive and negative maximum value patterns of the audio data. Therefore, correct correction can be performed without reducing the information amount of audio data.

As described above, the frequency that can be accurately identified and corrected is 1/4 or less of the sampling frequency of audio data. For example, when applied to a compact disc player, the sampling frequency is 44.1%.
Since it is KHz, correction processing can be performed without error on an analog voice signal having a frequency of 11 KHz or less, and normally, there is almost no component of 10 KHz or more in the analog voice signal, so that no practical inconvenience occurs.

Of course, the subsequent circuit of the correction circuit (10) may be different from that of the embodiment.

〔The invention's effect〕

As described above, according to the digital audio reproducing apparatus of the present invention, when an error is detected by the error detecting circuit, the maximum value data having the opposite sign to the immediately preceding digital audio data is used instead of the digital audio data. Is transmitted as error data to the correction circuit, and the correction circuit detects the maximum value data as error data from the positive, negative, and contents of the input data and corrects it. Accurate correction processing can be performed by reducing the circuit scale of the device.

Furthermore, since the maximum value data as error data becomes the data of the opposite sign depending on the positive or negative of the previous digital audio data, it is not necessary to previously assign a specific pattern of digital audio data to the error data. There is no limitation on the pattern of digital audio data, and the amount of information does not decrease.

Therefore, the error flag can be omitted and error data can be corrected without reducing the amount of information, the reproduction quality can be prevented from being deteriorated, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the digital audio reproducing apparatus of the present invention. (3) ... error detection circuit, (4) ... flag latch circuit, (6), (8) ... data first and second latch circuits,
(7) …… Information selection circuit, (9) …… Inversion circuit, (10)
... correction circuit.

Claims (1)

[Claims] 1. A digital audio data reproducing apparatus for detecting an error in reproduced digital audio data and correcting the audio data based on a result of the detection and outputting the corrected data to a subsequent circuit. An error detection circuit for detecting an error in the error detection circuit and generating a correct / incorrect flag, a first latch circuit that receives the audio data through the detection circuit and holds the input data for one sample period of the digital audio data, and the first latch. An inverting circuit for generating maximum value data of the inversion logic of the highest bit indicating the positive or negative of the output data of the second latch circuit one sample period before the output data of the circuit; Information that outputs the maximum value data to the second latch circuit instead of the output data of the first latch circuit. A correction for inputting the output data of the report selection circuit and the second latch circuit, identifying the maximum value data from the positive, negative and contents of the input data to detect the input of error data, and correcting the error data. A digital audio playback device characterized by including a circuit.