JPH0766868B2 - Discharge lamp lighting control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a discharge lamp lighting control device for lighting a discharge lamp at a high frequency.

[Prior Art] Conventionally, as a discharge lamp lighting control device for lighting a discharge lamp at a high frequency, a discharge lamp lighting circuit (for example, a half-bridge type inverter circuit) that has a pair of switching elements connected in series and that lights a discharge lamp at a high frequency. ) And a pulse generation circuit that alternately turns on and off both of the switching elements to form a two-phase clock signal whose on / off duty can be set, and a non-overlap section is provided in the two-phase clock signal. There was something I did.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, since the non-overlap section of the two-phase clock signal is fixed at the circuit design stage, the design change of the discharge lamp lighting circuit, the parts However, if the constants of the discharge lamp lighting circuit change due to variations in the characteristics of the discharge lamp, the setting of the non-overlap interval may become inappropriate, and the discharge lamp may not light normally. Therefore, it is necessary to design the circuit with a margin in consideration of changes in various constants of the discharge lamp lighting circuit, or to change the circuit specifications of the pulse generation circuit in accordance with the design change of the discharge lamp lighting circuit. There was a problem that was troublesome.

The present invention has been made in view of the above points, and an object of the present invention is to perform discharge lamp lighting in which the circuit design of the pulse generation circuit can be easily performed without considering changes in various constants of the discharge lamp lighting circuit. It is to provide a control device.

[Means for Solving the Problem] A discharge lamp lighting control device according to the present invention includes a discharge lamp lighting circuit that includes a pair of switching elements connected in series and that turns on a discharge lamp at a high frequency, and alternately turns on both switching elements. ,
A discharge lamp lighting control device comprising a pulse generation circuit that forms a two-phase clock signal to be turned off, and a non-overlap section is provided in the two-phase clock signal,
A non-overlap interval setting means is formed by a presettable counter that counts clock signals and a setting switch that inputs preset data of the presettable counter, so that the non-overlap interval is set based on the output of the presettable counter. The pulse generator circuit is configured in the.

[Operation] The present invention is configured as described above, and the discharge lamp lighting circuit equipped with a pair of switching elements connected in series lights the discharge lamp at a high frequency, and alternately turns on and off both of the switching elements. In a discharge lamp lighting control device in which a two-phase clock signal is provided with a non-overlap interval, a non-overlap interval is set based on the output of a presettable counter that counts clock signals, and the presettable counter is set. Since the non-overlap interval setting means is formed so that the preset data can be set by the setting switch, the non-overlap interval can be easily changed by the setting switch, and changes in various constants of the discharge lamp lighting circuit are taken into consideration. Circuit design of the pulse generation circuit without That.

[Embodiment] FIGS. 1 to 7 show an embodiment of the present invention. A two-phase clock OU for controlling on / off of a pair of series-connected transistors of a half-bridge type discharge lamp lighting circuit 10.
The pulse generation circuit that forms T ₁ and OUT ₂ includes a data latch circuit 1 that latches “H” section setting data and “L” section setting data of the output pulse signal, and a clock signal of a fixed cycle.
It is composed of a presettable counter circuit 2 that counts CLK and alternately sets the setting data of both sections, and a toggle flip-flop circuit 3 that uses the ripple carry signal RCY from the counter circuit 2 as a trigger clock. By providing the pulse width control means for changing the setting data independently, the toggle flip-flop circuit 3 obtains the pulse width modulated output pulse signal OUT. In the embodiment, the pulse width control means is formed by the microprocessor, and the "H" section setting data, "L" output from the microprocessor.
The section setting data is input terminals IN _{1 to} I of the data latch circuit 1.
It is adapted to be latched by the timing signal input to N ₁₂ and output from the timing control circuit 4.

Here, the data latch circuit 1 is composed of a primary buffer 1a and a secondary buffer 1b, and both buffers 1a and 1b are composed of a flip-flop and a T buffer as shown in FIGS. 2 and 3. There is. In the primary buffer 1a, when the section data set signal HL is input, the input terminals IN _{1 to} I
Latch signal LATCH _A , L for DT ₁ to DT ₁₂ input via N ₁₂
ATCH "H" section setting data DA ₁ to DA ₁₂ by _B, and so as to latch a "L" section setting data DB ₁ to DB _12. Further, in the secondary buffer 1b, the latch data DA ₁ to DA ₁₂ of the primary buffer 1a by a latch signal LTCH, DB ₁ to DB ₁₂
Captures, and outputs an enable signal EN _A, EN _B segment is selected by the configuration data DA ₁ to DA ₁₂ or DB ₁ to DB ₁₂ of the counter circuit 2 as preset data. The half clock control signal HLF is also latched once and output as the signal HALF.

Further, the counter circuit 2 and the toggle flip-flop circuit 3 are integrated as a counter / output circuit 5,
As shown in FIG. 4, a 12-bit counter circuit 2 is formed by using three 4-bit presettable counters,
The ripple carry signal RCY of the counter circuit 2 is input as a trigger clock signal RCY ′ to the toggle flip-flop circuit 3 via the half clock control circuit 6.
The output of the toggle flip-flop circuit 3 is output as an output pulse signal OUT via two inverters, and at the same time, enable signals EN _A and EN _{B for} reading out predetermined preset data from the data latch circuit 1 are output. Has become. Here, the half clock control circuit 6 shifts the rising edge of the ripple carry signal RCY (the inversion timing of the toggle flip-flop circuit) to the right by half a clock when the half clock control signal HALF is “H”, and the clock signal CLK It is possible to set "H" section and "L" section with half clock precision (double precision).

Further, the timing control circuit 4 uses the latch signals LATCH and LATC.
H _A , LATCH _B , LTCH generating latch control circuit 4a as shown in FIG. 5 and clear signal CLEAR, load signal LOAD, latch signal LTCH ₁ generating counter control circuit 4b as shown in FIG. A predetermined timing signal is output based on the clock signal CLK, the start signal START, and the section data set signal HL output from the microprocessor, and the operation timing of each circuit is controlled.

By the way, in the embodiment, the output pulse signal is used as the output signal for controlling the switching of the two-phase clock generation circuit 7 for generating the two-phase clock signals OUT ₁ and OUT ₂ based on the output pulse signal OUT and the discharge lamp lighting circuit 10. An output switching circuit 8 for switching between outputting OUT or outputting two-phase clock signals OUT ₁ and OUT ₂ by a switching signal SE / HB is provided, and a single end type (output pulse signal OU
Discharge lamp lighting circuit of 1-stone inverter system in which switching transistor is controlled by T) or half-bridge type (2-stone inverter system in which a pair of switching transistors connected in series by 2-phase clock signals OUT ₁ and OUT ₂ is controlled) 10 switching control signals are available. Here, the two-phase clock generation circuit 7 counts the clock signal CLK and sets a non-overlap interval based on a presettable counter circuit 7a and a ripple carry signal RCY ₂ ′ output from the presettable counter circuit 7a. is formed by the gate control circuit 7b that controls the gate circuit 7c, 2-phase clock signals non-overlap period is set based on the non-overlap interval setting data HB ₁ ~HB ₈ set in 8-bit configuration switch
OUT ₁ and OUT ₂ are output.

The operation of the embodiment will be described below with reference to the time charts shown in FIGS. 8 and 9. FIG. 8 is a waveform diagram showing the basic operation of this embodiment. First, when the start signal START output from the microprocessor rises, the system is reset. Next, "H" section setting data
When DA _{1 to} DA ₁₂ are confirmed, the interval data setting signal HL rises from the microprocessor and the latch signal LATCH _A becomes 1
The primary buffer 1a of the data latch circuit 1 is output as a pulse.
The "H" section setting data DA _{1 to} DA ₁₂ are latched at. Next, when the “L” section setting data DB _{1 to} DB ₁₂ are confirmed, the latch signal LATCH _B becomes 1 at the fall of the section data setting signal HL.
The pulse is output and the “L” section setting data DB _{1 to} DB ₁₂ are latched in the primary buffer 1 a of the data latch circuit 1.

Next, the clear signal CLEAR goes to “L” and the latch signal LTCH
Is output as 1 pulse, and both section setting data DA _{1 to} DA ₁₂ , DB ₁
~ DB ₁₂ is latched in the secondary buffer 1b. At this time, since the enable signal EN _A is “H”, the “H” section setting data DA _{1 to} DA ₁₂ is read from the secondary buffer 1b,
When the load signal LOAD for setting the preset data to the counter circuit 2 is output, the “H” section setting data DA _{1 to} DA ₁₂ is set to the counter circuit 2. In this state, the counter circuit 2 starts counting the clock signal CLK, and when all the outputs Q _{1 to} Q ₁₂ of the counter circuit 2 become “H”, the ripple carry signal RCY is output. This ripple carry signal RCY causes the enable signal EN _{B to} be “H”.
And at the same time, the output pulse signal OUT also becomes "H". Then, the section setting data DB _{1 to} DB ₁₂ are preset in the counter circuit 2 and the counter of the clock signal CLK is started,
When the ripple carry signal RCY is obtained, the output pulse signal becomes "L" and the enable signal EN _A becomes "H", and the above-described operation is repeated. Thus, (at the 12-bit range) "H" period and the "L" period is arbitrarily output pulse signal OUT based on both the section setting data DA ₁ to DA _12, DB ₁ to DB ₁₂ can be set, on, off The duty can be set. When changing the ON / OFF duty, set the "H" section setting data DA _{1 to} D
After setting A ₁₂ , the section data setting signal HL is set to “H”, “L” section setting data DB _{1 to} DB ₁₂ is set, and then the section data setting signal HL is set to “L”.

For example, as shown in FIG. 8, when the frequency of the clock signal CLK is 16 MHz (cycle 62.5 nsec) and the “H” section is set to 161 pulses and the “L” section is set to 164 pulses, the “H” section is set. Set the 8th and 6th bits of setting data DA _{1 to} DA ₁₂ to “1”, and set the 8th bit, 6th bit, 2nd bit and 1st bit of “L” section setting data DB _{1 to} DB ₁₂ Set to "1". In this case, the output pulse signal
The OUT cycle is 325 pulses of the clock signal CLK. 2
It is 0.2 μsec and the frequency is 49.2 kHz. Further, if the width of the “H” section or the “L” section is widened by one pulse (62.5 nsec), the cycle becomes 326 pulses of the clock signal CLK and the frequency becomes 49.1 kHz. Therefore, in the embodiment, the “H” section or the “L” section of the output pulse signal OUT is set to 6
It can be set in 2.5nsec increments and frequency can be controlled in 0.1kHz increments.This setting precision has a setting precision that cannot be achieved with a discharge lamp lighting control device that uses a software-like internal counter by a microprocessor.
When used as a switching control signal of the discharge lamp lighting control device, fine lighting control can be performed. Needless to say, the setting accuracy can be increased by increasing the frequency of the clock signal CLK counted by the counter circuit 2.

Next, FIG. 9 is a diagram for explaining the operation of the half clock control. Now, the half clock control signal HLF output from the microcomputer (that is, the data latch circuit 1
When the signal HALF) output from is at "L", the ripple carry signal RCY becomes the trigger clock of the toggle flip-flop circuit 3 as it is, and the ripple carry signal RCY rises as shown in FIG. 9 (b). The output pulse signal OUT is inverted periodically. On the other hand, when the half clock control signal HLF becomes "H", the rising edge of the ripple carry signal RCY is shifted to the right by half a clock as shown in FIG. 9 (a), and the shifted ripple carry signal RCY 'is changed. The inversion operation of the output pulse signal OUT is performed by using the trigger clock of the toggle flip-flop circuit 3. Therefore, the half clock control signal HLF
If "H" is set, the "H" section or "L" section is set in comparison with the case of FIG. 9 (b) in which the section setting data DA _{1 to} DA ₁₂ and DB _{1 to} DB _{12 are} set. Since it can be widened by half the clock of CLK, the setting accuracy of the “H” section and the “L” section can be doubled without increasing the frequency of the clock signal CLK, and cheap circuit elements can be used.
The cost can be reduced. Further, the half clock control can be automatically performed by synchronizing the half clock control signal HLF with the section data setting signal HL. That is, section setting data DA _{1 to} DA ₁₂ , DB _{1 to} DB
_By inputting the half clock control signal HLF at the time of inputting ₁₂ , it becomes possible to change the frequency f of the output pulse signal OUT at regular intervals to perform stepwise dimming of the discharge lamp and soft start. There is. FIG. 10 (a) shows an example of a change in frequency f when the discharge lamp is soft-started without half-clock control, and FIG. 10 (b) is a frequency when soft-start is performed with half-clock control. An example of changes in f is shown. When half clock control is performed, the change width of frequency f can be halved compared to the case where half clock control is not performed, and smooth soft start by fine step dimming. You can see that

Next, the 2-phase clock generating circuit 7, so as to set the non-overlap interval by counting the clock signal CLK the non-overlapping section setting data HB ₁ ~HB ₈ is at a preset presettable counter circuit 7a And
As shown in FIG. 11, a gate control signal for controlling the gate circuit 7c is formed based on the ripple carry signal RCY ₂ ′ output from the presettable counter circuit 7a, and the gate circuit controlled by this gate control signal is formed. Non-overlap interval is added to the output pulse signal OUT by 7c 2
The phase clock signals OUT ₁ and OUT ₂ are formed.

The output pulse signal OUT and the two-phase clock signals OUT ₁ and OUT ₂ generated as described above are adapted to be output via the output switching circuit 8, and the output switching signal OUT
When SE / HB is "H", output pulse signal OUT is output, and when output switching signal SE / HB is "L", 2-phase clock signal O
UT ₁ and OUT ₂ are output. Therefore, the output switching signal
By appropriately setting SE / HB, it is possible to obtain a discharge lamp lighting control device that can support the single-ended or half-bridge type discharge lamp lighting circuit 10.

[Advantages of the Invention] The present invention is configured as described above. The discharge lamp lighting circuit is provided with a pair of switching elements connected in series, and the discharge lamp is lit at high frequency. In a discharge lamp lighting control device in which a two-phase clock signal to be turned off is provided with a non-overlap interval, a non-overlap interval is set based on the output of a presettable counter that counts clock signals, and the presettable counter is set. Since the non-overlap interval setting means is formed so that the preset data to be set can be set by the setting switch, the non-overlap interval can be easily changed by the setting switch, and the constants of the discharge lamp lighting circuit can be changed. The effect that the circuit design of the pulse generation circuit can be done easily without considering There is a fruit.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIGS. 2 to 7 are main circuit diagrams of the same, and FIGS. 8 to 11 are operation explanatory diagrams of the same. 1 is a data latch circuit, 2 is a counter circuit, 3 is a toggle flip-flop circuit, 4 is a timing control circuit, 7 is a two-phase clock generation circuit, and 8 is an output switching circuit.

Claims (1)

[Claims] 1. A discharge lamp lighting circuit comprising a pair of switching elements connected in series for lighting a discharge lamp at a high frequency, and a pulse generation circuit for forming a two-phase clock signal for alternately turning on and off both switching elements. The above 2
In a discharge lamp lighting control device in which a phase clock signal is provided with a non-overlap interval, a non-overlap interval setting means is provided with a presettable counter for counting clock signals and a setting switch for inputting preset data of the presettable counter. A discharge lamp lighting control device, wherein a pulse generation circuit is formed so that a non-overlap interval is set based on the output of the presettable counter.