JPH0766974B2 - Tunnel transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor utilizing a tunnel phenomenon, which can be highly integrated and can operate at high speed.

[0002]

2. Description of the Related Art Utilizing tunnel development at a p ⁺ -n ⁺ junction on the surface of a semiconductor, a conventional Si MOSFET or Ga is used.
A tunnel transistor has been proposed as a transistor whose operating principle is different from that of As MESFET. Regarding this device, for example, Japanese Patent Application No. 3 by Baba and Uemura
No. 3,415,594. This transistor positively utilizes the avalanche and tunnel effect, which are problems at the limit of miniaturization of MOSFET, and enables high integration. The structure and operation of this conventional tunnel transistor will be briefly described with reference to the structural diagram.

FIG. 2 is a schematic diagram of the structure of a conventional tunnel transistor. In FIG. 2, 1 is a non-degenerate substrate, 2 is a degenerate first semiconductor having one conductivity type, 3
Is a non-degenerate second semiconductor, 5 is a fourth semiconductor having a conductivity type opposite to that of the first semiconductor, and 6 is a second semiconductor 3.
A fifth semiconductor provided above, 7 is a gate electrode provided on the fifth semiconductor, 8 is a source electrode forming ohmic contact with the first semiconductor 2, and 9 is ohmic contact with the fourth semiconductor. It is a drain electrode to be formed.

Regarding the operation of this conventional tunnel transistor, semi-insulating GaAs is used for the substrate 1, n ⁺ -GaAs is used for the first semiconductor 2, and undoped GaA is used for the second semiconductor 3.
s, p ⁺ -GaAs on the fourth semiconductor 5 and the fifth semiconductor 6
N-Al _{0 to. 3} Ga _{0. 7} As an undoped Al _{0 thereon. 6} Ga _{0. 4} obtained by laminating As, Al gate electrode 7, AuGe source electrode 8, the AuZn the drain electrode 9 cases Explained. Since n-type ionized impurities are added to the fifth semiconductor 6, two-dimensional electron gas is accumulated on the surface of the second semiconductor (undoped GaAs) due to the modulation doping structure (indicated by "-" in the figure). . When the concentration of this two-dimensional electron gas is high and the surface of the second semiconductor is degenerated, a junction similar to an Esaki diode (tunnel diode) is formed between the second semiconductor surface and the p ⁺ -GaAs layer 5 which is the fourth semiconductor. It When a voltage is applied between the source and drain in this state, a tunnel current flows. The tunnel barrier width changes depending on the concentration of the secondary electron gas, and the tunnel current is modulated. However, since the concentration of the two-dimensional electron gas can be controlled by the gate voltage, the transistor operation is realized.

[0005]

In this device, since a two-dimensional electron gas is accumulated on the surface of the second semiconductor by adding an impurity to the fifth semiconductor, it is necessary to accumulate electrons of higher concentration. It is necessary to increase the amount of this impurity added. However, the amount of this impurity added is limited, and the two-dimensional electron gas concentration is limited. Moreover, if the amount of impurities added is large, the gate insulating property deteriorates, and the gate leakage current increases. Therefore, high current density operation is difficult.

[0006]

In a transistor of the present invention, a degenerate first semiconductor having one conductivity type, a non-degenerate second semiconductor, and a third semiconductor having the same conductivity type as the first semiconductor. A semiconductor, and a structure in which a degenerate fourth semiconductor having an opposite conductivity type to the first semiconductor is adjacent,
A fifth layer which is made of a material having a band gap wider than that of the second and third semiconductors on at least the surfaces of the second and third semiconductors and partially or entirely contains ionized impurities, and the fifth layer. Is characterized by having a Schottky electrode on the layer and having electrodes for forming ohmic junctions in the first semiconductor and the fourth semiconductor, respectively.

[0007]

According to the present invention, a third semiconductor doped with an ionized impurity having the same conductivity type as the first semiconductor is inserted between the second and fourth semiconductors of the conventional tunnel transistor described above. As a result, carriers having a higher concentration than the surface of the second semiconductor can be accumulated on the surface of the third semiconductor, and the tunnel current increases.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments.

FIG. 1 is a schematic diagram showing an embodiment of the present invention. In FIG. 1, the same symbols as those in FIG. 2 are equivalent to those in FIG. 2 and perform the same functions. Further, 4 is a third semiconductor. Hereinafter, the semi-insulating GaAs and the first semiconductor 2 are formed on the substrate 1.
Is n ⁺ -GaAs, and the second semiconductor 3 is undoped GaA.
s, the third semiconductor 4 is n ⁺ -GaAs, the fourth semiconductor 5
P ⁺ -GaAs, n-Al ₀ to the fifth semiconductor 6 _{in. 3} G
a _{0. 7} undoped Al ₀ on the _{As. 6} Ga _{0. 4} A
s formed, Al on the gate electrode 7, source electrode 8
And AuZn for the drain electrode 9 will be described. Since the n-type ionized impurity is added to the third semiconductor, the amount of electrons accumulated by the modulation doping structure is the second.
Will be larger than that of semiconductors. Therefore, the electron concentration at the drain (p ⁺ -GaAs) end becomes higher than that in the conventional structure, and as a result, the tunnel barrier width becomes smaller, which leads to an increase in tunnel current density.

Fabrication of the device is as follows. From the first semiconductor to the fourth on the substrate by molecular beam epitaxy
N ⁺ -GaAs (1x10 ¹⁹ cm
^-3 , 300 nm), undoped GaAs (200 n
m), n ⁺ -GaAs (2 × 10 ¹⁹ cm ⁻³ , 5n
m), p ⁺ -GaAs (5 × ^{10 19} cm ⁻³ , 100
nm) is sequentially grown at a substrate temperature of 520 ° C. Then, the drain region is left in a mesa shape by lithography and etching to expose a part of the first semiconductor, n ⁺ -GaAs. After cleaning by organic cleaning, the sample was again introduced into the MBE device, and n-A was formed on the surface of the formed structure.
_{l 0. 3 Ga 0. 7} As (1x10 1 9 cm -3, 10
nm) and undoped _{Al 0. 6 Ga 0. 4} As (4
0 nm) is regrown. Then, Al was deposited the gate electrode, Al and _{n-Al 0. 3 Ga 0} . 7 As / i
-Al _{0. 6} Ga _0. Etching the ₄ As layers into the shape of a gate electrode. Lift off the AuGe to n ⁺ -Ga
It is formed on As and is alloyed to form a source electrode.
Finally, AuZn, which is the drain electrode, is formed on p ⁺ -GaAs by lift-off, and the fabrication of the tunnel transistor is completed. The fabricated device showed negative resistance characteristics depending on the gate voltage under forward bias. The obtained peak current value is about 0.7 μA / when the gate voltage is OV.
was μm.

In the embodiment shown in FIG. 1, the substrate is mesa-etched so that the drain is higher than the source and the first to fourth portions are provided between them.
The semiconductor layers are sequentially stacked. However, the source and drain are on the same plane on the substrate as in a normal transistor, and the first to fourth semiconductors are formed adjacent to each other between the source and the drain. It is obvious that the planar structure described above may be used.

Although the third semiconductor layer is a layer in the embodiment of FIG. 1, it is sufficient if it is in contact with at least the fifth semiconductor, and this structure is preferable.

Further, in the embodiment of FIG. 1, n ⁺ -GaAs 4 is thinned to 5 nm. Sheet density of carriers in this area (carrier density per unit area, 2 × in the example of FIG. 1)
10 ^{1 9} cm ^{- 3} × 5nm at ^{1 × 10 1 3 cm - 2} ) If the same thinner is the characteristics desired.

In the above embodiment, only the n-type conductivity type and the p-type conductivity type of the fourth semiconductor are shown for the first semiconductor, the third semiconductor and the fifth semiconductor. However, these conductivity types are reversed. However, the same operation can be obtained. Further, instead of the fifth semiconductor, an insulating layer having a bandgap larger than those of the second and third semiconductors may be used. Further, as a material to be used, other than GaAs / AlGaAs system, SiGe
/ Si, Ge / GaAs, InGaAs / InAlA
It is obvious that the present invention can be applied to other semiconductors such as s and GaSb / AlGaSb.

[0015]

The tunnel current density is increased by the structure of the tunnel transistor of the present invention.

For example, compared with the structure of FIG. 1 without the third semiconductor layer 4, the current density is increased about 20 times.

[Brief description of drawings]

FIG. 1 is a schematic view showing an embodiment of the present invention.

FIG. 2 is a structural diagram of a conventional tunnel transistor.

[Explanation of symbols]

 1 substrate 2 1st semiconductor 3 2nd semiconductor 4 3rd semiconductor 5 4th semiconductor 6 5th semiconductor 7 gate electrode 8 source electrode 9 drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/812 29/872 8826-4M H01L 29/48 H

Claims (1)

[Claims] 1. A degenerate first semiconductor having one conductivity type, a non-degenerate second semiconductor, a third semiconductor having the same conductivity type as the first semiconductor, and an opposite of the first semiconductor. A fourth semiconductor having a conductivity type and a degenerate fourth semiconductor adjacent to each other, and at least on the surfaces of the second and third semiconductors made of a material having a wider band gap than the second and third semiconductors; A fifth layer containing ionized impurities in a part or the whole thereof, and a Schottky electrode on the fifth layer for forming ohmic junctions on the first semiconductor and the fourth semiconductor respectively. A tunnel transistor having.