JPH0767070B2 - Select circuit - Google Patents

Description

The present invention relates to a select circuit, and more particularly to a select circuit for digital signals.

[Conventional technology]

In general, a digital signal selection circuit selects one of a plurality of different input signals by a selection signal and outputs the selected signal.

However, when a plurality of different input signals change at the same time, spike noise may occur due to a slight shift in input timing.

The output of the select circuit is often used as the CLOCK signal of the flip-flop and the GATE signal of the latch, and a clear signal without spike noise is required.

Details of the conventional select circuit will be described below with reference to the drawings.

FIG. 3 shows an example of a conventional select circuit, and FIG. 4 shows a timing chart for explaining the operation thereof.

FIG. 3 shows a selector composed of one AND2 inverter and one OR1 inverter. When the selection signal S changes to 0 or 1, either one of the different input signals A and B is selected to Or 1 is output.

FIG. 4 is a timing chart of spike noise generated in the conventional select circuit.

In order to prevent this spike noise, there is a circuit that uses the output in a disabled state when the input changes, but each time the input signal changes, another control signal must be used for control.

[Problems to be solved by the invention]

In the conventional select circuit described above, when the input signals A and B and the select signal S change simultaneously as shown in the timing chart of FIG. 4, the output C, which is not originally expected to change due to the change time difference, is output. Spike noise occurs,
The circuit subsequent to the select circuit may malfunction.

An object of the present invention is to provide a select circuit capable of preventing spike noise even when a plurality of input signals and selection signals change simultaneously.

[Means for solving problems]

The select circuit of the present invention includes (1) a multiplexer for inputting a plurality of input signals and a selection signal, and (2) an inverting delay circuit for delaying and inverting the plurality of input signals and selection signals of the multiplexer, and outputting the delayed and inverted signals. (3) A plurality of EXORs each having as input signals a plurality of output signals of the inverting delay circuit corresponding to a plurality of input signals of the multiplexer and a selection signal, respectively. (4) Outputs of the respective EXORs It is composed of an AND having a signal as a plurality of input signals, and (5) a latch having an output of the AND as a gate input and an output signal of the multiplexer as a data input.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 and 2 are a block diagram of a select circuit according to an embodiment of the present invention and a timing chart for explaining the operation thereof.

FIG. 1 shows a data input of a latch 2 which puts the output of the multiplexer 1 having 2 inputs and 1 output into a through state or a holding state, and delays the signals A and B and the selection signal S which are the input data of the multiplexer 1 by an inversion delay. Circuit 3,4,5, EXOR6,7,
Input to GATE input of latch 2 through 8 and AND9.

The operation of this select circuit will be described below with reference to the timing chart of FIG.

The digital signal select circuit selects and outputs one of the different input signals.

However, when a plurality of different input signals and selection signals change at the same time, spike noise may occur due to a slight shift in input timing.

On the other hand, in the select circuit of the present invention, the outputs of EXOR6, 7, and 8 are all 1 in the state before the input change, so the latch 2 is in the through state, but the output of EXOR6 becomes 0 when the signal A changes. The output of AND9 also becomes 0, and the inverting delay circuit 3
The latch remains in the hold state until the output of 0 becomes 0. That is, the select circuit is in the output holding state for the delay time of the delay circuit.

Then, if the output holding state is released after the change of the signal B is completed, the latch becomes the through state and a clear value after the change is output, and spike noise does not occur.

Also, regarding the time of the output holding state, the inverting delay circuits 3, 4,
It can be adjusted by 5, and can be adjusted according to the size of the input timing deviation.

〔The invention's effect〕

As described above, the present invention has an effect of preventing output spike noise without using another control signal even when a plurality of different input data and selection signals change simultaneously.

[Brief description of drawings]

1 is a block configuration diagram of a select circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of internal and output of the select circuit of FIG. 1, FIG. 3 is a conventional select circuit, and FIG. The figure is an output timing chart of the select circuit of FIG. 1 …… 2 input 1 output multiplexer, 2 …… latch,
3,4,5 …… Inversion delay circuit, 6,7,8 …… EXOR, 9 …… AND.

Claims (1)

[Claims] 1. A multiplexer for inputting a plurality of input signals and a selection signal, and an inverting delay circuit for delaying and inverting the plurality of input signals and a selection signal of the multiplexer, respectively. (3) a plurality of EXORs each having an input signal of a plurality of output signals of the inverting delay circuit corresponding to a plurality of input signals of the multiplexer and a plurality of output signals of the inverting delay circuit, respectively (4) output signals of the respective EXORs And a latch having (5) the output of the AND as the gate input and the output signal of the multiplexer as the data input.