JPH0767100B2 - Signal transfer circuit - Google Patents

Description

The present invention relates to a signal transfer circuit for transferring signals between a line setting section and an interface section.

[Conventional technology]

In the conventional signal transfer circuit, data signals are transferred between the line setting unit and the interface unit at the same speed as the operating speed of the line setting unit.

[Problems to be Solved by the Invention]

The above-mentioned conventional signal transfer circuit transfers the data signal to the interface section at the same speed as the operation speed of the line setting section. Therefore, when the operation speed of the line setting section is high, the signal transfer rate is also high. However, in order to operate the signal transfer speed between the line setting unit and the interface unit at a high speed, the device of the transfer buffer is limited, the current consumption becomes large, and a large margin cannot be obtained. is there.

[Means for Solving the Problems]

A signal transfer circuit according to the present invention includes a multiplexing unit that multiplexes a plurality of input data signals received from an input-side interface unit via an input buffer unit and outputs a multiplexed signal, and a line setting for the input multiplexed signal. A line setting unit for outputting the multiplexed signal from the line setting unit and separating the multiplexed signal from the line setting unit as a plurality of output data signals via the output buffer unit to the interface unit on the output side. And a signal transfer speed between the interface unit and the interface unit is different from the operation speed of the line setting unit.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, a multiplexing unit 12 that multiplexes a plurality of input data signals 1 to n received from an interface unit on the input side via an input buffer unit 11 and outputs a multiplexed signal, and a multiplexing unit 12 A line setting section 13 for setting and outputting the converted signal from the line and a multiplexed signal from the line setting section 13 are separated and transmitted to the interface section on the output side as a plurality of output data signals 1 to n via the output buffer section 15. The separation unit 14, the line setting unit 13, and the interface unit are configured to perform signal transfer at a speed different from the operation speed of the line setting unit 13.

Next, the operation will be described. Through the input buffer unit 11 that receives the data signal from the interface unit, the multiplexing unit
The line setting unit 12 multiplexes a plurality of data signals into one data so as to have the same operation speed as the line setting unit 13, and the demultiplexing unit 14 multiplexes the data processed by the line setting unit 13. The data signal is separated and sent to the interface unit via the output buffer unit 5.

With this configuration, in the signal transfer between the interface unit and the line setting unit, the buffer unit that receives the data signal
11, a multiplexing unit 12 for multiplexing a plurality of data into one line, a line setting unit 13 for performing a line setting, a separating unit 14 for separating one data into a plurality of data, and an output buffer unit for sending a signal to an interface unit. 15 is provided, and the signal transfer speed between the line setting unit 13 and the interface unit can be performed at a speed different from the operating speed of the line setting unit 13.

〔The invention's effect〕

INDUSTRIAL APPLICABILITY As described above, according to the present invention, a buffer unit for signal transfer, a multiplexing unit for multiplexing a plurality of data into one line, a line setting unit for performing line setting, and a separation unit for separating one data signal into a plurality of data. Since it has a section, the transfer rate of signals between the line setting section and the interface section can be performed at a speed different from the operating speed of the line setting section, so there is no limit to the buffer device for transmitting and receiving data signals, You don't have to use a different device. Therefore, the power consumption is not large, and it is possible to provide an operation and a margin for transmitting and receiving a signal.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. 11,15 …… Input / output buffer section, 12 …… Multiplexing section, 13
...... Line setting section, 14 …… Separation section.

Claims (1)

[Claims] 1. A multiplexing unit for multiplexing a plurality of input data signals received from an input side interface unit via an input buffer unit and outputting as a multiplexed signal, and a line setting of the input multiplexed signal for output. A line setting unit for separating the multiplexed signal from the line setting unit and transmitting it to the interface unit on the output side as a plurality of output data signals via the output buffer unit. A signal transfer circuit, wherein a signal transfer speed between interface units is set to a speed different from an operation speed of the line setting unit.