JPH0769360B2 - Frequency detection circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a detection circuit for detecting a signal having a predetermined frequency or higher.

[Conventional technology]

Conventionally, this type of frequency detection circuit is an FV composed of a one-shot multivibrator circuit and an integrating circuit.
The output of the conversion circuit is connected to the inverting input terminal of a comparator whose non-inverting input terminal is connected to a reference constant voltage source, and the frequency is detected by the output of the comparator.

FIG. 3 shows a conventional configuration. A waveform shaping circuit 31, an FV conversion circuit 34 including a one-shot multivibrator circuit 32 and an integration circuit 33, and an FV conversion circuit 34.
Output and a constant voltage source (V _ref0 ) as an input and a comparator 35 having a hysteresis characteristic.

In operation, when the number of pulses (PW ₀ ) of the frequency (f ₀ ) at the input terminal 30 is applied, it passes through the circuit 31, and the circuit 32 causes the PW _{0 to} be a pulse wave with a constant pulse width (see FIG. 4). PW ₁ )
Is converted to. This pulse wave PW ₁ is converted into a DC voltage (V _COUT ) by the circuit 33. At this time, the relation between the amplitude of PW ₁ (V _CC ), the high level (TON), the low level (TOFF) in _one cycle of PW ₁ and V _COUT is And changes from frequency H as shown in FIG.

Using this characteristic, a voltage (V _ref0 ) corresponding to the detection frequency (TfH ₁ ) is applied to the non-inverting input terminal of the comparator 35 by a constant voltage source.
The relationship between the V _COUT applied to the inverting input terminal had become as to detect the frequency as of FIG. 5 at the output 36 of the comparator 35 when a _{V COUT ≧ V ref0 ...... (2} ) was added.

[Problems to be solved by the invention]

In the conventional frequency detection circuit described above, since the circuit 33 is composed of the resistor (RA) and the capacitor (CA) whose one end is grounded, there is a delay in V _COUT by the time constant due to the charging and discharging of CA. As a result, there is a drawback in that the generation of the output of the comparator 35, which indicates that the frequency of the input signal has reached TfH ₁ , is delayed.

Here, a realistic delay of the frequency detection time (in the integrated circuit) will be calculated.

As shown in FIG. 5, when a certain frequency (f ₁ ) is applied to the input (IN) terminal, the voltage converted to a DC voltage by the FV conversion circuit 34 and applied to the input terminal of the comparator 35 is V ₁
And When f ₁ suddenly changes to a certain frequency (f ₂ ) and the voltage applied to the input terminal of the comparator is V ₂ which is converted into a DC voltage by the F-V conversion circuit 34, the input frequency changes rapidly. The response time T when Because It is represented by.

Now, try to find the response time T by substituting the real number into equation (3).

Considering the case where resistance RA = 1kΩ, capacitor CA = 16μF DC voltage V ₁ = 0.5V, DC voltage V ₂ = 2.0V Therefore, the conventional frequency detecting circuit using the integrating circuit 33 in the FV converting circuit 34 causes a delay of the response of T = 22.2 mS obtained by the above equation with respect to the rapid change of the input frequency.

[Means for solving problems]

A circuit according to the present invention comprises a capacitor and a second charge of the capacitor during a first logic level of the input pulse signal.
And a charging / discharging circuit that discharges during the period of the logic level, and a charging / discharging voltage of the capacitor is generated when the charging / discharging voltage of the capacitor having the first and second thresholds is equal to or higher than the first threshold. A comparator for stopping generation of a reset pulse when the voltage becomes equal to or lower than the second threshold value; and means for generating a set pulse in synchronization with a change of the input pulse signal from the first logic level to the second logic level. A reset-priority type latch circuit for receiving the reset pulse at the reset terminal and the set pulse at the set terminal, the charge / discharge time constant of the charge / discharge circuit and the first and second threshold values being the input pulse. When the frequency of the signal is lower than the frequency to be detected, a reset pulse having a pulse width including the set pulse is generated and the When higher frequencies are characterized by being set so that the reset pulse is not generated.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, which is ICOM1 to ICO.
M4 is a constant current source, V _ref1 and V _ref2 are constant voltage sources, Q1 and
Q2 is NPN transistor, Cp and Ch are capacitors, 200 and 300 are comparators with hysteresis characteristics, INV
1 to INV3 are inverter circuits, and NOR1 to NOR4 are NOR circuits, which are connected as illustrated. SR is an SR latch circuit, and q is supplied with an input pulse signal at an input terminal f. m, n and p are the outputs of the NOR circuit NOR4, the comparator 300 and the SR latch circuit SR, respectively.

When the input pulse signal to the input terminal q is low level, the transistor Q2 is turned on and the capacitor Ch is the constant current source ICOM.
When the input pulse signal changes to the high level, the transistor Q2 is turned off and the capacitor Ch is charged by the constant current source ICOM3. The voltage VCH of the capacitor Ch is input to the comparator 300. Since the comparator 300 has the hysteresis characteristic as described above, the output p of the comparator 300 becomes high level when the voltage VCH reaches the higher threshold value, and is supplied to the SR latch circuit SR as a reset pulse. When the input pulse signal is inverted to low level, the capacitor Ch is discharged again, and when the voltage VCH reaches the lower threshold of the comparator 300, the output p of the comparator 300 is inverted to low level. The above-mentioned high and low threshold _values of the comparator 300 are determined based on the reference voltage V _ref2 .

The above operation is similarly performed for the capacitor Cp.
That is, the capacitor Cp and the constant current source ICOM1 are charged by the high level of the input pulse signal, and when the voltage reaches the higher threshold of the comparator 200, its output becomes the high level. When the input pulse signal goes low, the capacitor Cp is discharged and its voltage is
When the lower threshold of 200 is reached, the output goes low. The output of the comparator 200 is the NOR circuit NOR1.
Input to the NOR circuit NOR2 via the inverter circuit INV3, respectively.
Only when the output of 200 is at high level, the output of NOR circuit NOR4 is at high level and is supplied to the SR latch circuit SR as a set pulse. The SR latch circuit SR is a reset priority type. That is, when both the set terminal S and the reset terminal R are at the high level, the reset is prioritized and the output is at the low level.

In such a configuration, each circuit constant is set so that when the frequency of the input pulse signal becomes higher than the frequency at the detection point, the state is output as the high level output of the SR latch circuit SR. This means that when the frequency of the input pulse signal is higher than the frequency to be detected, its high level period (pulse width) becomes small, and when it is lower than the frequency to be detected, its high level period (pulse width) becomes large. I am using it. That is, when the high level period of the input pulse signal becomes longer than the high level period TfH2 corresponding to the frequency serving as the detection point, the output of the SR latch circuit SR becomes the high level.

More specifically, as shown in FIG. 2, the timing waveform diagram when the high level period t1 of the input pulse signal is in three states of TfH2 <t1, TfH2 = t1 and TfH2> t1 is shown in FIG.
Considering the case of <t1, since the high level period of the input pulse signal is long, the voltage VCH of the capacitor Ch is
The high threshold value of 00 is sufficiently exceeded, and a wide reset pulse (p) is obtained as shown in the figure. The set pulse (m) is output from the NOR circuit NOR4 in synchronization with the inversion of the input pulse signal to the low level, but since it disappears during the output period of the reset pulse, the SR reset circuit SR remains in the reset state.

When the high level period t1 of the input pulse signal becomes TfH2 = t1, the charging voltage VCH of the capacitor Ch charged during the high level period of the input pulse signal is adjusted so that the charging voltage VCH of the capacitor Ch matches the high threshold of the comparator 300 and the current source ICOM3. Since the constant is set, a reset pulse (p) having a relatively narrow width can be obtained as shown in the figure. At this time, a reset pulse (m) is also generated, but since the capacitor Cp, the current source ICOM1 and the reference voltage V _ref1 are set so that this pulse is completely included in the reset pulse (p), SR
The latch circuit SR remains reset.

When the high level period t1 of the input pulse signal becomes shorter than TfH2, the output of the comparator 300 remains low level, while the constants are set so that the output of the comparator 200 can obtain high level. The latch circuit SR is set and its output (m) is inverted to high level. The detection delay at this time is the delay of the NOR circuit inverter circuit and is usually 10 nsec.

〔The invention's effect〕

By using the circuit described above, the present invention is a conventional F-
The delay in frequency detection due to charging / discharging of the capacitor in the V conversion circuit was several tens of mS, whereas the delay was only in the inverter circuit and NOR circuit in the circuit (normally several tens nS).
This has the effect of significantly reducing the delay in response time in frequency detection.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a timing chart in the figure, FIG. 3 is a conventional example, and FIGS. 4 and 5 are a timing chart, an FV graph and a timing chart in FIG.

Claims (1)

[Claims] 1. A capacitor, a charging / discharging circuit for charging the capacitor during a period of a first logic level of an input pulse signal, and discharging the capacitor during a period of a second logic level, and first and second threshold values. A comparator for generating a reset pulse when the charge / discharge voltage of the capacitor is equal to or higher than the first threshold value, and stopping the generation of the reset pulse when the charge / discharge voltage of the capacitor is equal to or lower than the second threshold value; Means for generating a set pulse in synchronization with the change from the first logic level to the second logic level, and a reset-priority type latch circuit for receiving the reset pulse at the reset terminal and the set pulse at the set terminal, respectively. And a charging / discharging time constant of the charging / discharging circuit and the first and second thresholds are set to a frequency to be detected by the frequency of the input pulse signal. Frequency detection circuit, characterized in that when higher than the frequency to be the detection reset pulse having a pulse width including the set pulse is generated is set such that the reset pulse is not generated when the number below.