JPH0769393B2 - Real Chip Simulator - Google Patents

Description

The present invention relates to a simulator for performing logic simulation by combining an LSI and a software simulator, and in particular, a MOS LSI including a dynamic circuit can be used with simple timing adjustment. Real chip simulator.

[Conventional technology]

Conventionally, this kind of real-chip simulator has a LSI that operates at high speed but can hold the state for only a few hundred microseconds.
Since it was composed in combination with a software simulator, which takes several seconds to simulate changing one input signal, the output of the software simulator for timing these operations was reedited into the input signal pattern for LSI. Later, it was input to LSI.

[Problems to be solved by the invention]

In the above-mentioned conventional real chip simulator, when the circuit scale of the LSI is small, the operating time of the LSI is short and is almost limited by the operating time of the software simulator.However, as the circuit scale of the LSI rapidly increases, LSI
It takes several tens of minutes to several hours to change the initial state of resetting the internal circuit from the initial state to the circuit state to be simulated, and an example in which additional simulation of several patterns takes one day or more occurs. Furthermore, since the LSI is usually composed of a dynamic circuit that uses MOS FETs, it is not possible to maintain the same circuit state for a long time. Therefore, it is necessary to set the circuit state again many times for a simulation that takes a long time. There is a drawback that.

[Means for solving problems]

The real chip simulator of the present invention includes a low temperature tank for cooling a board that implements a logic circuit to be studied by mounting a plurality of LSIs, a variable voltage source capable of adjusting the operating voltage of the LSIs,
A logic simulator that controls an LSI based on a program for examining a logic circuit, a board on which the LSI is mounted, an interface that adjusts the output signal level of the logic simulator and supplies it to the LSI, and input and output signals of the LSI and the logic simulator And a variable clock signal generator for synchronizing the above.

The real chip simulator of the present invention extends the data retention time in the LSI by lowering the operating temperature of the LSI,
By making the LSI operate at a low speed with a clock cycle that matches the logic simulator operating at low speed, it becomes unnecessary to create a timing adjustment program for the LSI and the logic simulator.
No need to edit input / output signal patterns to match the input / output signal timing of LSI and logic simulator.
Logic simulator and LS as real chip simulator
The operation time can be shortened to the one having the longer operation time, not the sum of the operation times of I.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the real chip simulator of the present invention. A printed circuit board 1 in which logic circuits to be considered by mounting LSIs a, b, c, d are realized as a combination of these LSIs is installed in a low temperature tank 2. Next, I / O interface 5 equipped with programmable pulse generator 3 and variable voltage source 4
Printed circuit board 1 on which LSI a, b, c, d are mounted with cable 6
Connect to. The I / O interface 5 is connected by a cable 8 to an engineering workstation (EWS) 7 that operates a logic simulation program. The LSIs a to d mounted on the printed circuit board 1 use a dynamic logic circuit composed of MOS FETs, and a heat radiation fin or the like for adjusting the thermal resistance of the case in which the LSIs are assembled in order to make the chip surface temperature almost the same. I have it.

Figure 2 shows the correlation between the data holding time of MOS LSI and the operating temperature. It should be noted here that the LSI operating temperature is the surface temperature of the silicon chip, not the ambient temperature of the printed circuit board.

Next, the operation of the device will be described.

By cooling the LSIs a, b, c, d in the low temperature tank 2 capable of cooling the ambient temperature of the printed circuit board 1 to about −40 ° C., as shown in FIG. The data retention time can be extended 1000 times or more compared to the operation at room temperature.

Therefore, the clock cycle supplied to the synchronous circuit of the printed circuit board 1 on which the LSIs a, b, c, and d are mounted is synchronized with the logic simulator operating on the EWS7 (the number shown in the LSI characteristics table at room temperature). It can be set to 100 times the clock period). Since the MOS transistors that make up a MOS LSI have a higher threshold value as the operating temperature decreases, it is necessary to set the power supply voltage higher than room temperature in an LSI whose operating voltage is limited by the transmission gate. Therefore, there is an I / O interface 5 with a level adjustment circuit between the output circuit of the EWS7 that normally operates with a 5V power supply and the LSIs a, b, c, and d in the low temperature tank 2 that operates with a voltage other than 5V to adjust the signal level. Deploy. The LSI a, b, c, d in the low temperature tank 2 supplies a power source or a reference voltage from the variable voltage source 4 via the variable voltage source 4 via the I / O interface 5. By supplying the input / output signal of the simulation simulator and the reference clock signal of the programmable pulse generator 3 from the EWS7 operating the logic simulator through the cable 8.
The LSI can operate in synchronism with the timing of the logic simulator running on the EWS7, and the timing is matched with the logic simulator on the EWS7, which is about two digits slower than the LSI that can only operate at high speed at room temperature. Since it is not necessary to create the program and the editing of the LSI simulation pattern on the printed circuit board 1 is unnecessary, the speed can be increased as a real chip simulator.

〔The invention's effect〕

As described above, the real chip simulator of the present invention lengthens the data retention time of the circuit that operates dynamically by lowering the operating temperature of the LSI mounted on the printed board, and changes the operating voltage due to the threshold change of the MOS transistor. By providing a variable voltage source that adjusts the signal and an I / O interface that adjusts the signal level between the EWS and the LSI board, the timing of the LSI board of the real chip simulator and the logic simulator implemented by the software on the EWS can be controlled at low speed. Can be adapted to a working simulator,
There is no need to create a program for timing adjustment,
As a result of eliminating the need to edit the board simulation pattern, there is an effect that the real chip simulator can be speeded up.

[Brief description of drawings]

FIG. 1 is a system configuration diagram according to an embodiment of the present invention, and FIG.
The figure is a characteristic diagram of data holding time / operating temperature of an LSI including a dynamic circuit. LSI a, b, c, d ... LSI, 1 ... Printed circuit board, 2 ... Low temperature tank, 3 ... Programmable pulse generator, 4
...... Variable voltage source, 5 ... I / O interface system, 6,8 ... Cable, 7 ... EWS.

Claims (1)

[Claims] 1. An LSI and a logic simulator on a computer system, the LSI being controlled by the logic simulator.
And a means for cooling the LSI in a real chip simulator for activating a
Means for adjusting the power supply voltage of the logic simulator, means for matching the input / output signal level of the logic simulator with the input / output signal level of the LSI and supplying the LSI with the clock signal supplied from the logic simulator. A real-chip simulator characterized by having means for synthesizing a required clock signal group.