JPH0769804B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing device which realizes high processing capability by an advanced pipeline processing mechanism.

[Conventional technology]

In the conventional data processing device described in detail in Japanese Patent Application No. 61-236456, one instruction is divided into a plurality of pipeline processing units (hereinafter referred to as step codes) in the decoding stage, In the subsequent stages, the processing is performed on the one-step code.

FIG. 10 shows a data flow in a data processing device having a conventional pipeline processing mechanism. In the figure, 10
0 is the instruction fetch stage, 101 is the decode stage, 10
2 is an address calculation stage, 103 is an operand fetch stage, and 104 is an execution stage. The decode stage performs an operation of dividing one instruction into one or more step codes.

FIG. 11 is a diagram showing an instruction format in a conventional data processing device. In the figure, (a) is a format in which a source operand follows the opcode and a destination operand follows (first format).
(B) is the case where the destination operand follows the operation code and the immediate value follows (second format). Here, 105a and 106a are operation code designation fields, 105b is a source operand designation field, and 105c and 106b are destination operand designation fields. Also, 106c indicates immediate data.

FIG. 12 is a diagram showing a flow of a pipeline in the case of processing an instruction of the first format in a conventional data processing device. In the figure, 1S is a step code containing the information of the source operand, and 1D is a step code containing the information of the destination operand. In the decode stage 101, one instruction is divided into an S step code and a D step code.

Next, taking an addition instruction as an example, the source operand is at the address obtained from the sum of register 1 indicating the base address and displacement 1, and the destination operand is the address obtained from the sum of register 2 indicating the base address and displacement 2. The flow of the pipeline processing in this conventional example is shown. First, this instruction is fetched from the memory in the instruction fetch stage 100. In decode stage 101,
When this instruction is fetched from the instruction fetch stage 100, the step code 1S is created from the operation code 105a and the source operand specification field 105b, and the step code 1D is created from the operation code 105a and the destination operand specification field 105c. This step code 1S is the address calculation stage 102.
Upon entry, the value of register 1 and displacement 1 are added, the address for fetching the operand is obtained, and the address is sent to the operand fetch stage 103.

In the operand fetch stage 103, the value of the source operand is fetched from the memory. In the execution stage 104, the value of the source operand fetched from the memory is saved in the working register. The D step code flows through each stage following the S step code. When the D step code enters the address calculation stage 102, the value of the register 2 and the displacement 2 are added to obtain the address for fetching the operand, and the address is sent to the operand fetch stage 103. Operand fetch stage 103
In, the value of the destination operand is fetched from memory.

When the D step code enters the execution stage 104, the value of the source operand previously saved in the working register and the value of the destination operand are added, and the result is stored in the location designated by the destination. One instruction is processed in 2 basic clocks in each stage, and all instructions in the first format are processed in 5 basic clocks. However, when writing to the memory as in the above example, 1
An extra base clock is required and is processed with 6 base clocks.

Also, in the conventional data processing device, whether the destination operand instructed in the general-purpose addressing mode is in the register or in the memory is passed as a parameter to the microprogram to write the operand to the register and the operand to the memory. , The same micro-instruction is used for processing to reduce the micro ROM size.

[Problems to be Solved by the Invention]

However, in the conventional data processing device, FIG.
When processing a two-operand instruction in which the source operand is limited to the immediate data specified in the instruction code as in the second format, the destination operand is specified first, and the immediate data that is the source operand follows. In the data processing device, pipeline processing is performed in the order of the processing unit corresponding to the destination operand and the processing unit for immediate data. In this case, since the processing unit for processing the destination operand and the processing unit for writing the micro instruction do not correspond to each other, the micro program provides information about whether the destination operand is in the register or in the memory. There is a problem that it cannot be passed in association with the processing unit for writing.

Further, in the conventional data processing device, when the instruction whose destination operand is limited to the register is processed, the destination operand is not designated in the general-purpose addressing mode, so that the parameter is not set.

The present invention has been made in order to solve the problems of the conventional ones described above, and a processing unit for writing the information whether the destination operand is in the register or in the memory at the execution stage. It is an object of the present invention to provide a data processing device capable of further reducing the area occupied by a micro ROM by making it compatible with the above.

[Means for Solving the Problems]

In the data processing device according to the present invention, in order to solve the above-mentioned problems of the conventional device, the processing unit for sending the processing information regarding the destination operand is different from the processing unit for writing to the destination operand in the execution stage. Also in this case, whether the write operand is in the register or in the memory is instructed in correspondence with the processing unit for writing in the execution stage.

Further, when the instruction whose destination operand is limited to the register is processed, it is designed to indicate that the operand is on the register.

[Action]

The data processing device according to the present invention indicates whether the destination operand is on the memory or on the register in correspondence with the processing unit in which writing is performed in the execution stage, and the same microinstruction is set regardless of the position of the operand. Since the write processing of the operand is carried out, the microinstruction can be shared and the area of the micro ROM can be further reduced.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

(1) Functional Block Configuration FIG. 1 shows a block diagram of a data processing apparatus according to an embodiment of the present invention. Functionally, the inside of the data processing device of this embodiment is roughly divided into an instruction fetch unit 51, an instruction decoding unit 52, a PC calculation unit 53, an operand address calculation unit 54, a micro ROM unit 55, a data calculation unit 56, and an external bus. Divided into interface section 57. In FIG. 1, an address output circuit 58 for outputting an address to the outside of the CPU and a data input / output circuit 59 for inputting / outputting data to / from the outside of the CPU are shown separately from the other functional block portions.

(1.1) Instruction fetch unit The instruction fetch unit 51 has a branch buffer, an instruction queue and its control unit, determines the address of the instruction to be fetched next, and fetches the instruction from the branch buffer or a memory outside the CPU. It also registers instructions in the branch buffer.

Since the branch buffer is small, it operates as a selective cache. Details of the operation of the branch buffer are described in detail in Japanese Patent Application No. 61-202041.

The address of the instruction to be fetched next is calculated by a dedicated counter as the address of the instruction to be input to the instruction queue. When a branch or jump occurs, the address of the new instruction is transferred from the PC calculation unit 53 or the data calculation unit 56.

When fetching an instruction from the memory outside the CPU, the address of the instruction to be fetched is output from the address output circuit 58 to the outside of the CPU through the external bus interface unit 57, and the instruction code is fetched from the data input / output circuit 59.

Of the buffered instruction codes, the instruction decode section
The instruction decoding unit 52 determines the instruction code to be decoded next at 52.
Output to.

(1.2) Instruction decode unit The instruction decode unit 52 basically decodes the instruction code in 16-bit (halfword) units, and indicates whether the operand specified by the general-purpose addressing mode is on a register or in memory. To do. This block includes an FHW decoder that decodes the operation code included in the first halfword, an NFHW decoder that decodes the operation code included in the second and third halfwords, and an addressing mode decoder that decodes the addressing mode.

A second decoder that further decodes the output of the FHW decoder and NFHW decoder to calculate the entry address of the micro ROM, a branch prediction mechanism that predicts the branch of conditional branch instructions, and a pipeline conflict when calculating the operand address An address calculation conflict check mechanism is also included.

The instruction code input from the instruction fetch unit is decoded into 0 to 6 bytes every 2 clocks. Among the decoding results, the information related to the operation in the data operation block 56 is output to the micro ROM unit 55, the information related to the operand address calculation is output to the operand address calculation unit 54, and the information related to the PC calculation is output to the PC calculation unit 53. It

(1.3) Micro ROM unit The micro ROM unit 55 mainly includes a micro ROM storing a micro program for controlling the data operation unit 56, a micro sequencer, a micro instruction decoder, and a part of the field of the micro instruction. Is a specific bit pattern, the instruction means included in the instruction decoding unit 52 writes the execution result to the register when the instruction means indicates that the operand is on the register, and the instruction means stores the operand on the memory. When the instruction is given, an operand writing means for writing the execution result in the memory is included. Micro instructions are read from the micro ROM once every two clocks. In addition to the sequence processing shown by the micro program, the micro sequencer
Accepts exception, interrupt, and trap (all three are collectively called EIT) processing by hardware. Also micro
The ROM section also manages the store buffer. Flag information based on an interrupt that does not depend on an instruction code and a result of operation execution, and an output of the instruction decoding unit such as an output of the second decoder are input to the micro ROM unit. The output of the microdecoder is mainly output to the data operation unit 56, but some information such as other preceding processing by the execution of the jump instruction and stop information is also output to other blocks.

(1.4) Operand Address Calculation Unit The operand address calculation unit 54 is hard-wired controlled by the information related to the operand address calculation output from the address decoder of the instruction decoding unit 52.
In this block, most of the address calculation of operands is performed. It is also checked whether the memory access address or operand address for memory indirect addressing falls within the I / O area mapped in the memory.

The address calculation result is sent to the external bus interface unit 57. The values of general-purpose registers and program counters required for address calculation are input from the data calculation unit.

When indirect memory addressing is performed, the address output circuit 58 to the CPU through the external bus interface 57
The memory address to be referenced is output to the outside, and the indirect address value input from the data input / output unit 59 is output to the instruction decoding unit.
Fetch through 52.

(1.5) PC calculation unit The PC calculation unit 53 is hard-wired controlled by the information related to the PC calculation output from the instruction decoding unit 52, and the PC of the instruction
Calculate the value. The data processing apparatus of this embodiment has a variable length instruction set, and the length of the instruction cannot be known unless the instruction is decoded. PC calculator 53 is instruction decoder 52
The PC value of the next instruction is created by adding the instruction length output from the to the PC value of the instruction being decoded. Further, when the instruction decoding unit 52 decodes a branch instruction and instructs branching at the decoding stage, the PC value of the branch destination instruction is calculated by adding the branch displacement instead of the instruction length to the PC value of the branch instruction. . The branching of a branch instruction at the instruction decoding stage is called a pre-branch in the data processor of this embodiment. Japanese Patent Application No. 61-204
It is described in detail in Japanese Patent No. 500 and Japanese Patent Application No. 61-200557.

The calculation result of the PC calculation unit 53 is output as the PC value of each instruction together with the instruction decode result, and is output to the instruction fetch unit as the address of the next instruction to be decoded at the pre-branch.

Further, it is also used as an address for branch prediction of an instruction decoded next by the instruction decoding unit 52. The branch prediction method is described in detail in Japanese Patent Application No. 62-8394.

(1.6) Data operation unit The data operation unit 56 is controlled by a micro program,
According to the output information of the micro ROM unit 55, the operations necessary for realizing the function of each instruction are executed by the register and the arithmetic unit. The address calculated by the operand address calculation unit 54 may be obtained through the external bus interface unit 57, or the operand fetched at that address may be obtained from the data input / output circuit 59.

The arithmetic unit includes ALU, barrel shifter, priority encoder, counter, shift register and so on. Three buses are connected between the register and the main arithmetic unit.
One microinstruction for instructing an operation between two registers is processed in two clock cycles.

When it is necessary to access the memory outside the CPU during data operation, the address is output from the address output circuit 58 to the outside of the CPU through the external bus interface 57 according to the instructions of the microprogram, and the target data is output through the data input / output circuit 59. To fetch.

When storing data in a memory outside the CPU, the address is output from the address output circuit 58 through the external bus interface unit 57, and at the same time, the data is output from the data input / output circuit 59 to the outside of the CPU. In order to perform the operand store efficiently, the data operation unit 56 has a 4-byte store buffer.

When the data operation unit 56 obtains a new instruction address by performing a jump instruction process or an exception process, the data operation unit 56 outputs it to the instruction fetch unit 51 and the PC calculation unit 53.

(1.7) External Bus Interface Unit The external bus interface unit 57 controls communication on the external bus of the data processing apparatus of this embodiment. All memory accesses are clock-synchronized and can be performed in a minimum of two clock cycles.

The access request to the memory is generated independently from the instruction fetch unit 51, the address calculation unit 54, and the data calculation unit 56. The external bus interface unit 57 arbitrates these memory address requests. Furthermore, for memory addresses that cross a 32 bit (word) alignment boundary that is the size of the data bus connecting the memory and the CPU, it is automatically detected that the word boundary is crossed within this block, and it is decomposed into two memory accesses. Access.

In addition, conflict prevention processing when the prefetched operand and the stored operand overlap and bypass processing from the store operand to the fetch operand are also performed in this block.

(2) Instruction format of the data processing apparatus of this embodiment The instruction of the data processing apparatus of this embodiment has a variable length in 16-bit units, and there is no instruction of odd byte length.

The data processing device of this embodiment has a specially devised instruction format system in order to make a high-frequency instruction into a short format. For example, for a two-operand instruction, there are two formats: a general format that basically has a structure of 4 bytes + an extension and can use all addressing modes, and a short format that can use only frequently used instructions and addressing modes. There is a format.

The meanings of the symbols appearing in the instruction format of the data processing apparatus of this embodiment are as follows.

-: Part containing opcode #: Part containing literal or immediate value Ea: Part specifying operand in 8-bit general addressing mode Sh: Part specifying operand in 6-bit short addressing mode Rn: Register The partial format that specifies the above operand by register number is the LSB side on the right side as shown in Fig. 3,
And the address is high. The instruction format cannot be discriminated unless the two bytes at address N and address N + 1 are seen.
This is because it is premised that the data is fetched and decoded in bit (2 bytes) units.

In any of the formats in the data processing apparatus of this embodiment, the extension part of Ea or Sh of each operand is always placed immediately after the halfword including the basic part of the Ea or Sh. This takes precedence over immediate data implicitly specified by the instruction and the extension of the instruction. Therefore, in the case of an instruction of 4 bytes or more, the operation code of the instruction may be divided by the extension part of Ea.

Also, as will be described later, the multi-stage indirect mode
Even if the extension part of Ea has an extension part, that part has priority over the next instruction opcode. For example, the first
Consider the case of a 6-byte instruction that includes Ea1 in the halfword, Ea2 in the second halfword, and up to the third halfword. Since the multistage indirect mode is used for Ea1, the extension part of the multistage indirect mode shall be attached in addition to the ordinary extension part. At this time, the actual instruction bit pattern is the first instruction
Halfword (including Ea1 base), Ea1 extension, Ea
Multistage indirect mode extension of 1, second halfword of instruction (E
(including the basic part of a2), the extension part of Ea1, and the third halfword of the instruction.

(2.1) Short two-operand instruction This is the short two-operand instruction format shown in FIGS. 4 (a) to 4 (d).

FIG. 4A shows the format of the memory-register arithmetic instruction. This format includes an L format in which the source operand side is a memory and an S format in which the destination operand side is a memory.

In the L format, Sh represents a source operand designation field, Rn represents a destination operand register designation field, and RR represents a Sh operand size designation. The size of the destination operand placed in the register is fixed at 32 bits. Sign extension is performed when the size of the register and that of the memory are different and the size of the source is small.

In the S format, Sh represents a destination operand designation field, Rn represents a source operand register designation field, and RR represents a Sh operand size designation. The size of the source operand placed on the register is fixed to 32 bits. When the size of the register and the size of the memory are different, and the size of the source is large, the overflow portion is truncated and the overflow check is performed.

FIG. 4B shows the format (R format) of the register-register arithmetic instruction. Rn is a designation field of the destination operand register, and Rm is a designation field of the source register. Operand size is
Only 32 bits.

FIG. 4 (c) shows the format (Q format) of the literal-memory operation instruction. MM is a destination operand size specification field, # is a literal source operand specification field, and Sh is a destination operand specification field.

FIG. 4D shows the format (I format) of the immediate-memory operation instruction. MM is an operand size specification field (common to source and destination),
Sh is a designated field of the destination operand. The size of the immediate value of the I format is 8, 16, 32 bits in common with the size of the operand on the destination side, and zero extension and sign extension are not performed.

(2.2) General-purpose 1-operand instruction FIG. 4 (e) shows the general-purpose format (G1 format) of the 1-operand instruction. MM is a field for specifying the operand size. Some G1 format instructions
There is an extension part other than the extension part of Ea. Also, some instructions do not use MM.

(2.3) General-purpose two-operand instruction FIGS. 4 (f) to 4 (h) are general-purpose formats of the two-operand instruction. Included in this format are instructions that have a maximum of two operands in the general addressing mode specified by 8 bits. The total number of operands themselves may be three or more.

FIG. 4 (f) shows the format (G format) of the instruction in which the first operand requires memory reading. Ea
M is the designated field of the destination operand, M
M is a destination operand size specification field, EaR is a source operand specification field, and RR is a source operand size specification field.

FIG. 4 (g) shows an instruction format (E format) in which the first operand is an 8-bit immediate value. EaM is the destination operand specification field, MM is the destination operand size specification field, and # is the source operand value.

Although the E format and the I format are functionally similar to each other, they are significantly different from each other in the point of view. The E format is a derivative of the 2-operand general type (G format), and the size of the source operand is 8
Bit fixed, destination operand size is
It is selected from 8/16/32 bits. In other words, the 8-bit source operand is zero-extended or sign-extended according to the size of the destination operand on the premise of the operation between different sizes. On the other hand, the I format is a shortened form of an immediate value pattern that is frequently used especially for transfer instructions and comparison instructions, and the source operand and the destination operand have the same size.

FIG. 4H shows a format (GA format) of an instruction whose first operand is only address calculation. EaW is the destination operand specification field, WW is the destination operand size specification field,
EaA is a designated field of the source operand. The execution address calculation result itself is used as the source operand.

FIG. 4 (i) shows the format of the short branch instruction. CCCC is a branch condition designation field, and disp: 8 is a displacement designation field with a jump destination. In the data processing device of this embodiment, when the displacement is designated by 8 bits,
The specified value in the bit pattern is doubled to obtain the displacement value.

(2.4) Addressing Mode The addressing mode designating method of the data processing device of this embodiment includes a short form designating with 6 bits including a register and a general form designating with 8 bits.

If an undefined addressing mode is specified, or if a combination of addressing modes that is obviously strange in terms of meaning is specified, a reserved instruction exception is generated and exception processing is started, as when an undefined instruction is executed. To do.

This corresponds to the case where the destination is the immediate mode, the case where the immediate mode is used in the addressing mode designation field which should accompany the address calculation, and the like.

The symbols used in the format diagrams are as follows.

Rn register specification mem [EA] Memory content of the address indicated by EA Sh Specification method in 6-bit short addressing mode Ea Specification method in 8-bit general addressing mode The part enclosed by the dotted line in the format diagram is The extension is shown.

(2.4.1) Basic Addressing Mode The data processing device of this embodiment supports various addressing modes. Among them, the basic addressing modes supported by the data processor of the present embodiment include register direct mode, register indirect mode, register relative indirect mode, immediate value mode, absolute mode, PC relative indirect mode, stack pop mode, and stack push mode. is there.

In the register direct mode, the contents of the register are directly used as the operand. The format is shown in Fig. 5 (a). Rn indicates the general register number.

In the register indirect mode, the contents of the memory whose address is the contents of the register are the operands. The format is shown in FIG. Rn indicates the general register number.

In the register relative indirect mode, the displacement value is 16
There are two types depending on whether it is bit or 32-bit. Each of them uses the contents of the memory whose address is a value obtained by adding a displacement value of 16 bits or 32 bits to the contents of the register as an operand. The format is shown in FIG. 5 (c). Rn indicates the general register number. disp: 16 and disp:
32 is the displacement value of 16 bits, 32 respectively
Indicates the displacement value of the bit. The displacement value is treated as signed.

In the immediate mode, the bit pattern specified in the instruction code is regarded as a binary number as it is and is used as an operand. The format is shown in FIG. imm-data indicates an immediate value. The size of imm-data is specified in the instruction as the operand size.

There are two types of absolute modes depending on whether the address value is indicated by 16 bits or 32 bits. The contents of the memory with the 16-bit or 32-bit bit pattern specified in the instruction code as an address are used as operands. The format is shown in FIG. abs: 16 and
abs: 32 indicates 16-bit and 32-bit address values, respectively. When the address is indicated by abs: 16, the specified address value is sign-extended to 32 bits.

There are two types of PC relative indirect mode depending on whether the displacement value is 16 bits or 32 bits. Each of the program counter contents has a 16-bit or 32-bit displacement value added as an address, and the memory contents as an address are used as operands. The format is shown in Fig. 5 (f).
Shown in. disp: 16 and disp: 32 represent a 16-bit displacement value and a 32-bit displacement value, respectively. The displacement value is treated as signed. The value of the program counter referred to in the PC relative indirect mode is the start address of the instruction including the operand. Even when the value of the program counter is referenced in the multi-stage indirect addressing mode, the address at the beginning of the instruction is used as the PC-relative reference value in the same manner.

In the stack pop mode, the content of the memory whose address is the content of the stack pointer SP is the operand. After the operand is accessed, SP is incremented by the operand size. For example, when handling 32-bit data, SP is updated by +4 after operand access. It is also possible to specify the stack pop mode for operands of sizes B and H, and SP is updated by +1 and +2 respectively.
The format is shown in FIG. If the stack pop mode has no meaning for the operand, a reserved instruction exception is generated. Specifically, the reserved instruction exception is the stack pop mode specification for the write operand and the read-modify-write operand.

In the stack push mode, the contents of the memory whose address is the contents of SP decremented by the operand size are the operands. In stack push mode, SP is decremented before operand access. For example, when handling 32-bit data, SP is updated by -4 before operand access. It is also possible to specify the stack push mode for operands of sizes B and H, and SP is updated by -1 and -2, respectively. The format is shown in FIG. If the stack push mode has no meaning for the operand, a reserved instruction exception is generated. Specifically, the reserved instruction exception is the stack push mode specification for the read operand and the read-modify-write operand.

(2.4.2) Multistage indirect addressing mode Basically, any complicated addressing can be decomposed into a combination of addition and indirect reference. Therefore, if complicated addition and indirect reference operations are given as addressing primitives and they can be arbitrarily combined, any complicated addressing mode can be realized. The multi-stage indirect addressing mode of the data processing apparatus of this embodiment is an addressing mode based on such a concept. Complex addressing modes are especially useful for data references between modules and AI language implementations.

When designating the multi-stage indirect addressing mode, in the basic addressing mode designation field, one of the three designation methods of register-based multi-stage indirect mode, PC-based multi-stage indirect mode, and absolute base multi-stage indirect mode.
Specify one.

The register-based multistage indirect mode is an addressing mode in which a register value is used as a base value for expanding multistage indirect addressing. The format is shown in Fig. 5 (i).
Shown in. Rn indicates the general register number.

In the PC-based multi-stage indirect mode, the value of the program counter is
This is an addressing mode that is used as a base value for expanding multistage indirect addressing. The format is shown in FIG. 5 (j).

The absolute base multi-stage indirect mode is an addressing mode in which zero is used as a base value for expanding multi-stage indirect addressing. The format is shown in FIG.

The multistage indirect mode specification field to be expanded has 16 bits as a unit, and this is repeated any number of times. Addition of displacement, scaling (× 1, × 2, × 4, × 8) of index register and addition, and indirect reference of memory are performed by the one-stage multi-stage indirect mode. The format of the multistage indirect mode is shown in FIG. The fields have the following meanings.

E = 0: Multi-stage indirect mode continued E = 1: Address calculation end tmp → address of operand I = 0: No memory indirect reference tmp + disp + Rx * Scale → tmp I = 1: Memory indirect reference mem [tmp + disp + Rx * Scale] → tmp M = 0: Use <Rx> as index M = 1: Special index <Rx> = 0 Do not add index value (Rx = 0) <Rx> = 1 Use program counter as index value (Rx = PC) <Rx> = 2 to reserved D = 0: The value of the 4-bit field d4 in the multi-stage indirect mode is multiplied by 4 to be a displacement value, which is added. d4 is treated as signed, and it is always multiplied by 4 regardless of the operand size.

D = 1: dispx (16 /
(32 bits) is used as the displacement value and this is added. The size of the extension is specified in the d4 field.

d4 = 0001 dispx is 16 bits d4 = 0010 dispx is 32 bits XX: Index scale (scale = 1/2/4/8) When the program counter is scaled by × 2, × 4, × 8 Is the intermediate value (tm
An undefined value is entered as p). The effective address obtained by this multistage indirect mode has an unpredictable value, but no exception occurs. Do not specify scaling for the program counter.

Variations of the instruction format in the multistage indirect mode are shown in FIGS. 5 (1) and 5 (m). Fig. 5 (1)
Indicates a variation of whether the multistage indirect mode continues or ends. FIG. 5 (m) shows variations in displacement size.

If the multi-stage indirect mode with an arbitrary number of stages can be used, it is not necessary to divide the case depending on the number of stages in the compiler, which has the advantage of reducing the load on the compiler. This is because the compiler must be able to generate correct code even if the frequency of multiple indirect references is extremely low. Therefore, an arbitrary number of stages is possible in the format.

(2.5) Exception processing The data processing device of this embodiment has a variety of exception processing functions to reduce the software load. In the data processor of the present embodiment, the exception processing is one in which instruction processing is re-executed (exception), one in which instruction processing is completed (trap), and interrupt.
The names are given separately for each type. Further, in the data processing apparatus of this embodiment, these three types of exception processing and system failure are collectively referred to as EIT.

(3) Pipeline information The pipeline processing of the data processing apparatus of this embodiment has a configuration as shown in FIG. That is, an instruction fetch stage (IF stage) 31 for prefetching instructions, a decode stage (D stage) 32 for decoding instructions,
Operand address calculation stage (A stage) 33 that performs operand address calculation, operand fetch stage (F stage) that performs micro ROM access (specifically called R stage 36) and operand prefetch (specifically called OF stage 37) 34 The five-stage configuration of the execution stage (E stage) 35 for executing instructions is the basis of pipeline processing. In the E stage 35, there is a one-stage store buffer, and since some high-performance instructions pipeline the instruction itself, there is actually a pipeline processing effect of five or more stages.

Each stage operates independently of the other stages, and theoretically five stages operate completely independently. Each stage can perform one processing in a minimum of 2 clocks. Therefore, ideally, pipeline processing proceeds every two clocks.

In the data processing device of this embodiment, there are instructions that cannot be processed by only one basic pipeline process, such as memory-memory operations and memory indirect addressing. However, the data processing device of this embodiment deals with these processes. However, it is designed to perform balanced pipeline processing as much as possible. That is, an instruction having a plurality of memory operands is decomposed into a plurality of pipeline processing units (step codes) at the decoding stage based on the number of memory operands and pipeline processing is performed. The method of disassembling the pipeline processing unit is described in detail in Japanese Patent Application No. 61-236456.

The information passed from the IF stage 31 to the D stage 32 is the instruction code 40 itself. The information passed from the D stage 32 to the A stage relates to the operation specified by the instruction (D
There are two types, one called code 41) and the other related to address calculation of operands (called A code 42). Information passed from the A stage 33 to the F stage is an R code 43 including an entry address of a microprogram routine and parameters to the microprogram, and an F code 44 including an address of an operand and access method instruction information. . The information passed from the F stage 34 to the E stage 35 is an E code 45 including operation control information and literals and an S code 46 including operands and operand addresses.

The EIT detected in a stage other than the E stage 35 does not start the EIT processing until the code reaches the E stage 35. Only the instructions processed in the E stage 35 are in the execution stage, and the instructions processed in the IF stages 31 to F stage 34 have not yet reached the execution stage.
Therefore, the EIT detected at a stage other than the E stage 35 only records the detection of it in the step code and transmits it to the next stage.

(3.1) Pipeline processing unit (3.1.1) Classification of instruction code field The pipeline processing unit of the data processing apparatus of this embodiment is determined by utilizing the characteristics of the format of the instruction set. As described in section (2), the instruction of the data processing device of this embodiment is a variable length instruction in units of 2 bytes, and is basically (2 byte instruction basic part + 0 to 4 byte addressing extension part). The instruction is configured by repeating 1 to 3 times.

In many cases, the instruction basic part has an opcode part and addressing mode specification part. When index addressing or memory indirect addressing is required, instead of the addressing expansion part (2 bytes multi-stage indirect mode specification part + 0 to 4 bytes addressing expansion Parts) are attached arbitrarily. In addition, depending on the instruction, a 2-byte or 4-byte extension section peculiar to the instruction is added at the end.

The instruction basic part includes the operation code of the instruction, the basic addressing mode, and the literal. The addressing extension is one of displacement, absolute address, immediate value, and branch instruction displacement. Instruction-specific extensions include register maps and immediate value specifications for I-format instructions. FIG. 6 shows the characteristics of the basic instruction format of the data processor of this embodiment.

(3.1.2) Decomposition of instruction into step code In the data processing device of the present embodiment, pipeline processing is carried out by making use of the characteristics of the above instruction format. In the D stage 32, a 2-byte instruction basic part + 0 to 4-byte addressing extension part), (multi-stage indirect mode designation part + addressing extension part) or an instruction-specific extension part is processed as one decoding unit. The decoding result of each time is called a step code, and after the A stage 33, this step code is a unit of pipeline processing. The number of step codes is peculiar to each instruction, and when the multistage indirect mode is not designated, one instruction is divided into a minimum of one step code and a maximum of three step codes. If there is a multistage indirect mode specification, the step code will increase accordingly. However, this is only the decoding stage as described later.

(3.1.3) Management of Program Counter All step codes existing on the pipeline of the data processing apparatus of this embodiment may be for different instructions, and the value of the program counter is managed for each step code. Every step code has the program counter value of the instruction that caused the step code. The program counter value attached to the step code and flowing through each stage of the pipeline is called a step program counter (SPC). SPCs are handed over to the pipeline stages one after another.

(3.2) Processing of each pipeline stage I / O step codes of each pipeline stage are named for convenience as shown in FIG. In addition, the step code performs processing related to the opcode,
There are two series, that is, an entry address of the micro ROM and a series of parameters for the E stage 35, and a series of operands for the micro instruction of the E stage 35.

(3.2.1) Instruction fetch stage The instruction fetch stage (IF stage) 31 fetches an instruction from a memory or a branch buffer, inputs it to the instruction queue, and outputs an instruction code 40 to the D stage 32.
Input to the instruction queue is done in aligned 4-byte units.
Fetching instructions from memory requires a minimum of 2 clocks for every 4 bytes aligned. When the branch buffer is hit, it is possible to fetch the aligned 4 bytes in 1 clock. The output unit of the instruction queue is variable every 2 bytes, and up to 6 bytes can be output during 2 clocks. Immediately after branching, it is possible to bypass the instruction queue and directly transfer the two bytes of the basic instruction portion to the instruction decoder.

Controls such as registering and clearing instructions in the branch buffer,
The IF stage 31 also manages the prefetch destination instruction address and controls the instruction queue.

The EIT detected in the IF stage 31 includes a bus access exception when fetching an instruction from memory and an address translation exception due to a memory protection violation.

(3.2.2) Instruction decode stage Instruction decode stage (D stage) 32 is IF stage 31
The instruction code 40 input from is decoded. Decoding is performed once every two clocks using the FHW decoder, NFHW decoder, and addressing mode decoder of the instruction decoding unit 52 and consumes 0 to 6 bytes of instruction code in one decoding process (return of RET instruction The instruction code is not consumed in the output processing of the step code including the destination address). About 35 bit control code which is A code 42 which is address calculation information and maximum 32 bit address modification information for A stage 33 and D code 41 which is intermediate decoding result of operation code is about 50 in one decoding. It outputs a bit control code and 8-bit literal information.

In the D stage 32, control of the PC calculator 53 for each instruction, branch prediction processing, pre-branch processing for pre-branch instructions, and instruction code output processing from the instruction queue are also performed.

The EIT detected in the D stage 32 includes a reserved instruction exception and an odd address jump trap at pre-branch. The various EITs transferred from the IF stage 31 are encoded in the step code and transferred to the A stage 33.

(3.2.3) Operand address calculation stage The operand address calculation stage (A stage 33) is roughly divided into two processes. One is a process of using the decoder 2 of the instruction decoding unit 52 to perform the subsequent decoding of the operation code, and the other is a process of calculating the operand address in the operand address calculation unit 54.

In the subsequent decoding process of the operation code, the D code 41 is input, and the R code 43 including the write reservation of the register and the memory and the entry address of the microprogram and the parameters for the microprogram is output. In addition,
The write reservation of the register or memory is for preventing the contents of the register or memory referred to in the address calculation from being rewritten by the preceding instruction on the pipeline and erroneous address calculation being performed. In order to avoid deadlock, write reservation of registers and memory is performed not for each step code but for each instruction. The write reservation of registers and memory is described in detail in Japanese Patent Application No. 62-144394.

Operand address calculation processing uses A code 42 as input,
According to the A code 42, the operand address calculation unit 54 performs address calculation by combining addition and memory indirect reference, and outputs the calculation result as an F code 44. At this time, a conflict check is performed at the time of reading the register or memory associated with the address calculation, and if the conflict is instructed because the preceding instruction has not completed the writing process to the register or memory, the preceding instruction performs the writing process at the E stage 35. Wait until it finishes. In addition, the operand address and the address of the memory indirect reference are I / O mapped to the memory.
It also checks whether it enters the O area.

The EIT detected at the A stage 33 includes a reserved instruction exception, a privileged instruction exception, a bus access exception, an address translation exception, and a debug trap due to an operand breakpoint hit at the time of memory indirect addressing. D code 41, A
If code 42 itself indicates that it caused an EIT, then A
The stage 33 transmits the EIT to the R code 43 and the F code 44 without performing address calculation processing on the code.

(3.2.4) Micro ROM access stage The operand fetch stage (F stage) 34 is also roughly divided into two processes. One is the access processing of the micro ROM, which is particularly called the R stage 36. The other is an operand prefetch process, which is particularly called an OF stage 37.
The R stage 36 and the OF stage 37 do not always operate at the same time, but operate independently depending on whether or not a memory access right can be acquired.

The micro ROM access process, which is the process of the R stage 36, is a micro process for producing an E code, which is an execution control code used for execution in the next E stage for the R code.
ROM access and micro instruction decoding processing. If the processing for one R code is broken down into more than one microprogram step, the micro ROM is used in the E stage 35 and the next R code 43 waits for the micro ROM access. The micro ROM access to the R code 43 is made at the last micro instruction execution in the E stage 35 before that. In the data processor of this embodiment, most of the basic instructions are executed in one microprogram step, so in practice, micro ROM access to the R code 43 is often made one after another.

There is no new EIT detected in R stage 36. R code 43
Indicates an instruction processing re-execution type EIT, the microprogram corresponding to the EIT processing is executed, so the R stage 36 fetches the microinstruction according to the R code 43. When the R code 43 indicates an odd address Jap trap, the R stage 36 conveys it to the E code 45. This is for pre-branch, E stage
At 35, if no branch occurs at the E code 45, the pre-branch is validated and an odd address jump trap is generated.

(3.2.5) Operand Fetch Stage The operand fetch stage (OF stage) 37 performs the operand prefetch process of the above two processes performed in the F stage 34.

In the operand prefetch, the F code 44 is input, and the fetched operand and its address are output as the S code 46. One F code 44 may cross word boundaries, but specifies an operand fetch of 4 bytes or less. The F code 44 also includes designation of whether or not to access the operand. When the operand address itself calculated in the A stage 33 or the immediate data is transferred to the E stage 35, the operand prefetch is not performed and the F code The contents of 44 are transferred as S code 46. When the operand to be prefetched matches the operand to be written by the E stage 35, the operand prefetch is not performed from the memory but bypassed. For the I / O area, the operand prefetch is delayed, and the operand fetch is performed after waiting for all the preceding instructions.

The EIT detected in the OF stage 37 includes a bus access exception, an address translation exception, and a debug trap due to a breakpoint hit for operand prefetch. When the F code 44 indicates an EIT other than the debug trap, it is transferred to the S code 46 and operand prefetch is not performed. When the F code 44 indicates a debug trap, the same processing as when the F code 44 does not indicate EIT is performed and the debug trap is set to the S code.
Tell 46.

(3.2.6) Execution stage E code 45, S code in execution stage (E stage) 35
Operates with 46 as input. The E stage 35 is a stage for executing instructions, and all the processes performed in the stages before the F stage 34 are pre-processes for the E stage 35. Jump instruction is executed at E stage 35, or EIT
When the process is activated, all the processes from the IF stage 31 to the F stage 34 are invalidated. E stage 35
Is controlled by the microprogram, and executes an instruction by executing a series of microprograms from the entry address of the microprogram indicated by the R code 45.

The reading of the micro ROM and the execution of the micro instructions are pipelined. Therefore, when a branch occurs in the microprogram, there is a space of 1 microstep. Further, the E stage 35 can use the store buffer in the data operation unit 56 to pipeline the operand store within 4 bytes and the next microinstruction execution.

In the E stage 35, the write reservation for the register and memory made in the A stage 33 is performed after writing the operand,
To release.

When the conditional branch instruction causes a branch at the E stage 35, the branch prediction for the conditional branch instruction was incorrect, so the branch history is rewritten.

A bus access exception is added to the EIT detected in E stage 35,
Address translation exception, debug trap, odd address jump trap, reserved function exception, invalid operand exception,
Reserved stack format exception, divide by zero trap, unconditional trap, condition trap, delayed context trap, external interrupt, delayed interrupt, reset interrupt, system failure.

All EITs detected in E stage 35 are processed by EIT, but detected between IF stage 31 to F stage 34 before E stage and reflected in R code 43 and S code 46.
Is not always EIT processed. IF stage 31-F
Although an EIT is detected during stage 34, all EITs that did not reach E stage 35 due to the preceding instruction having executed a jump instruction at E stage 35 are canceled. The instruction that caused the EIT was not executed in the first place.

External interrupts and delayed interrupts are directly accepted by the E stage 35 at instruction breaks, and the necessary processing is executed by the microprogram. Other various EITs are also processed by microprograms.

(3.3) State control of each pipeline stage Each stage of the pipeline basically has an input latch and an output latch and operates independently of other stages. Each stage completes the previous processing, transfers the processing result from the output latch to the input latch of the next stage, and when the input latch of the own stage has all the input signals necessary for the next processing, The process of is started.

In other words, in each stage, all input signals for the next process output from the previous stage are valid,
The current processing result is transferred to the input latch of the subsequent stage, and when the output latch becomes empty, the next processing is started.

All input signals must be available at the clock timing one clock before the operation of each stage. If the input signals are not complete, the stage enters the waiting state (waiting for input). When transferring from the output latch to the input latch of the next stage, the input latch of the next stage must be empty, and even if the input latch of the next stage is not empty, the pipeline stage is in the waiting state. (Waiting for output). If the necessary memory access right cannot be acquired, a wait is inserted in the memory access being processed, or other pipeline conflict occurs, the processing itself of each stage is delayed.

(4) Details of Memory Writing The outline of the data processing device has been described above. Here, the control method and configuration of the memory writing of this embodiment will be described.

(4.1) Description of Operation of Memory Write Control Section FIG. 8 shows the configuration of the memory write control section of this embodiment. First, the configuration of FIG. 8 will be described. 21 is the first instruction decoder of the D stage 32, 22 is the second instruction of the A stage 33
The instruction decoder, 27 is a micro ROM. Reference numeral 4 is an intermediate code passed from the first instruction decoder 21 to the second instruction decoder 22, and 5 is a parameter passed from the first instruction decoder 21 to the second instruction decoder 22. EAFLAG1 is the decoding result from the decoder 22 and is also a selection signal for addressing information. MEMWCNT2 is also the decoding result from the decoder 22 and is also a write control signal. MEM-D6, PUSH-D8, and ADDM-D9 show addressing information by the decoding result of the decoder 21, and CMEM12 at the A stage.
To generate. PMEM11 is addressing information of the previous step code stored in the latch 24. MEMW-R
Reference numeral 14 is a write signal sent to the F stage. Reference numeral 3 is an output from the instruction decoder 22 and indicates an entry address of the micro ROM. A microinstruction register 28 stores the microinstruction read from the microROM 27, and the microinstruction includes a bus access control field 29 for controlling bus access. The condition write instruction signal 26 is a signal for giving a memory write instruction when the operand is on the memory by the MEMW-R signal 14.
A logical product with 14 is taken to generate the memory write signal 15 in the E stage 35. In reality, the bus access control field 29 gives an unconditional write instruction and a conditional write instruction that reflects the execution result, but the description thereof is omitted.

The operation of FIG. 8 will be described below. In the D stage 32, the fetched data is analyzed by the decoder 21, and the intermediate code 4 and parameter 5 which are input to the decoder 22 are passed to the A stage 33. At the same time, MEM-D that indicates that the operand is specified in memory by an addressing mode other than push mode, pop mode, or multistage indirect mode
The signal 6, the PUSH-D signal 8 indicating that the push mode is designated, and the ADDM-D signal 9 indicating that the multistage indirect mode is designated are sent to the A stage 33 as the D code 41.

Intermediate code sent from D stage 32 at A stage 33
4, parameter 5 is input to PLA22 of the second instruction decoder, and microentry address and EAFLAG signal 1, MEMWCNT
A control signal such as signal 2 is generated.

1-bit EAFL as an effective addressing mode flag
Generate AG1 and write memory write signal MEMW-R signal 14
At the time of generation, it is selected whether to use the addressing mode signal of the same step code or the addressing mode signal of the immediately preceding step code. When the value of the EAFLAG signal 1 is "0", the addressing mode of the same step code is valid, and when it is "1", the addressing mode of the previous step code is valid. That is, when a step code including destination operand information, such as a G format instruction, is processed by the E stage 35 and an operand write is performed, it becomes "0".
It becomes "1" when the step code including the destination operand information is followed by the step code for writing the operand in the E stage 35 as in the I format instruction.

In addition, 1-bit MEMWCN as a memory write control signal
Set T signal 2. When the value of the MEMWCNT signal 2 is "0", the memory write signal MEMW-R14 is forcibly set to "0", indicating that the destination operand is on the register. In addition, when the value of MEMCNT signal 2 is "1", the memory write signal MEMW-R14 depends on the addressing mode.
Is set.

As described in section (2), the R and L format instructions have a fixed destination operand in the register, so MEMWCN is processed when these instructions are processed.
The T signal 2 is "0", and "0" is always output as the MEMW-R signal 14. By doing so, it is possible to perform processing in the R format and the L format by the same microinstruction as the instructions in other formats.

MEM-D signal 6, PUSH-D signal 8, ADD of the previous step code
If any one of the MD signals 9 is "1", the information is stored in the latch 24 and the PMEM signal 11 becomes "1". If any of the current MEM-D signal 6, PUSH-D signal 8, and ADDM-D signal 9 is "1", CMEM12 becomes "1". That is, CM
EM12 shows the information on whether the operand processed by the own step code is on the memory, and the PMEM signal 11 shows the information on whether the operand processed by the previous step code is on the memory. Shows.

When EAFLAG1 is "1", the previous addressing mode is enabled and the PMEM signal 11 is referred to. If both are "1", the MEMW-R signal 14 becomes "1". Also: When EAFLAG1 is “0”, the current addressing mode is enabled and CMEM12
Is referred to, and if both are "1", the MEMW-R signal 14 becomes "1". The MEMW-R signal 14 is sent to the R stage 36 as the R code 43 together with the micro entry address 3.

In the R stage 36, the micro ROM 27 is accessed by the micro entry address 3 in the R code 43, and the micro instruction is read into the micro instruction register 28. MEMW-R by the bus access control field in the micro instruction
When it is instructed to write the condition by referring to the signal, the condition write instruction signal 26 becomes "1".
At this time, if the MEMW-R signal 14 is "1", the memory write signal 15 sent to the execution unit becomes "1", and if the MEMW-R signal 14 is "0", the memory write signal sent to the execution unit. 15 becomes “0”. Actually, the bus access control field 29 also gives an unconditional write instruction and a conditional write instruction that reflects the effective result.
15 is set.

In the E stage 35, when the memory write signal 15 is "1", the data operation unit 56 performs the process of 2 clocks and then the memory write process.

(4.2) Example of Instruction Execution The flow of processing will be described below by taking the I-format ADD instruction in which the destination operand is designated in the register indirect mode as an example. The bit allocation of this instruction is as shown in FIG. 4 (d). However, as shown in FIG. 5B, the register indirect mode does not have an extension part of the addressing mode, so immediate data is placed immediately after the 2-byte instruction basic part. The flow of processing of this instruction is shown in FIG.

The I format instruction is decomposed into two step codes, a first step code including the destination operand information and a second step code including the information of the immediate data, and pipelined at the instruction decoding stage.

First, the processing of the first step code after the D stage 32 will be described.

In the D stage 32, the instruction basic part of 2 bytes is fetched from the IF stage 31 (step 91), the first stage decoding processing is performed, and the first instruction concerning the I format ADD instruction is performed.
A step code is generated (step 92). That is,
Intermediate code 4, parameter 5, addressing information MEM-D6, PUSH-D8, ADDM-D9 are sent as the D code 41, and address calculation information regarding the destination operand is sent to the A stage 33 as the A code 42. In this case, since the register indirect mode is used as the addressing mode, MEME-D6 is set to "1". Further, a part of the intermediate code 4 is held in the latch 24 as an intermediate decoding result and becomes an input to the instruction decoder 21 in the next decoding cycle.

At the A stage 33, the intermediate code 4 and the parameter 5 are input to the instruction decoder 22 and the second decoding process is performed. Since MEM-D6 is “1”, CMEM12 is also “1”. This value is held in the latch 24 when the processing of the A stage 33 is completed (steps 95 and 96). On the other hand, the address calculator 5
At 4, the destination address is calculated and transferred to the FA register that stores the address as the F code 44 (step 93). FA in F code 44 at F stage 34
The destination operand is fetched according to the address stored in the register, and is fetched into the SD register that stores the operand data as the S code 46. The destination address is S code 46.
Is transferred to the SA register that stores the address (step 94). Also, the micro ROM 27 is accessed (step 97), the micro instruction is decoded (step 98), and the E control signal group E in the E stage 35 is accessed.
Generate code 45 (step 99).

The E stage 35 transfers the contents of the SA register containing the destination address to the AA register which is an address register managed by the E stage 35. Also, save the contents of the SD register that contains the destination data to the working register (step 10
0).

Next, the second step code will be described.

In the D stage 32, the value held in the latch 24 is input, the first stage decoding process is performed, and the second step code for the I-format ADD instruction is generated (step 113). At this time, the immediate data in the instruction code is fetched (step 112). Intermediate code 4, parameter 5, and ME as addressing information as D code 41
Address calculation information for the M-D6, PUSH-D8, and ADDM-D9 to transfer the immediate data serving as the source operand as the A code 42 is sent to the A stage 33.

At the A stage 33, the second stage decoding is performed. In this case, EAFLAG1 is "1", and the addressing information PM at the time of processing the first step code which is the output of the latch 24 is processed.
Refers to EM11. MEMWCNT2 is also set to "1", indicating that the MEMW-R signal 14 is set in the addressing mode.

Since "1" is latched in PMEM11 reflecting the addressing mode of the destination operand, ME
"1" indicating writing to the memory is set in the MW-R14 (steps 114 and 115). Further, the address calculator 54 transfers the immediate value to the FA register (step 118).

In the F stage 34, the immediate value is transferred from the FA register to the SA register (step 119). Further, the micro ROM 27 is accessed (step 116) and the micro instruction is decoded (step 117), and the E code 45, which is an effective control signal group for performing addition processing by the ALU, is generated.
At this time, the bus access control field in the microinstruction refers to MEMW-R14 to give an instruction to determine whether to write (step 120), and the condition write instruction signal 26 becomes "1". Since the MEMW-R14 is "1", the memory write signal 15 is "1" (step 123).

In the E stage 35, an addition process of the value of the SA register that stores the immediate value and the working register that stores the value of the saved destination operand is performed according to the instruction of the E code 45, and the addition result is stored in the memory. The data is written in the DD register that stores the write data (step 124). Since MEMW-R14 is set to "1", the value of the DD register is stored at the address of the destination operand stored in the AA register (step
125).

The example in which the destination operand is in memory has been described above. When the destination operand is on the register, when the first step code is processed in the A stage 33, "0" is stored in the latch 24, reflecting the register direct mode. Also, E
At stage 35, the value of the register designated as the destination operand is saved in the working register. At the time of the second step code processing, the MEMW-R signal 14 becomes "0" and the memory write signal 15 also becomes "0", so the addition result is stored in the register designated as the destination operand. No store processing is performed.

When the multi-stage indirect mode is used as the addressing mode of the destination operand, the step code for the designated number of stages is generated between the first step code and the second step code. As it is absorbed on stage 33, it is F stage 34
The subsequent processing is exactly the same. Even in such a case, since the value of the latch 24 can be held during the multi-stage indirect mode processing in the A stage, the information as to whether the destination operand is in the register or in the memory is the second information. It is sent in association with the step code.

The bit allocation of the BFINS instruction for inserting bit fields is shown in FIG. 7 (b). The BFINS instruction is decomposed into 3 step codes and processed. Although the destination information exists in the second step code, writing to the actual operand is performed in the third step code. In this case, the same processing as described above can be performed by associating the addressing information of the destination operand of the second step code with the third step code.

The bit allocation of the POP instruction is shown in FIG. 7 (c). The POP instruction has an instruction basic part of 2 bytes and is apparently a 1-operand instruction, but in reality, the source operand is specified to be the stack top (memory) as a function of the instruction itself. Therefore, this instruction is a memory-memory transferable instruction. An instruction for performing a memory-memory operation in the data processing apparatus of this embodiment is basically decomposed into two step codes and a pipeline is flowed, and a POP instruction is also decomposed into two step codes in the D stage 32. The processing for the destination operand is performed by the first step code, and the writing to the operand is performed by the second step code. That is, PO
The P instruction is the same as the I format, and the same processing can be performed. In addition, the above-described processing can be applied to other instructions involving memory write.

As shown in FIGS. 4 (a) and 4 (b), the destination operand is fixed to the register in the R format instruction for performing the register-register operation and the L format instruction for performing the memory-register operation.
In particular, in the L format instruction, the operand specified in the general addressing mode is the source operand. Therefore, in these instructions, the information of the destination operand is not reflected in the MEM-D signal 6, PUSH-D signal 8 and ADDM-D signal 9 in the D code 41. During processing of these instructions, MEMWCNT2 is "0", and "0" is always output as the MEMW-R signal 14. By processing in this way, it is possible to process the R format and L format instructions by the same microinstruction as the instructions of other formats. For example, the L-format ADD instruction is processed by the same micro-instruction as the micro-instruction for the second step code of the G-format or E-format ADD instruction. In the case of the above-mentioned processing in which the destination operand is fixed to the register, the present invention can be applied to any data processing apparatus of the microprogram control system even if pipeline processing is not performed.

As described above, according to the present embodiment, the microinstruction is referred to the flag indicating whether the operand is in the register or the memory, and the store processing is performed after the operation is completed in the E stage 35 according to the value of the flag. Since it has a function to specify whether or not the destination operand is in a register or in memory, processing can be performed by the same microinstruction. Further, since it has a function of reflecting the previous addressing information in the next step code, the step code for transmitting the processing information regarding the write operand like the I format instruction and the step in which the writing is performed in the execution stage It can handle different codes well. Further, in the case of an instruction in which the destination operand is limited to the register, by instructing that the operand is on the register, the processing can be performed by the same micro instruction as the instruction of the other format.

〔The invention's effect〕

As described above, according to the present invention, whether the write operand is on the register or in the memory even when the processing unit for sending the information on the processing regarding the destination operand is different from the processing unit for writing in the execution stage. Since the instruction is given in correspondence with the processing unit in which the writing is performed in the execution stage, the writing processing to the operand can be performed by the same microinstruction regardless of the position of the operand. Further, even when an instruction whose destination operand is limited to a register is processed, since the operand is instructed to be on the register, the same microinstruction as other instructions can be processed. Therefore, micro-instructions can be shared and the area of the micro ROM can be reduced, so that an inexpensive data processing device can be obtained.

[Brief description of drawings]

1 is an overall block diagram of a data processing apparatus according to an embodiment of the present invention, FIG. 2 is a schematic diagram of a pipeline of a data processing apparatus according to an embodiment of the present invention, and FIG. 3 is according to an embodiment of the present invention. A schematic diagram of the instruction format of the data processing device,
4 is a diagram showing an instruction format of a data processing device according to an embodiment of the present invention, FIG. 5 is a diagram showing a format of an addressing mode of a data processing device according to an embodiment of the present invention, and FIG. 6 is a diagram showing the present invention. FIG. 7 is a diagram showing the characteristics of the instruction format of the data processing device according to one embodiment, and FIG.
FIG. 8 is a diagram showing bit allocation of ADD instruction, BFINS instruction, and POP instruction of format. FIG. 8 is a block diagram of a memory write control block of a data processor according to an embodiment of the present invention. FIG. 9 is execution of ADD instruction of I format. Fig. 10 is a flowchart showing the time, Fig. 10 is a diagram showing an outline of the pipeline of the conventional data processing device, Fig. 11 is a diagram showing the instruction format of the conventional data processing device, and Fig. 12 is a pipe in the conventional data processing device. It is a figure which shows the mode of line processing. In the figure, 51 is an instruction fetch section, 52 is an instruction decoding section (instructing means), 53 is a PC calculating section, 54 is an operand address calculating section, 55 is a micro ROM section (operand writing section), 56 is a data operation section, 57 Is an external bus interface unit, 58 is an address output circuit, and 59 is a data input / output circuit.

Claims (1)

[Claims] 1. A first stage comprising an operand instruction whose operand can be designated by a general-purpose addressing mode, decoding the instruction, and decomposing one instruction into one or a plurality of processing units in a pipeline. And a data processing device for pipeline processing an instruction by a plurality of stages including a second stage for executing an instruction according to an instruction of a microinstruction, wherein an operand specified by the general addressing mode is on a register or a memory. And a part of the microinstruction has a specific bit pattern, and when the indicating means indicates that the operand is on a register, the execution result is registered. Write to, the instruction means that the operand is in the memory And an operand writing unit that writes the execution result to the memory when instructing, and the first stage decodes an instruction that involves a writing process to a destination operand specified by the general-purpose addressing mode. When generating a plurality of the processing units including a first processing unit including processing information regarding the destination operand and a second processing unit that writes the destination operand in the second stage, The data processing device, wherein the instructing means indicates whether the destination operand is on a register or on a memory in association with the second processing unit.