JPH0769874B2 - Error detection device in memory system - Google Patents

Description

The present invention relates to an error detection device in a memory system including a memory unit and an error detection / correction circuit.

[Prior art]

FIG. 2 is a block diagram showing the system configuration of a memory system for implementing the conventional error detection method. As shown in the figure, the memory system has an error detection / correction circuit.
It is composed of 10 and a memory unit 20.

The error detection / correction circuit 10 is a check bit generation circuit 11 for 1-bit error correction / multi-bit error detection, a driver 12 with ON / OFF control terminals, a receiver 13 with ON / OFF control terminals, 1-bit error correction / multi-bits. A syndrome generation circuit 14 for error detection, a syndrome decoding circuit 15, a data correction circuit 16 and a driver 17 with an ON / OFF control terminal are provided.

In addition, the memory unit 20 includes a data word area 21 and a redundant
The word memory unit 22 is provided.

In the memory system having the above-described configuration, during writing into the memory unit 20 (hereinafter referred to as "memory write cycle"), the central processing unit (hereinafter referred to as "CPU") outputs the write data S ₁ of a plurality of n bits, the write control The signal S ₂ is turned on, the read request signal S ₄ is turned off, and the read control signal S ₇ is turned off.

As a result, the n-bit write data S ₁ becomes the write data S ₉ via the driver 12 with the ON / OFF control terminal that is in the ON state by the ON signal of the write control signal S ₂ , and then the data of the memory unit 20. It is written to the address specified by the CPU in word area 21.

At the same time, the write data S ₁ is input to the check bit generation circuit 11 (hereinafter referred to as “check bit generation circuit 11”) for 1-bit error correction / multi-bit error detection, and m is used according to a fixed rule with error correction capability. It becomes a check bit S ₈ for error correction of the bit, passes through the driver 12 with an ON / OFF control terminal which is in an ON state by the ON signal of the write control signal S ₂ , and becomes a check bit S ₁₀ for error correction, and then the memory section 20. It is written in the address specified by the CPU in the redundant / word area 22 of.

Further, since the read control signal S ₇ is off, the receiver 13 with the on / off control terminal is turned off, and the n-bit write data S ₉ and the m-bit error correction check bit S _{10 are obtained.}
Is suppressed by the receiver 13 with an ON / OFF control terminal.

Further, since the read request signal S ₄ is off, the driver 17 with the on / off control terminal is turned off, and the corrected read data S ₃ is not output.

As described above, the error correction check bit S ₈ is generated in the memory write cycle, and the redundancy / word area is generated.
22 and the write data S ₁ are written in the data word area 21.

Next, when reading from the memory unit 20 (hereinafter referred to as “memory read cycle”), the address to be read is read from the CPU by the memory unit 20.
Then, the read word S _{9 of} n bits from the data word area 21 and the check bit S ₁₀ of m bits of error correction from the redundant word area 22 are received by the receiver 13 with the ON / OFF control terminal. At this time, by turning off the write control signal S ₂ , turning on the read request signal S ₄ and turning on the read control signal S ₇ from the CPU, the receiver 13 with on / off control terminal is turned on and the write data receiving the S ₉ and error correction check bits S _10, as no correction read data S ₁₁ and error correction check bits S _12, respectively,
It is input to the syndrome generation circuit 14 for 1-bit error correction / multi-bit error detection (hereinafter referred to as "syndrome generation circuit 14"). The syndrome generation circuit 14 uses the uncorrected read data S ₁₁ and the error correction check bit S ₁₂ to determine the error correction check bit generation rule at the time of writing according to the reverse rule. Generates a syndrome bit S ₁₃ that can be determined.

This syndrome bit S ₁₃ is input to the syndrome decoding circuit 15, and the syndrome decoding circuit 15 decodes the error bit if the number of bits in which an error has occurred and 1 bit error occurs from the syndrome bit S _13. When a bit error is detected, the correction data S
At the same time that ₁₄ is output, the 1-bit error detection signal S ₅ is sent to the CPU
When a multi-bit error is detected, the multi-bit error detection signal S ₆ is reported to the CPU.

Next, the bit and the uncorrected read data S ₁₁ decoded by the syndrome decoding circuit 15 are corrected by the data correction circuit 16 in the case of a bit error, and the corrected read data S 11
_It becomes ₁₅ and is input to the driver 17 with ON / OFF control terminal. Driver 17 with ON / OFF control terminal is a read request signal
Since S ₄ is the ON signal, it is in the ON state, and the corrected read data S ₁₅ is sent to the CPU as the corrected read data S ₃ .

As described above, the error is detected in the memory read cycle, and when the 1-bit error is detected, the bit in which the error has occurred is corrected and the 1-bit error detection is reported to the CPU. When a multi-bit error is detected, a multi-bit error detection report is sent to the CPU.

[Problems to be Solved by the Invention] However, in the above conventional error detection method, since error detection / correction is performed only during the memory read cycle, erroneous data is stored in the memory unit 20 during the memory write cycle during error detection. Whether the data was written, or the data was inverted while the memory unit 20 was holding the data,
There was a problem that it was not possible to determine whether or not the data was erroneous while reading the data from 20, and the location of the error could not be limited.

The present invention has been made in view of the above points, and solves the problem of not being able to determine when a detected error has occurred, and provides an error detection device in a memory system that can provide accurate error occurrence information. To provide.

[Means for solving problems]

In order to solve the above problems, the present invention, as shown in FIG. 1, generates a logical sum of a write control signal S ₂ and a read control signal S ₇ in the error detection / correction circuit 10 of the memory system. A circuit 18 is provided so that the receiver 13 with an on / off control terminal for receiving the write data S ₉ and the error correction check bit S ₁₀ in the memory write cycle is operated by the logical sum signal from the logical sum circuit 18. Configured.

[Action]

With the above-described configuration, it is possible to detect an error even during a memory write cycle, limit an error occurrence point, shorten the investigation time of the error occurrence point, and reliably detect the error occurrence point.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of a memory system for implementing the error detection method according to the present invention. In the same figure, the parts given the same reference numerals as in FIG. 2 indicate the same or corresponding parts.

In FIG. 1, reference numeral 18 denotes an OR circuit, which is provided to adopt the error detecting method of the present invention. The write control signal S ₂ is connected to one input of the OR circuit 18, and the read control signal S ₇ is connected to the other input. The output is also connected to the receiver 13 with an on / off control terminal.

In the memory system configured as described above, in the memory write cycle, the CPU is complicated as in the conventional case.
Bit write data S ₁ is output, write control signal S ₂ is turned on, read request signal S ₄ is turned off, and read control signal S ₇ is turned off.

As a result, the n-bit write data S ₁ becomes the write data S ₉ via the driver 12 with the ON / OFF control terminal that is in the ON state by the ON signal of the write control signal S ₂ , and then the data of the memory unit 20. It is written to the address specified by the CPU in word area 21.

At the same time, the write data S ₁ is input to the check bit generation circuit 11 and becomes the m-bit error correction check bit S ₈ according to a fixed rule with error correction capability, and the on / off control terminal driver 12 in the on state is set. It becomes an error correction check bit S ₁₀ via the data and is written in the address of the redundancy / word area 22 of the memory unit 20 designated by the CPU. The above is the same operation as the conventional one.

Next, the output of the logic circuit 18 added in adopting the error detection method of the present invention is one write control signal S ₂
Is on because it is on. As a result, the receiver with on / off control terminal 13 is turned on and receives the n-bit write data S ₉ and the m-bit error correction check bit S ₁₀ .

The received uncorrected read data S ₁₁ and the error correction check bit S ₁₂ are input to the syndrome generation circuit 14. The syndrome generation circuit 14 can determine the bit in which an error has occurred from the uncorrected read data S ₁₁ and the error correction check bit S ₁₂ according to a rule that is the reverse of the rule for the error correction check bit generation rule performed at the time of writing. Generates syndrome bit S ₁₃ .

This syndrome bit S ₁₃ is input to the syndrome decoding circuit 15, and in the syndrome decoding circuit 15, the error bit is decoded from the syndrome bit S ₁₃ and in the case of 1 bit error, the error bit is decoded and the 1 bit error is generated. At the time of detection, the correction data S ₁₄ is output, and at the same time, the 1-bit error detection signal S ₅ is reported to the CPU, and at the time of detection of the multi-bit error, the multi-bit error detection signal S ₆ is reported to the CPU.

Next, the bits decoded by the syndrome decoding circuit 15 and the uncorrected read data S ₁₁ are
In the case of a 1-bit error, the data is corrected to be corrected read data S ₁₅ , which is input to the driver 17 with an ON / OFF control terminal. The driver 17 with ON / OFF control terminal is in the OFF state because the read request signal S ₄ is OFF, and the corrected read data S ₁₅ is not output.

As described above, in the memory write cycle, the check bit for error correction is generated, and it is used as the redundancy / word area 22
To the data word area 21 and detect an error. When a 1-bit error is detected, a 1-bit error detection report is sent to the CPU. When a multi-bit error is detected, a multi-bit error detection report is sent to the CPU.

Next, during the memory read cycle, the CPU turns off the write control signal S ₂ simultaneously with the conventional memory read cycle.
The OR circuit added by the present invention by setting the read request signal S ₄ to ON and the read control signal S ₇ to ON
The output of 18 is turned on because the read control signal S ₇ of one input is turned on. As a result, the receiver with on / off control terminal 13 is turned on, and the same operation as the conventional memory read cycle is performed.

As a result, similarly to the conventional circuit, the error is detected in the memory read cycle, and when the 1-bit error is detected, the bit in which the error has occurred is corrected and the 1-bit error detection report is sent to the CPU. When a multi-bit error is detected, a multi-bit error detection report is sent to the CPU.

As described above, according to the above-described embodiment, the error detection / correction circuit 10 writes the write data during the memory write cycle.
A logic circuit for turning on the receiver 13 with an on / off control terminal for receiving S ₉ and the error correction check bit S _10.
By providing 18, it is possible to detect an error even during a memory write cycle, and by limiting the error occurrence location, it is possible to shorten the investigation time of the error occurrence location and reliably detect the error occurrence location.

〔The invention's effect〕

As described above, according to the present invention, the following excellent effects can be obtained.

An OR circuit for generating an OR signal of the write control signal and the read control signal is provided, and the output of the OR circuit is connected to the read control signal input terminal of the second driver with ON / OFF control terminal. With a simple configuration of providing a circuit, an error can be detected even during a memory write cycle, and an error occurrence location can be limited, so that the reliability of the error occurrence location can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a memory system for implementing an error detection method according to the present invention, and FIG.
FIG. 1 is a block diagram showing a system configuration of a memory system for implementing a conventional error detection method. In the figure, 10 ... Error detection / correction circuit, 11 ... Check bit generation circuit, 12 ... Driver with ON / OFF control terminal,
13 …… Driver with ON / OFF control terminal, 13 …… Receiver with ON / OFF control terminal, 14 …… Syndrome generation circuit,
15 …… Syndrome decode circuit, 16 …… Data correction circuit, 17 …… Driver with ON / OFF control terminal, 18 …… OR circuit, 20 …… Memory section, 21 …… Data word area,
22 …… Redundant / word area.

Claims (1)

[Claims] 1. A memory unit (20) and an error detection / correction circuit (10) are provided, and the memory unit (20) stores data for storing write data.
A word area (21) and a redundant word area (22) for storing error detection / correction check bits are provided. The error detection / correction circuit (10) receives write data from the CPU and detects an error. A check bit generation circuit (11) for generating a check bit for correction and a write control signal from the CPU, and when the write control signal is on,
A driver with a first on / off control terminal for outputting the write data and the error detection / correction check bit to the data word area (21) and the redundancy word area (22) of the memory section (20), respectively ( 12) and the input terminal is connected to the terminal of the memory section (30) to which the output terminal of the first on / off control terminal-equipped driver (12) is connected.
When the read control signal from the CPU is received and the read control signal is on, the write data from the data word area (21) and the redundant word area (22) of the memory section (20) and the error detection A receiver (13) with an on / off control terminal that takes in a check bit for correction, and the uncorrected write data received by the receiver (13) with an on / off control terminal and an error detection / correction check bit are input and written. A syndrome generation circuit (14) that generates a syndrome bit according to a rule that is the reverse of the error correction check bit generation rule that is sometimes used, and inputs the syndrome bit, determines the bit in which an error has occurred, and outputs corrected data. Syndrome day code circuit (15), data for inputting the corrected data and the uncorrected write data and outputting corrected read data A positive circuit (16) and a second driver (17) with an on / off control terminal for receiving the read request signal from the CPU and outputting the corrected read data to the CPU when the read request signal is on. An error detection device in a memory system comprising: a logical sum circuit (18) for generating a logical sum signal of the write control signal and the read control signal.
The output of 8) is the receiver with the ON / OFF control terminal (13)
2. An error detecting device in a memory system, wherein the error detecting device is connected to the read control signal input terminal.