JPH0770169B2 - PLL circuit for magnetic disk device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic disk device PLL circuit, and more particularly to a PLL circuit used when reading data from a magnetic disk device such as a floppy disk device or a hard disk device.

[Conventional technology]

Conventionally, this type of PLL circuit is a one-shot system in which an input data signal is input from terminal 1 as shown in FIG. 7, and the rising edge of the input data signal is used as a trigger to output only 1/4 times the minimum input data interval T0. It is configured so that it is inputted to the set side of a Yaltimibrator circuit (hereinafter abbreviated as MLT) 7 and a reset set flip-flop (hereinafter abbreviated as RSFF) 8. The outputs of MLT7 and RSFF8 are input to the phase detector 9, and the phase detector 9 charges the charge pump 3 up or down according to the input phase difference. The output of the charge pump 3 is the low-pass filter 4
After being band-limited by, it is input to a voltage controlled oscillator (hereinafter abbreviated as VCO) 5. Then, the output of VCO5 is frequency-divided by the frequency divider 6 whose frequency division ratio can be set, and then the frequency-divided signal is input to the reset side of RSFF8 described above. It is configured to follow.

A timing chart of this conventional RLL circuit is shown in FIG. Here, the center frequency f osc of VCO5 is f os when the minimum data transfer rate of the input data signal is T0.
c = 4 (1 / T0) is set, and the frequency divider 6 is set to divide by two.

From FIG. 8, for example, the first input data signal changes the output of MLT7 and RSFF8 from the low level to the high level at the rising edge thereof, the MLT7 maintains the high level state for the T0 / 4 section, and the output of RSFF8 is , At the next rising edge of the first VCO5 oscillation signal, it returns to low level. The phase detector 9 detects the phase difference between the rising edge of the output of the MLT7 and the rising edge of the RSFF8 when the μPC1008C manufactured by NEC Corporation or the MC4044 manufactured by Motorola is used later, and the phase difference is detected as the phase difference. Depending on, the up (UP) signal and the down (DW) signal are made, the high level of the charge pump output,
It creates three states: floating and low level.

In the first input data signal, the phase of the input data signal and the phase of the output signal of VCO5 (that is, the output phase of frequency divider 6)
Shows a state of zero (just lock), the output of the charge pump shows a floating state, and holds the oscillation frequency of VCO5. The second input data signal shows the phase delay state of the VCO oscillation signal, and the falling edge of the MLT7 output is earlier than the falling edge of the RSFF8 output, so the corresponding up signal is output and the charge pump , The output is set to high level accordingly. On the other hand, with the third and fourth input data signals, the phase advance state of the VCO oscillation signal is shown, and the down signal is output only for the time of the rising edge difference between the outputs of MLT7 and RSFF8, and the charge pump is The output is set to low level by that amount, and the oscillation frequency of VCO5 is controlled so as to match the phase of the input data signal.

[Problems to be Solved by the Invention] The conventional PLL circuit described above, for example, when used in a reading circuit of a floppy disk device, corresponds to a change in data transfer rate of 125,250,500 kbps. The high level output section T _MLT and the frequency division ratio of the frequency divider 6 are set as shown in Table 1.

Conventionally, in modes with a relatively low data transfer rate of 250 kbps or less, the MLT7 is composed of a digital counter that counts 8, 16, 32 MHZ as a clock, but in the 500 kbps mode, the quantization generated by the digital counter is used. Since the phase error caused by the error (1 clock) deteriorates the reading accuracy, ICs with functions such as the 74121 TTL IC that can set the output width with external resistors and capacitors are usually used. Preventing subordination.

However, like floppy disk devices that can support high-speed data transfer rates such as recent IMbps and 2Mbps, and hard disk devices that have a data transfer rate of 5Mbps or more,
A disk device capable of supporting various kinds of high-speed data transfer rates requires a plurality of one-shot multivibrator circuits, which has a drawback that a plurality of external resistors and capacitors are required.

In the vicinity of zero phase difference, the up / down signal of the phase detector has a narrow data width, and while the signal is transmitted to the input of the low pass filter via the charge pump, the transmission system If there is no transmission capability of the phase detector up,
The down signal disappears on the way, and there is an apparent range in which the phase difference cannot be detected. For this, the VCO
However, there was a drawback that the oscillation frequency of had a jitter and poor stability after locking the PLL circuit.

Further, when the input noise 6 is superimposed as in the case of the fifth input data signal of FIG. 8, the output waveform of the MLT7 falls only once, but the output waveform of the RSFF8 The phenomenon that the falling appears twice occurs. The phase detectors such as the μPC1008C and C4044 described above output the difference between the falling edges of the input signals as a phase difference, and thus have a drawback that they malfunction due to this input noise.

[Means for solving problems]

The PLL circuit for the magnetic disk device of the present invention has an input signal,
A PLL circuit for a magnetic disk device that detects a phase difference between a signal obtained by frequency-dividing the output of a voltage-controlled oscillator by a frequency divider, the output being set at the edge of the input signal, At the edge of the output signal, the first logic circuit that resets the output, and immediately after the first logic circuit resets the output,
A second logic circuit which sets as an output a half cycle of the output signal of the frequency divider, and when the output of the second logic circuit is set, the output of the first logic circuit is set. A phase detecting means constituted by a circuit for preventing the output, and outputs a high level when the output of the first logic circuit is set, and outputs a low level when the output of the second logic circuit is set, Phase output means for keeping the output of the first and second logic circuits in a floating state during a period in which the output is not set, a low-pass filter for band limiting the output of the phase output means, and the low-pass filter. A voltage-controlled oscillator in which the oscillation frequency range is limited so that the frequency of the output signal of the frequency divider at the output of the filter is 1/2 to 2 times the frequency of the input signal. ing.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG.
In one embodiment of the present invention, an input data signal is input from the terminal 1 and a phase difference between the input signal and the output signal of the frequency divider 6 is detected by the phase detector 2 and the phase difference is detected by the charge pump 3 according to the phase difference. Is converted into a voltage, the oscillation frequency of the VCO 5 is changed via the low pass filter 4, and the output of the VCO is input to the frequency divider 6 to form a PLL circuit.

FIG. 2 shows the configuration of the phase detector 2 used in one embodiment of the present invention. In FIG. 2, an input data signal is input from a terminal 1 and is input to a clock terminal of a D-type flip-flop (hereinafter abbreviated as DFF) 24. When the output of DFF26 is low level, the output of DFF24 becomes high level at the rising edge of the input data signal. The output of DFF24 is
It is connected to the reset terminal and data terminal of DFF25,
At the fall of the output of the frequency divider 6, the inverted output of DFF25 is set to low level. Furthermore, the inverted output of DFF25 is connected to the reset terminal of DFF24, and when it goes low, DF
Reset the output of F24. In other words, the output of DFF24 is DFF26.
When the output of is at a low level, the rising edge of the input data signal is set and reset at the falling edge of the output of the frequency divider 6. On the other hand, when the output of the DFF 24 is high level, the output of the DFF 26 becomes high level at the rising edge of the inverted signal of the frequency divider 6, that is, at the falling edge of the frequency divider 6. The output of DFF26 is connected to the data terminal and reset terminal of DFF27, and the inverted output of DFF27 is the output of frequency divider 6 and the forward rotation signal via inverters 28 and 29, that is, the rise of the output of frequency divider 6. To low level. Further, the inverted output of DFF27 is connected to the reset terminal of DFF26 and resets the output of DFF26 when it goes low. That is, the output of the DFF26 is set at the falling edge of the frequency divider 6 and reset at the rising edge of the divider 6 when the output of the DFF24 is at the high level.

In the present embodiment, the output of the DFF 24 described above is used as the up signal of the phase detector, the output of the DFF 26 is used as the down signal, and is used as the input signal to the charge pump 3. In other words, the output of the DFF24 is connected to the positive power supply terminal 21
Input to the gate of P-type MOSFET 31 connected to
N-type MOSFE that connects the output of 6 to the negative power supply terminal 22
Input to the gate of T32, the drains of the MOSFETs 31 and 32 are connected to each other and output to the charge pump output terminal 23.

The phase detection characteristic of the phase detector of this embodiment is as shown in FIG. 3, and the timing chart of the phase control of the PLL circuit of this embodiment is as shown in FIG. That is, in FIG. 5, at the first rising edge of the input data signal, as described above, the output of the DFF24 becomes high level, and at the first rising edge of VCO oscillation (falling edge of the frequency divider output), it becomes low level. At the same time, the output of DFF26 goes high and the input of DFF24 goes low. Then, at the rise of the VCO oscillation (rise of the frequency divider), the output of DFF26 becomes low level and the input of DFF24 becomes high level. Therefore, the charge pump output terminal 23 sets the output to the high level only in the high level section of the output of the DFF 24, sets the low level only in the high level section of the output of the DFF 26, and sets the other sections in the floating state. In the PLL circuit of the present embodiment, the phases are controlled so that the high level sections of these DFFs 24 and 26 are equal.

Further, in the present embodiment, the output of the DFF24 is set at the rising edge of the input signal and the output is reset at the falling edge of the output of the frequency divider 6, but even if the output of the DFF24 is set at the falling edge of the input signal. , DFF2 at the rising edge of frequency divider 6 output
It can be easily inferred that similar control can be performed even if the output of 4 is reset.

In FIG. 5, in the first input data signal, the difference between the phase of the input data signal and the phase of the output signal of VCO5 (that is, the output phase of the frequency divider 6) is zero (just lock).
The second input data signal shows the phase delay state of the VCO oscillation signal, and the high level section of DFF24 is longer than the high level section of DFF26 by the amount of the phase delay. Therefore, the output voltage of the charge pump 3 is raised accordingly. The third and fourth input data signals show the phase lead state of the VCO oscillation signal, and the high level section of DFF24 is shorter than the high level section of DFF26 by the amount of phase lead, The output voltage of the chart pump 3 is lowered accordingly.

On the other hand, as in the case of the fifth and sixth input data signals,
The output of DFF24 goes high due to the rising edge of the input data signal, and goes low when the output of the divider goes low.While the output of DFF26 is high, the input data signal goes high again due to input noise. In such a case, if a high level is always input to the DFF24 input data terminal, a pulse as shown by the dotted line is generated in the DFF24 output waveform, and the DFF24 output and D
When the output of FF26 becomes high level at the same time, MOSF
The malfunction that ET31 and 32 turn on at the same time occurs. Therefore, in order to prevent such malfunction, the inverted output of DFF26 is connected to the input data terminal of DFF24 so that the output of DFF24 does not become high level when the output of DFF26 is high level.

In this way, the PLL circuit of the present embodiment synchronizes with the input data signal and is a stable VC that does not easily malfunction due to input noise.
O oscillation signal can be obtained.

In addition, since the phase detection characteristic has a periodicity of 2π as shown in FIG. 3, there is a high possibility that the input data transfer rate T0 is an integer multiple or an inverse integer multiple and is erroneously locked. As a measure to prevent this, the oscillation frequency of VOC5 f osc
, 1 / (2 * T0) <(1 / N) * fosc <2 / T0 N; the frequency division ratio of the frequency divider 6 can be restricted.

For example, as this means, as shown in FIG.
In a VCO circuit equipped with a voltage-current conversion circuit, which has been disclosed in Japanese Laid-Open Publication No. 244115 (current-controlled oscillator),
Connect the resistor 46 (R0) and resistor 45 (R1) to R1> 2 * R0 T0 = 1 (N * fosc) fosc = (V _SH −V _SL ) / (2 * C0) * VDD / (2 * R0 ) V _SH , V _SL : Hysteresis voltage value of Schmitt trigger circuit 48 C0: Capacitance value of capacitor 57 can be set so that it is satisfied.

In FIG. 4, a terminal 44 is an input terminal for applying a half value of the power supply voltage VDD, and an operational amplifier (hereinafter abbreviated as operational amplifier) 47 and a P-type MOSFFT 49 for connecting a back gate to a source.
Provides a circuit that voltage-follows the source electrode of the P-type MOSFET 49 to VDD / 2 (V). The source of the P-type MOSFET 49 has a resistor R0 connected to the positive power supply terminal 41 and one of them.
The resistor R1 connected to the input terminal 40 of the VCO circuit is connected.

If the input voltage of the terminal 40 is V _IN , the current I flowing in the MOSFET 49 is given by I = VDD / (2 * R0) − (1 / R1) * (VDD / 2−V _IN ). Is transferred by the N-type MOSFETs 53 and 54 having a current mirror configuration to be used as an input current of the current control type oscillation circuit.

FIG. 6 shows another configuration of the phase detector 2 in the PLL circuit which is an embodiment of the present invention. The signal input from the input data terminal 1 is first input to the AND gate 80. AND gate 80
Always outputs a low level when the output of the NAND gate 65 of the RSFF75 is at a high level, and outputs the same waveform as the signal input from the input data terminal when the output of the NAND gate 65 of the RSFF75 is at a low level. The output signal of the AND gate 80 is a delay circuit composed of an inverter 67 and a capacitor 70,
The waveform is shaped by the NAND 60 into a data width corresponding to the delay time generated in the delay circuit, and the result is input to the set terminal of the RSFF 74 composed of NAND 63 and 64. On the other hand, the reset terminal is the input terminal
After the output signal of the frequency divider 6 input from 20 is inverted by the inverter 76, the signal whose data width has been shaped is input by the inverter 68, the capacitor 71 and the NAND 61 as in the set side. The output of RSFF74 is an inverter 77 and a capacitor 78.
After the data width is shaped by the delay circuit consisting of NAND79, it is input to the set terminal of RSFF75 consisting of NAN65 and NAN65. On the other hand, the divider 6 is connected to the reset terminal of this RSFF.
The output of is shaped after the data width is shaped by the delay circuit consisting of the invert 69 and the capacitor 72, and the NAND 62, and then input.

Then, the inverted output of RSFF74 is input to the gate of the P-type MOSFET 31 of the charge pump 3 in the same manner as described with reference to FIG. 2 of the present embodiment, and the inverted output of RSFF75 and the output of the frequency divider 6 are supplied to NOR73.
Then, the signal after the logic synthesis is input to the gate of the N-type MOSFFT 32.

In the PLL circuit using this configuration for the phase detector, RSFF74,75
Since the data shaping circuit is added to the input of,
The feature is that impulsive noise is prevented from being input to RSFF74 and 75 to prevent malfunction.
As described in the embodiment, when the output of the NAND gate 65 of the RSFF75 is high level, the inverted output of the NAND gate 65 of the RSFF75 is used to prevent the malfunction that the MOSFETs 31 and 32 are simultaneously turned on.
It is characterized in that the input signal is gated so that the output signal of 0 is always kept at the low level.

As described above, the PLL circuit of the present invention has a phase detector, a charge pump, a low-pass filter, a VCO, and a frequency divider whose frequency division ratio can be set. In
The output goes high at the rising edge of the input data signal,
At the rising edge of the output of the frequency divider, the first means for making the output low level, and at the falling edge of the output of the first means, making the output high level, and at the rising edge of the divider, the output To a low level, and means for preventing the output of the first means from becoming a high level while the output of the second means is at a high level. The output of 1 controls the output of the charge pump and eliminates the need for a one-shot multivibrator circuit that produces the reference signal of the phase detector.

〔The invention's effect〕

As described above, according to the present invention, since the one-shot multivibrator circuit which is conventionally required is not required, it is possible to cope with various data transfer rates by changing the frequency division ratio of the frequency divider 6. As can be seen from FIG. 5, the active logic width of the up and down signals is zero in the conventional case in the phase difference zero (just lock) state, whereas in the present invention, a sufficiently large value is set. Therefore, there is no section in which the phase detector does not respond in the vicinity of the phase difference of zero, and there is an effect that the jitter of the oscillation frequency of the VCO is reduced.

Furthermore, for the input data signal on which the input noise is superimposed,
Since the configuration is less susceptible to the influence of input noise, malfunction due to input noise can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a PLL circuit which is an embodiment of the present invention,
FIG. 2 is a diagram showing a configuration of a phase detector in a PLL circuit which is an embodiment of the present invention, FIG. 3 is a diagram showing characteristics of this phase detector, and FIG. 4 is a voltage-controlled oscillator. 5 and 5 are timing charts of the PLL circuit of this embodiment, FIG. 6 is a diagram showing another configuration of the phase detector of this embodiment, and FIG. 7 is a conventional PLL circuit. 8 and 9 are timing charts of a conventional PLL circuit. 1 ... Data input terminal, 2 ... Phase detector, 3 ... Charge pump, 4 ... Low-pass filter, 5 ... Voltage-controlled oscillator, 6 ... Divider, 7 ... One-shot Multi-vibrator circuit, 8 ... Reset flip-flop (RSF
F), 24,25,26,27 …… D-type flip-flop (DFF), 2
0 …… Input terminal for output signal of frequency divider, 28,29,30,67,68,6
9,76,77 …… Inverter, 21 …… Static power supply terminal, 22 …… Negative power supply terminal, 23 …… Charge pump output terminal, 31,32,4
9,50,51,52,53,54,55,56 …… MOS field effect transistor (MOSFET), 80 …… 2-input AND, 57,70,71,72,78 …… Capacitor, 47 …… Op Amp, 48 …… Schmidt amplifier, 42 …… VCO output terminal, 44 …… Reference power input terminal, 60,
61,62,63,64,65,66,79 …… 2-input NAND, 73 …… 2-input NO
R.

Claims (1)

[Claims] 1. A PLL circuit for a magnetic disk device, which detects a phase difference between an input signal and a signal obtained by dividing an output of a voltage controlled oscillator by a frequency divider, wherein an output is generated at an edge of the input signal. The first logic circuit that sets and resets the output at the edge of the output signal of the frequency divider, and immediately after the first logic circuit resets the output,
A second logic circuit that sets as an output a half cycle of the output signal of the frequency divider, and when the output of the second logic circuit is set, the output of the first logic circuit is set. A phase detection unit constituted by a circuit for preventing the output of the first logic circuit, and outputs a high level when the output of the first logic circuit is set, and outputs a low level when the output of the second logic circuit is set. Phase output means for keeping the output of the first and second logic circuits in a floating state during a period in which the output is not set, a low-pass filter for band-limiting the output of the phase output means, and the low-pass filter. The oscillation frequency is controlled by the output of the filter, and the frequency of the output signal of the frequency divider is equal to the frequency of the input signal.
A PLL circuit for a magnetic disk device, comprising: the voltage-controlled oscillator whose oscillation frequency range is limited to 1/2 to 2 times.