JPH0770170B2 - Digital audio playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital audio reproducing apparatus, and more particularly to a digital audio reproducing apparatus with improved audio performance.

(Prior Art) In a CD player, for the purpose of reducing noise due to a digital system or a servo system, a digital reproducing section for reproducing sampled and quantized digital data of a pickup servo system, a digital signal processing circuit, or the like, A digital / analog converter (D / A converter) and subsequent audio reproduction units are separated.

An example of such a device is from pages 12 to 19 of Electronics Life March issue (1987) published by Japan Broadcasting Corporation.
Shown on the page. As disclosed in the document, the device transmits / receives data from the digital reproducing unit to the audio reproducing unit by adding a synchronizing signal for each sampling frequency, modulating the biphase mark signal, and transmitting it by a single cable. Is being done.

(Problems to be Solved by the Invention) In the above-mentioned conventional technique, since the clock is reproduced from the received data, clock jitter occurs during transmission or by the PLL circuit forming the clock reproducing circuit on the receiving side. When the clock jitter occurs, digital
There is a problem that the sampling point at the time of analog conversion has jitter, and the fidelity of reproduction in the time axis direction deteriorates. Further, this causes a problem that distortion in a high frequency band of audio performance is deteriorated.

The object of the present invention is to eliminate the above-mentioned problems of the prior art,
It is to provide a digital audio reproducing apparatus for reproducing a faithful audio signal.

(Means for Solving Problems) The above-mentioned object is to provide an oscillator serving as a reference clock provided on the D / A converter side (analog reproduction side) and the output of the oscillator to the digital reproduction side. It is achieved by providing means for operating the digital reproduction side.

(Function) By providing an oscillator on the analog playback side, the jitter that occurs during data transmission can be absorbed by digital processing before D / A conversion, and the timing of D / A conversion can be generated by the oscillator. This enables faithful reproduction in the time axis direction.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram of the CD player of this embodiment, in which 14 denotes a digital reproducing section (hereinafter referred to as a CD player section) and 15 denotes an analog reproducing section (hereinafter referred to as an audio section). . The CD player section 14 and the audio section 15
And are connected by a cable.

In the CD player unit 14, a signal is taken out from the disc 1 by the optical pickup 2, and the signal is amplified by the preamplifier 3. The error signal in the track and focus directions of the pickup 2 obtained by the preamplifier 3 is sent to the pickup 2 via the pickup servo circuit 4 to control the pickup 2. Further, the signal component obtained by the preamplifier 3 is subjected to the detection of the synchronizing signal and the error correction process by the signal processing circuit 5, and the 16-bit data 5D and the sampling frequency timing signal 5C are D / A.
It is added to the converter 8 and the serial output circuit 12.

The D / A converter 8 converts the left and right two-channel data into analog signals and outputs the left and right two-channel analog data 8L, 8
It outputs R to the output terminals T1 and T2. Further, the serial output circuit 12 adds a new frame synchronization signal to 16-bit data, modulates it into a bi-phase mark signal, and outputs serial data 12B. The serial data 12B is applied to the output terminal T3.

The clock generated from the oscillator 9 and the PLL circuit 10 is switched by the switch 11 and added to the signal processing circuit 5. The clock acts as the reference clock for the CD player. Specifically, the reference clock of the motor servo circuit 6 is used to control the number of revolutions of the motor 7, and the clock 5C of the sampling frequency is determined.

The PLL circuit 10 is a feslocked loop circuit for setting the clock frequency applied to the input terminal T5 to the same frequency as the oscillator 9. For example, the output of oscillator 9 is 8.4672MHz
Then, if the clock applied to the input terminal T5 is 5.6448 MHz, the PLL circuit divides the input clock of the input terminal T5 by 128, and divides the output (8.4672 MHz) of the oscillator in the PLL circuit 10 by 192. By comparing the phases, the output of PLL circuit 10 is 8.4
672MHz can be obtained.

Reference numeral 13 is a switch for generating a selection signal that determines which side the switch 11 is to be selected, and the selection signal 11C generated from the switch 13 is applied to the input terminal T4. By selecting the switch 11 to the oscillator 9 side, the CD player section 14 operates normally.

Reference numeral 15 is an audio section for adding the serial data signal 12B sent from the CD player section 14 via a cable to the input terminal T6 to obtain analog signals 22L and 22R.

Reference numeral 16 is a bit synchronization circuit, which performs clock recovery from the biphase mark signal sent via the input terminal T6, and demodulates the bit synchronization clock 16C and the captured data 16D.
18 and the frame sync detection circuit 17.

The frame synchronization detection circuit 17 detects the synchronization signal pattern in the serial signal added for each sampling frequency, and adds the detected synchronization pulse 17F to the demodulation circuit 18. Demodulation circuit 18
Is a bit sync clock 16C, data 16D from the bit sync circuit 16, and a sync pulse from the frame sync detection circuit 17.
The 17F demodulates the biphase mark signal and outputs the demodulated 16-bit data 18D and the sampling frequency timing 18C.

Reference numeral 23 is an oscillator, and as described above, for example, the sampling frequency 44.1
It outputs a clock of 5.6448MHz which is 128 times the frequency of KHz. The timing circuit 24 divides the clock of the oscillator 23 to generate a sampling frequency timing signal. The sampling frequency timing signal is applied to the switch 21 and is also supplied to the buffer register 19 for temporarily storing data as its output timing signal.

20, 21 are switches. The switch 20 serves to switch the data before and after the buffer register 19. On the other hand, the switch 21 supplies the timing signal supplied to the D / A converter 22,
The timing signal 18C output from the demodulation circuit 18 or the sampling frequency timing signal output from the timing circuit 24 is selected. 22 is a D / A converter, and the D / A converter 22 converts the data into an analog signal by the data and the sampling frequency timing signal applied via the switches 20 and 21. The D / A converter 2
Analog outputs 22L and 22R from 2 are applied to output terminals T8 and T9. Further, the switch 25 controls the switches 20 and 21 by applying a signal 25C to the input terminal T10.

Next, the operation of this embodiment having the above configuration will be described below. First, in the state shown in FIG. 1, that is, when the switch 13 and the switch 25 are open, the switch 11 is selected on the oscillator 9 side, and the switches 20 and 21 are selected on the output side of the demodulation circuit 18. The operation at that time will be described.

In this state, the same circuit operation as that conventionally performed is performed, and the clock frequency Fx8.4672 of the oscillator 9 is used.
The signal processing circuit 5 is operated at MHz. As a result, the signal processing circuit 5 outputs the 44.1 kHz clock 5C of the Fx divided by 192 to operate the D / A converter 8. Further, the clock frequency Fx operates as a reference clock of the motor servo circuit 6 and controls the motor 7 to reproduce the data of the transmission rate 4.3218 Mbps from the pickup 2.

Further, the clock frequency Fx is divided by 2/3 by the signal processing circuit 5, and the 5.6448 MHz clock 5B is output to the serial output circuit 12. The serial output circuit 12 performs an operation of modulating the data 5D into a biphase mark signal with this clock 5B. The output data of the serial output circuit 12 has half the value of the clock 5B as the transmission rate and is 2.8224
Mbps. This value is the L. output from the signal processing circuit 5.
R2 channel data 5D transmission rate 44.1KHz x 2 channels x 16 bits = 2x of 1.4112Mbps, 1.4112Mbps other than data is the frame sync signal indicating the division of each sample, subcode, category, etc. Used to transmit the indicated code.

Therefore, the CD player unit 14 operates with the clock frequency Fx of the oscillator 9 as the basic frequency, and the serial output circuit 12
The transmission rate of is also determined by the oscillator 9.

In the audio section 15, the signal 12 from the serial output circuit 12
Upon receiving B, the bit synchronization circuit 16 reproduces the clock 16C synchronized with the transmitted data. This clock frequency is 5.6448 MHz, which is twice the transmission rate of 2.822 Mbps. Serial data 16 output from bit synchronization circuit 16
The frame and the clock 16C have their sync patterns detected by the frame sync detection circuit 17. As a result, the frame sync detection circuit 17 outputs a sync pulse 17F in units of one sampling frequency.

The demodulation circuit 18 demodulates the biphase mark signal and outputs 16-bit data 18D and a sampling frequency timing signal 18C. The data 18D and the signal 18C are converted into analog signals 22L and 22R by the D / A converter 22 and output to output terminals T8 and T9. Therefore, the timing of D / A conversion operates based on the clock 16C reproduced by the bit synchronization circuit 16.

As is clear from the above description, when the switches 13 and 25 are in the open state, the clock that determines this system is the oscillator 9, which causes the bit synchronization circuit 16 to follow and the D / A converter 22 / A conversion timing is determined.

Next, the operation when the switches 13 and 25 are closed will be described. At this time, the switch 11 is the PLL circuit 1
The 0 side and the switches 20 and 21 select the buffer register 19 and the timing circuit 24, respectively. The reference oscillator in this state is the oscillator 23, and the clock output 23C which is the output of the oscillator 23 is transmitted to the PLL circuit 10 via the output terminal T7 and the input terminal T5. The PLL circuit 10 converts the clock output 23C into the reference clock frequency of the CD player unit 14 and applies it to the signal processing circuit 5. Therefore, the transmission rate of the data 12B output from the serial output circuit 12 is synchronized with the oscillator 23. This data 12B is applied to the bit synchronization circuit 16 via the output terminal T3 and the input terminal T6.

The data 18D demodulated by the demodulation circuit 18 is written in the buffer register 19, and the oscillator 23 by the timing circuit 24 is written.
Are generated at the sampling frequency timing. The data read from the buffer register 19 is D /
The data is input to the A converter 22, and the D / A converter 22 converts the data into an analog signal at the timing of the oscillator 23. Therefore, according to the present embodiment, it is possible to eliminate the influence of clock jitter that occurs during data transmission and reproduce a faithful audio signal.

FIG. 2 shows another embodiment of the present invention, which is characterized in that the circuit configuration does not use the buffer register 19 in the first embodiment. 2 that are the same as or similar to those in FIG. 1 indicate the same or equivalent parts.

The sampling frequency timing signal 24C obtained by dividing the output of the oscillator 23 is output to the output terminal T7. The signal 24C is input to the PLL circuit 10 via the input signal T5.

The PLL circuit 10 compares the timing signal 5C of the sampling frequency generated by the signal processing circuit 5 and the sampling frequency timing signal 24C sent from the audio unit 15 in phase to control the VCO. , PLL circuit. The other structure is almost the same as the structure shown in FIG.

Next, the operation of this embodiment will be described. When the switches 13 and 25 are closed, the output clock of the PLL circuit 10 is sent to the signal processing circuit 5. The signal processing circuit 5 generates a sampling frequency timing signal 5C, and the signal 5C is fed back to the PLL circuit 10. Therefore, the signal 5C is synchronized with the phase of the signal 24C applied to the input terminal T5 in the PLL circuit 10.

Therefore, the output phase of the serial output circuit 12 is determined, and the output data timing of the demodulation circuit 18 is also determined.

The D / A converter 22 converts the output data 18D of the demodulation circuit 18 into an analog signal at the timing of the oscillator 23. As a result, a faithful audio signal can be reproduced without being affected by the clock jitter generated during data transmission.

The operation when the switches 13 and 25 are open is the same as that in the first embodiment, and the description thereof is omitted.

FIG. 3 shows a specific example in which the switch 11 shown in FIGS. 1 and 2 can be automatically controlled. In the figure, reference numeral 30 is a level detector for detecting the level of the input terminal T5, other reference numerals have the same functions as those in FIG. 1, and the configuration other than the switch 11 is omitted.

In the configuration of FIGS. 1 and 2, the switch 11 can be controlled freely, but if the clock is not input to the input terminal T5, the PLL circuit 10 operates the player unit 14 with an unstable clock that is free-running. Will be lost.

This specific example solves this problem, and the level detector 30 determines whether or not a signal is applied to the input terminal T5 and controls the switch 11. In this specific example, the switch 11 is not connected to the PLL circuit 10 unless a signal is applied to the input terminal T5. Therefore, it is possible to prevent the CD player unit 14 from operating with an unstable clock.

FIG. 4 shows another specific example of automatically controlling the switch 11 shown in FIG. In the figure, 31 is an edge detection circuit that detects the edge of a signal applied to the input terminal T5 by the output clock of the PLL circuit 10, 32 is a counter that is cleared by the edge detection circuit 31, and counts the clock of the PLL circuit 10, 36
Is a latch circuit for latching the count value, and 33 is a comparison circuit for comparing the value M of the B input with the value of the latch 36 of the A input. Further, 34 is a comparison circuit 33, and A ≠ B
Is an OR circuit for decoding that
Is a monostable multivibrator triggered by.

In operation, the edge of the timing clock of the sampling frequency applied to the input terminal T5 is detected by the edge detection circuit 31, the count value from that edge to the next edge is counted by the counter 32, and held in the latch circuit 36. It
Therefore, if there is an input at the input terminal T5 and the PLL circuit 10 is normally locked, the value of the latch 36 becomes M.

On the other hand, if it is not locked, the values other than M are latched.
Loaded in. Therefore, the comparison circuit 33 and the OR circuit 34 output the H pulse when they are not locked. This allows the monostable multivibrator 35 to
The switch 11 is controlled by giving a hysteresis to a variable value of 36.

According to this example, the switch 11 does not malfunction even if an incorrect signal is input to the input terminal T5.

FIG. 5 is a block diagram showing a specific example of the switch control circuit for preventing the malfunction of the audio section 15 caused by the clock selection switch 25.

In the embodiment of FIG. 2, the switch 25 forces D /
Since the clock for A conversion can be supplied from the oscillator 23, when the CD player unit 14 is operating with its own clock oscillator 9, overflow or lack of data may occur due to the frequency difference between the oscillators 9 and 23. Occurs.

FIG. 5 shows a switch control circuit proposed to prevent this. Reference numeral 50 in the figure indicates the prevention circuit section. The edge detection circuit 40, the counter 41, and the latch circuit 41L are provided to count the time from edge to edge of the sampling frequency timing clock of the output of the demodulation circuit 18 using the output of the oscillator 23. Now, the CD player section 14
Is operating with the oscillator 23, the oscillator 23 and the demodulation circuit 18 are synchronized, so that a constant value M is loaded into the latch 41L.

On the other hand, when the CD player unit is operating with its own oscillator 9, a value other than M is loaded. Therefore, the comparator 42 compares it with the value of M, and decodes the output by the OR circuit 43 to "L" when the CD player section is operating by the oscillator 23, and when the CD player section is operating by the oscillator 9. It becomes H "level. This is made to have hysteresis by the monostable multivibrator 44, and the control signal 25C of the switch 25 and the OR circuit 4
Logical OR with 5.

As a result, even if the switch 25 is turned on and the D / A converter 22 is operated at the timing of the oscillator 23, the switch 21 cannot be controlled unless the CD player unit 14 is operating by the oscillator 23.

Therefore, the CD player unit 14 and the audio unit 15 do not malfunction due to an erroneous operation of the changeover switch. In addition, the output of the OR circuit 45 indicates the clock switching state by the driver 47 and the light emitting element 48.
Even if 25 is turned on, it is possible to grasp the state where the clock cannot be switched. As a result, there is an effect that the user is not confused.

In the first and second embodiments, the switches 11, 20, and 21 are provided for switching in order to achieve compatibility with the conventional device, but the present invention is not limited to this and the signal processing is not limited thereto. Of course, the circuit 5 and the PLL circuit 10, and the D / A conversion circuit 22 and the timing circuit 23 may be fixedly connected.

(Effect of the Invention) According to the present invention, an audio source is provided with an oscillation source serving as a reference, and a signal output from the oscillation source is used as a reference frequency for D /
Since the A conversion is performed, there is an effect that the jitter on the time axis can be eliminated. Also, the audio section
Since it is independent from the CD player unit, it can eliminate disturbances such as digital signal processing and servo circuits, and can reproduce faithful audio signals. In particular, it is possible to prevent deterioration of distortion in the high frequency range of audio performance. The effect is that you can do it.

[Brief description of drawings]

FIG. 1 is a block diagram of a CD player showing one embodiment of the present invention, FIG. 2 is a block diagram of a CD player showing another embodiment of the present invention, and FIGS. 3 and 4 show the present invention. FIG. 5 is a block diagram showing a concrete example of the switching means of the CD player section, and FIG. 5 is a block diagram showing a concrete example of the switching means of the audio section of the present invention. 5 ... Signal processing circuit, 8 ... D / A converter, 10 ... PLL circuit, 12 ... Serial output circuit, 18 ... Demodulation circuit, 22 ...
D / A converter, 23 ... Oscillator, 24 ... Timing circuit

Claims (4)

[Claims] 1. A reproducing means for reproducing a signal recorded on a recording medium to obtain a digital signal, and a converting means for converting an output of the reproducing means into one serial digital data string.
A first for generating a reference clock for the reproduction means and the conversion means,
, A clock reproducing means for receiving the output data of the converting means and reproducing a clock synchronized with the data, a demodulating means for demodulating the received data, and an output data of the demodulating means. Digital audio having analog-to-analog converting means for converting the analog signal into an analog signal, and an analog reproducing section comprising the first clock generating means and the second clock generating means for generating the reference clock of the digital-analog converting means. The reproducing apparatus further comprises a transmitting unit that transmits the clock output from the second clock generating unit to the first clock generating unit of the digital reproducing unit, and the first clock generating unit includes the second clock generating unit. The clock that is in phase with the clock output by the clock generator is output. Digital audio reproducing apparatus according to claim. 2. The digital reproducing section has a third clock generating means for generating a reference clock for the reproducing means and the converting means, and a selecting means for selecting the first generating means and the third clock generating means. On the other hand, on the other hand, the analog reproducing section is provided with a timing signal output from the demodulating means and a selecting means for selecting a signal obtained by dividing the clock output from the second clock generating means. A digital audio reproducing apparatus according to claim 1. 3. The first clock generating means is the second clock generator.
3. A digital audio reproducing apparatus according to claim 1 or 2, wherein the digital audio reproducing apparatus comprises a PLL circuit which receives a clock generated by the clock generating means as an input. 4. The output data of the demodulating means is temporarily stored in a buffer register, and the output data is read by a signal obtained by dividing the clock output from the second clock generating means. A digital audio reproducing apparatus according to claim 1.