JPH0770228B2 - Semiconductor memory write operation control method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write operation control method for a semiconductor memory manufactured as a super integrated circuit, particularly an insulated gate field effect semiconductor memory.

(Prior Art) Currently, there are DRAM and SRAM as volatile memories, and EEPROM and FLASH EEPROM as nonvolatile memories.

Although volatile memories such as DRAM and SRAM can be written and read at high speed, DRAM has drawbacks such as requiring a refresh cycle and a large standby current.

Complementing this is the SRAM, which has the advantage that it can read data faster than the DRAM and consumes less power, but has the drawback that the degree of integration is reduced.

In addition, both RAMs require battery backup during standby, data is lost even in the event of a momentary power failure, etc. Furthermore, battery backup in high and low temperature environments consumes a lot of power and has many problems.

Therefore, EEPROM is a device that complements these drawbacks.
There is a non-volatile memory such as. However, this element cannot be written and erased within the read time, and therefore direct writing and erasing from the CPU is difficult and its application range is limited in device applications.

For this reason, Ramtron Inc. of the United States
At the national sonid state circuit conference, the memory device shown in Fig. 1 was announced.

In this ferroelectric memory cell, the output terminals A and B of two inverter circuits composed of transistors 9, 10, 11, and 12 are connected to the input of one inverter circuit, and the output terminals A and B are word lines. Transfer transistor controlled by 5
Through 7,8 It has the structure of a normal SRAM cell connected to the ferroelectric capacitor 2, and the output terminals A and B are connected via the control transistors 4 and 4'controlled by the control line 3 to the ferroelectric capacitor 2 and
The other electrode is connected to the drive line 1 at one electrode of 2 ', and the data is made nonvolatile by adding two transistors 4, 4'and two ferroelectric capacitors 2, 2'. I suggest you to remember.

Now, looking at the characteristics of the ferroelectric capacitor itself, the charge amount with respect to the voltage has a hysteresis curve as shown in FIG. That is, when the voltage is increased, a rapid increase in the amount of electric charge is observed, and when the voltage exceeds a certain voltage, the amount of increase is constant. Even if this voltage is returned to 0V, the amount of charge does not return to the original state and a certain amount of residual charge is retained.

Then, when the voltage is further lowered, the amount of electric charge is rapidly reduced and the amount of negative electric charge is increased. Further, it has a characteristic of holding a constant negative charge amount when the voltage is returned to 0V.

At present, this ferroelectric thin film PZT (Lead Zirconate Ti
Although a method of performing film formation by sputtering or the like is adopted for tanate), it has a problem that it has a problem of orientation and causes a phenomenon of deterioration of hysteresis.

Therefore, Ramtron, Inc. of the United States has proposed to add the transistors 4 and 4'having control gates to store in the ferroelectric capacitor when the power supply voltage is cut off as described above.

In Fig. 3, the power supply voltage Vcc (reference numeral in the figure) is cut off and the potential is H
FIG. 6 is a timing chart of the control line 3 and the drive line 1 regarding the write timing to the ferroelectric memory when changing from igh (Vcc) to Low (GND).

When the power supply voltage Vcc is cut off and transiently changes from High to Low, when writing "0" of the bit line 6 and "1" of the bit line 6 ', the signal of the control line 3 first has a constant power supply voltage drop. The control transistors 4 and 4'are turned on by switching the control transistors 4 and 4'to High from Low (GND). When the signal on this control line 3 is high, drive line 1 is low (G
When ND) is changed to High, the electric charge of Q (0) is retained in the ferroelectric 2. Then, when the signal of the control line 3 is High and the drive line 1 is changed from High to Low (GND), the electric charge of Q (1) is held in the ferroelectric electric body 2 '.

Therefore, when the power supply voltage Vcc is cut off, the electric charges of Q (0) and Q (1) are held in the ferroelectric capacitors 2 and 2 ', respectively, so that the data "0" and "1" of the nodes A and B are the above-mentioned. It will be written to the memory in the following manner.

On the other hand, when the power is turned on, the nodes A and B are held at Low (GND) level, and then the control line 3 is held at High level and then the drive line 1 is held at High when the power supply voltage becomes a constant level. If so, the ferroelectric capacitor 2
Since the electric charge of Q (0) is held at, the electric charge does not move due to the potential difference of the power supply voltage, and the Low (GND) level is secured.

Next, the electric charge of Q (1) is held in the ferroelectric capacitor 2 ', and when the potential of the power supply voltage is lowered, the electric charge moves in the direction of increasing the electric charge, and the high level is secured.

Therefore, the data "0" and "1" are read to the nodes A and B, and the data before the power is turned off is retained.

(Problems to be Solved by the Invention) The operation principle of the conventional ferroelectric non-volatile memory has been described above. However, the relative dielectric constant of a ferroelectric substance such as PZT is as high as 100 to 150, which is 20% higher than that of a SiO ₂ film. About twice as large.

Therefore, the capacitance connected to the drive line 1 becomes a considerable value, it is quite difficult to drive in the transient state when the power is turned off, and there is a problem that storage in the ferroelectric memory is not performed effectively.

In view of such circumstances, the present invention operates as an SRAM during normal operation, realizes high speed and low power consumption, and performs a write operation to a ferroelectric capacitor when the power supply voltage becomes a certain voltage or less. It is therefore an object of the present invention to provide a write operation control method for a semiconductor memory that prevents data loss.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a pair of inverter circuits each including a plurality of transistors, and a strong circuit arranged between the control line and the drive line corresponding to the circuit. A dielectric capacitor is provided, and both input terminals and output terminals of the inverter circuit are connected to each other, and each of the output terminals is connected to a bit line via a transfer transistor. A write operation control method in a semiconductor memory including a plurality of memory cells, which is connected to one of the electrodes of the capacitor via a control transistor controlled by a control line. After the disconnection, when the power supply voltage becomes a predetermined voltage lower than the normal operating voltage, the voltage drop of this power supply voltage turns the control line to the high level to turn on the control transistor, and before this transistor turns on. The drive line is applied to the intermediate potential of the power supply voltage by the resistance dividing means of the power supply voltage, and when the power supply voltage reaches a low level lower than the predetermined voltage, the operation of writing binary data in the capacitor is executed. It is characterized by doing so.

(Operation) With such a configuration, even a memory cell with a strong dielectric capacitor having a large relative permittivity can be operated as SRAM during normal operation. When writing data of "0" and "1" to the control transistor, turn on the control transistor when the power supply voltage becomes lower than the specified voltage.
The control line goes high. On the other hand, since the drive line is at the intermediate potential of the power supply voltage after the power is turned on, the ferroelectric 2 obtains the electric charge by 1/2 Vcc and produces the remanent polarization Q (0), while the ferroelectric 2'is The charge due to / 2Vcc is obtained and the remanent polarization Q (1) is generated.

Therefore, the charges of Q (0) and Q (1) are secured in the ferroelectric and data of "0" and "1" are written.

(Embodiment) A semiconductor memory write operation control method according to the present invention will be described with reference to the drawings.

FIG. 4 shows a timing chart relating to the method of the present invention. This timing chart shows the relationship between the control line 3 and the drive line 1 regarding the write timing to the ferroelectric memory when the power supply voltage Vcc13 changes from High (Vcc) to Low (GND) after the power is cut off. .

After the power is turned off, when the power supply voltage becomes a predetermined voltage lower than the normal operating voltage, that is, the power supply voltage Vcc13 is high (Vc
c) When changing to Low (GND) transiently, When writing the data of "0" and "1", the control transistors 4, 4'when Vcc falls below a certain predetermined voltage.
Control the control line so that turns on. In this case, set the control line to High (Vcc) level.

As a circuit for turning on the control transistors 4 and 4'when the power supply voltage is lower than a certain level, there is a circuit shown in FIG.

Before the control transistors 4 and 4'are turned on,
The drive line has an intermediate voltage of the power supply voltage Vcc by the method of resistance dividing means.

This resistance division method is, for example, the circuit shown in FIG. 6, and the intermediate potential between the power supply voltage Vcc and the ground voltage GND is GΩ such as P-well or N-well formed on the semiconductor substrate.
It is defined by the resistance division in units.

When the intermediate potential is secured in this way, Q
The charges of (0) and Q (1) are retained,
Data of "0" and "1" is written.

That is, the ferroelectric substance 2 has a potential of Vcc-1 / 2Vcc = 1 / 2Vcc, and as shown in FIG.
You will get (0).

On the contrary, the ferroelectric 2'is GND-1 / 2Vcc = -1 / 2Vcc
Then, the electric potential becomes equal to, and as shown in FIG.

(Effect of the Invention) According to the write operation control method of the semiconductor memory of the present invention, the drive line is applied to the intermediate potential of the power supply voltage by the resistance dividing means before the ON state of the control transistor, and the electric charge is held in the capacitor. , It is not necessary to drive in order to make a pulse within a short time when the power is turned off, and data can be surely written in the ferroelectric capacitor.

[Brief description of drawings]

FIG. 1 is a circuit diagram in which a ferroelectric memory is added to an SRAM cell, FIG. 2 is a voltage-charge hysteresis curve diagram of a ferroelectric substance, FIG. 3 is a timing chart diagram of a conventional control line and a drive line, and FIG. FIG. 5 is a timing chart similar to FIG. 3 according to the present invention, and FIG. 5 is a circuit diagram showing an embodiment in which the control transistor is turned on when the power supply voltage becomes lower than a predetermined voltage during operation of the semiconductor memory. FIG. 6 is a circuit diagram showing a resistance division method for applying an intermediate potential to the drive line. 1 ... Drive line, 2,2 '... Capacitor 3 ... Control line 4,4' ... Control transistor 5 ... Word line, 6 ... Bit line 7,8 …… Transfer transistor 9,10,11,12 …… Transistor

Claims (1)

[Claims] 1. A pair of inverter circuits composed of a plurality of transistors and a ferroelectric capacitor corresponding to the circuit and arranged between a control line and a drive line are provided, and the inverter circuit has both input terminals. The output terminals are connected to each other, and each of the output terminals is connected to the bit line through the transfer transistor. A write operation control method in a semiconductor memory including a plurality of memory cells, which is connected to one of the electrodes of the capacitor via a control transistor controlled by a control line. After the disconnection, when the power supply voltage becomes a predetermined voltage lower than the normal use voltage, the control line is set to the high level by the voltage drop of this power supply voltage to turn on the control transistor, and before the ON state of this transistor. The drive line is applied to the intermediate potential of the power supply voltage by the resistance dividing means of the power supply voltage, and when the power supply voltage reaches a low level lower than the predetermined voltage, the operation of writing binary data in the capacitor is executed. A method characterized by doing so.