JPH0770232B2 - Data writing method - Google Patents

Description

The present invention relates to a data writing method of a semiconductor memory used as, for example, a data memory of an IC card, and more particularly to an automatic page writing method of an EEPROM. .

(Prior Art) Recently, as a semiconductor memory, an EEPROM, which is capable of electrically erasing and rewriting data, has been attracting attention instead of an EPROM. However, the data writing time of EEPROM is
Since it is longer than that of EPROM, various improvements have been made.

In particular, what is remarkable as an improved product is to provide a buffer composed of several bytes of RAM in the EEPROM and write to this buffer within a specific time. Is rewritten to EEPROM. This is the EPROM time to write to the buffer
Since it is about the same as the above, the writing time is apparently shortened.
For this purpose, the memory is divided according to the concept of page, the lower-order bits of the address data supplied to the memory indicate the number of bytes in the page, and the remaining higher-order bytes indicate the number of pages. From this concept, the so-called page writing function is called.

However, conventionally, the specific time is only described in the specification, and the page writing operation to the EEPROM as an external device is designed by the numerical value in the specification. However, depending on the EEPROM, even if the specified time is shortened due to factors such as the writing environment, the external device may recognize that all access data has been written.
Therefore, there is a demand for a method by which an external device can easily identify whether or not the EEPROM is in a data receiving state.

(Problems to be Solved by the Invention) The present invention has been made in view of the above-described demands. When writing a page, data reception is in the waiting state for the first byte of data or the data of the second and subsequent bytes. It is an object of the present invention to provide a data writing method capable of easily identifying from the outside whether it is in a waiting state or in a data writing operation in which data cannot be accepted.

[Structure of the Invention] (Means for Solving Problems) The present invention relates to a memory divided into a bit string of at least 1 bit as an access unit of a 2 ⁿ (n is a positive integer) string, and Data holding means for externally receiving and holding 2 ^n- column data to be written, and writing means for writing the data held in the data holding means in a predetermined divided area of the memory, When writing the data, the data holding method is such that after writing the data of 2 ⁿ columns or less to the data holding means, the writing means writes the data to the predetermined divided area of the memory. A counter that counts the amount of data, and causes the writing means to perform the writing operation when a predetermined amount of data is counted by this counter. In either case, whether the data reception by the data holding means is in the waiting state for the first byte data or the second byte or later data based on the count value of the counter, or the writing operation by the writing means is performed. It is determined whether or not the data reception is impossible, and whether the data reception by the data holding means is in the waiting state for the first byte data or not 2
It is characterized by comprising control means for outputting to the outside an identification signal capable of identifying whether each is in a waiting state for data after the byte byte or in a state in which data cannot be received during the writing operation by the writing means. There is.

(Operation) At the time of page writing, the amount of data received by the data holding means is counted, and when the predetermined amount of data is counted, the writing operation is performed by the writing means, and the data by the data holding means is based on the count value. Is the reception of 1st byte data waiting state? 2
It is determined whether the data is waiting for the data on and after the byte or the data is not being received by the writing means and the data holding means waits for the first byte. Is in a waiting state for the data of the second byte or later, or
By providing a control means for outputting to the outside an identification signal capable of identifying whether each of the writing operations by the writing means is in the data unacceptable state, the acceptance of the data is in the waiting state for the first byte or in the two bytes. It is possible to easily identify from the outside whether the data is in a waiting state after the eyes or is in a data writing operation and cannot accept data. Therefore, an efficient write sequence can be provided as an external device.

In addition, by making it possible to identify whether the first byte of data is in a waiting state or the second and subsequent bytes of data are in a waiting state, it is possible to determine whether or not the first byte of data has been normally received from the outside. Since it is possible to easily identify, if there is an abnormality in the exchange of data with the external device, the external device can identify the occurrence of the abnormality at an early stage.

(Example) Hereinafter, one example of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit configuration of, for example, a 64 kilobit (8192 words × 8 bits) EEPROM. That is,
Reference numeral 1 denotes a row address latch, which is a control circuit 1 which will be described later with the higher-order 8-bit data A _{12 to} A ₅ of the address data A _{12 to} A _0.
Latch by the signal d from 0. 2 is a row address decoder to generate a row select signal a by decoding the address data A ₁₂ to A ₅ latched in the row address latch 1. 3 is a memory cell array of 8192 words × 8 bits. A column address buffer 4 holds lower 5 bits of data A _{4 to} A ₀ of the address data A _{12 to} A ₀ . A column address decoder 5 decodes address data A _{4 to} A ₀ output from the column address buffer 4 by a signal e from a control circuit 10 described later to generate column selection signals b and c. An access identification information latch 6 is a signal c from the column address decoder 5.
The access identification information is latched by. Reference numeral 7 is an input data latch, which is input from an input / output buffer 8 described later.
The bit data is latched by the signal c from the column address decoder 5. Reference numeral 8 denotes an input / output buffer, which is 8-bit input / output data according to a signal h from a control circuit 10 described later.
Holds D _{7 to} D ₀ . An internal write controller 9 performs an internal write process in response to a signal f from a control circuit 10 described later. Reference numeral 10 is a control circuit, which controls the writing and reading of the EEPROM. Control circuit 10 from outside
The ▼ signal (write enable signal), ▲ ▼ signal (chip enable signal), and ▲ ▼ signal (output enable signal) are supplied, and the WRB signal and RRB signal as write status signals, which will be described later, are output to the outside. To do.

The external write timing of the EEPROM thus configured is shown in FIG. In steady state, WRB signal and RRB
Both signals are at "H" level. Here, the WRB signal is "L" when the first byte of the write byte is accessed.
The level becomes high, and when the subsequent internal write processing is completed, the level becomes high again. The control circuit 10 includes a timer and a counter. The timer defines the acceptance period of the next byte input after the write byte is input, and the counter counts how many write bytes are accepted. In this embodiment, for example, 32
The acceptance process ends when the byte is accepted. In addition, the timer overflows 50 μs after resetting. That is, it took more than 50 μs to access one byte and the next byte, or each access was within 50 μs and 32
When the byte is accessed, the write byte acceptance process ends. The counting up of the counter and the resetting of the timer are performed by the input acceptance timer reset signal (pulse) generated by the writing operation. The RRB signal informs the outside of whether or not the acceptance processing is continuing. The RRB signal is set to "L" level when the acceptance processing is completed, and is set to "H" level again when the subsequent internal writing processing is completed.

That is, if both the WRB signal and the RRB signal are at "H" level, it is in the waiting state of the first byte as a write byte, and if the WRB signal is at "L" level and the RRB signal is at "H" level, Indicates that the first byte has been accepted and the subsequent bytes are being accepted. If both the WRB signal and the RRB signal are at "L" level, it indicates that the write byte acceptance is prohibited and the internal write processing is being performed. As a result, the above three states can be easily identified as an external device.

Now, when writing is performed with both the WRB signal and the RRB signal in the "H" level state, a signal (signal d in FIG. 1) obtained by ANDing the ▲ ▼ signal and the ▲ ▼ signal at this time
Latching the row address latch 1 to address data A ₁₂ to A ₅ as row address. At this time, set the WRB signal to "L"
Down to the level. At the same time, the column address decoder 5
Is to decode the signal c by decoding the address data A _{4 to} A ₀ input from the column address buffer 4 with a signal (signal e in FIG. 1) obtained by ANDing the ▲ ▼ and ▲ ▼ signals. To generate. Here, the access identification information latch 6 is composed of 32 1-bit latches, is reset in the steady state, and the latch selected by the signal c is set. The input data latch 7 is composed of a latch of 8 bits × 32 words, and each word is a signal c.
The latch selected at this time latches the data input via the input / output buffer 8. Namely, thereby the data value sequence to A ₄ to A ₀ is be made randomly stored in the corresponding word, also either stored in the access identification information latch 6 words data is stored is none It will be.

In the example of FIG. 2, the value xx is latched in the row address latch 1 at the end of the acceptance period, and in the input data latch 7, the data a and the third 8 bits are stored in the first 8-bit latch. Data d, fourth in the latch
The data c is latched in the eighth 8-bit latch and the data b is latched in the seventh 8-bit latch. In the access identification information latch 6, the first, the third, the fourth, and the seventh are latched.
Bits are set, and the rest are all reset.

Next, the internal write processing will be described with reference to the flowchart shown in FIG. First, the trace of the acceptance period,
Set the internal write column address to "0". This is because there is a column address generator in the internal write controller 9, and this output has a value from "00" to "1F" for the internal write column address shown in FIG. Then, the column selection signal i and the signals j, k are generated by decoding this output.

Next, the internal write controller 9 selects the corresponding latch in the access identification information latch 6 by the generated signal j (that is, refers to the access identification information corresponding to the column address), and determines whether it is set or not. To determine. If it is not set (that is, "0"), writing to the memory cell array 3 is not performed, and the address is incremented by 1 by the column address generator.
If it is set (that is, "1"), the generated signal k selects the corresponding word in the input data latch 7 (that is, the word of the input data latch 7 corresponding to the column address is selected). , The data in the word is supplied to the memory cell array 3, and at the same time, the column selection signal i
The memory cell to be written is specified by the (column address) and the row selection signal a (row address), and the write enable signal 1 is given to the memory cell array 3. When receiving the write enable signal l, the memory cell array 3 stores the data previously supplied to the memory cell (8 bits) designated by the address data. Then, the internal write controller 9 recognizes that the data has been written in the memory cell array 3, and increments the address by 1 by the column address generator.

However, it is determined whether or not the address value before incrementing by one column address is in the "1F _H", indicating that the write has been completed to the control circuit 10 if made by the signal m. When the control circuit 10 recognizes that the writing is completed by the signal m, it sets the WRB signal and the RRB signal to the “H” level, resets all the latches of the access identification information latch 6 by the signal g, and operates as a memory. Return to steady state.

In addition, during the internal writing process period in FIG.
The signal, ▲ ▼ signal and ▲ ▼ signal are invalid.

Next, the read operation is a read signal input during the read permission period (a period other than the internal write processing period in FIG. 2). It is performed in conjunction with the ▲ ▼ signal and the ▲ ▼ signal. At this time, when the control circuit 10 recognizes that it is a read operation, the address data A _{12 to} A ₅ are converted into the row selection signal a by the row address decoder 2 via the row address latch 1 and the address data A _{4 to} A _{5 are} generated. ₀ is the column address decoder 5 via the column address buffer 4
Then, the data of the memory cell (8 bits) designated by the row selection signal a and the column selection signal b is read out and stored in the input / output buffer 8 by the signal h.

In this way, the identification signal (WRB signal, R
RB signal) to the outside, when the first byte is accepted for page writing, when a predetermined time has expired (when the data acceptance process has finished), and when the internal write process has finished. At the first byte by changing the output level of the identification signal,
Three states can be easily identified from the outside, that is, the state where the second and subsequent bytes are being accepted, and the write byte acceptance prohibited state (the state where the internal write process is being performed). Therefore, an efficient writing sequence can be provided as an external device.

The identification signal (WRB signal, RRB signal) makes it possible to identify whether the first byte is in the waiting state or the second and subsequent bytes are in the waiting state. Since it is possible to easily identify whether or not the data has been normally received, if the data exchange with the external device is abnormal, the external device can identify the occurrence of the abnormality at an early stage.

[Effects of the Invention] As described in detail above, according to the present invention, whether data reception is in the waiting state of the first byte of data or in the waiting state of the second and subsequent bytes at the time of page writing, Alternatively, it is possible to provide a data writing method by which it is possible to easily identify from the outside whether or not the data cannot be received during the data writing operation.

Further, according to the present invention, it is possible to distinguish whether the first byte data is in a waiting state or the second and subsequent bytes are in a waiting state. Since it is possible to easily identify whether or not the data has been received, it is possible to provide a data writing method that enables the external device to identify the occurrence of the abnormality at an early stage when there is an abnormality in the data exchange with the external device.

[Brief description of drawings]

FIG. 1 is a diagram for explaining one embodiment of the present invention. FIG. 1 is a block diagram showing a circuit configuration of an EEPROM, FIG. 2 is a diagram showing a data write timing, and FIG. 3 is a diagram showing an internal write process. It is a flowchart. 1 ... Row address latch, 2 ... Row address decoder, 3 ... Memory cell array, 4 ... Column address buffer, 5 ... Column address decoder, 6 ... Access identification information latch, 7 ... Input data latch, 8 ...... Input / output buffer, 9 ... Internal write controller, 10 ...
Control circuit.

Claims (1)

[Claims] 1. A memory which is divided into a bit string consisting of at least 1 bit, which is an access unit of 2 ⁿ (n is a positive integer) columns, and 2 ⁿ columns of data to be written in this memory are externally received. It has a data holding means for holding and a writing means for writing the data held in the data holding means in a predetermined divided area of the memory, and when writing data to the memory, the data of 2 ⁿ columns or less is written. A data writing method of writing data to a predetermined divided area of the memory by the writing means after receiving the data by the data holding means, and having a counter for counting the amount of data received by the data holding means. When the predetermined amount of data is counted by the write means, the write operation is performed, and based on the count value of the counter. The reception of data by the data holding means is in the waiting state for the data of the first byte, the waiting state of the data of the second byte or later, or the writing operation by the writing means is in the unacceptable state. Whether the data is received by the data holding means in the waiting state for the first byte of data or the waiting state of the second and subsequent bytes, or
A data writing system characterized by comprising control means for outputting to the outside an identification signal capable of identifying whether each of the writing operations by the writing means is in a data unacceptable state.