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JPH0770535B2 - Method for manufacturing semiconductor device - Google Patents
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JPH0770535B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JPH0770535B2
JPH0770535B2 JP61147049A JP14704986A JPH0770535B2 JP H0770535 B2 JPH0770535 B2 JP H0770535B2 JP 61147049 A JP61147049 A JP 61147049A JP 14704986 A JP14704986 A JP 14704986A JP H0770535 B2 JPH0770535 B2 JP H0770535B2
Authority
JP
Japan
Prior art keywords
film
sio
present
treatment
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61147049A
Other languages
Japanese (ja)
Other versions
JPS634624A (en
Inventor
正治 浜崎
和夫 西山
博士 山本
和浩 田島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP61147049A priority Critical patent/JPH0770535B2/en
Publication of JPS634624A publication Critical patent/JPS634624A/en
Publication of JPH0770535B2 publication Critical patent/JPH0770535B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関するものである。本
発明は例えばメモリー装置の製造に適用することがで
き、その場合特に最近のMOSメモリー(DRAM,SRAM等)で
要求されている薄いSiO2膜の特性を著しく改善できる。
The present invention relates to a method for manufacturing a semiconductor device. INDUSTRIAL APPLICABILITY The present invention can be applied to, for example, manufacturing of a memory device, and in that case, the characteristics of a thin SiO 2 film which is required particularly in a recent MOS memory (DRAM, SRAM, etc.) can be remarkably improved.

〔発明の概要〕 本発明は、半導体装置の製造方法において、半導体基板
を酸化雰囲気中で処理することにより半導体材料と雰囲
気中の酸化成分とを反応させて半導体基板上に酸化膜を
形成し、その後IR加熱法により加熱処理を施すことによ
り、半導体基板材料と酸化膜との間の未結合種を低減し
て、界面特性を改善することにより、短時間の加熱によ
って膜特性を著しく改良し得るようにしたものである。
SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device, wherein a semiconductor substrate is treated in an oxidizing atmosphere to react a semiconductor material with an oxidizing component in the atmosphere to form an oxide film on the semiconductor substrate, After that, by performing a heat treatment by an IR heating method, the unbonded species between the semiconductor substrate material and the oxide film can be reduced, and the interface characteristics can be improved, whereby the film characteristics can be significantly improved by heating for a short time. It was done like this.

〔従来の技術〕[Conventional technology]

最近の半導体装置、例えばMOSメモリーは微細化が進
み、スケーリング則に従ってゲート酸化膜等は極めて薄
くなって来ている。
Recent semiconductor devices, such as MOS memories, have been miniaturized, and gate oxide films and the like have become extremely thin according to scaling rules.

例えば256KDRAMでの容量酸化膜厚は100〜120Åであり、
1MbitDRAMでは80〜100Å程度の薄膜が望まれる。SRAMセ
ルでの酸化膜も同様であり、256KSRAMで200Å、1MbitSR
AMでは150Å以下が要求される。
For example, the capacity oxide film thickness in 256K DRAM is 100-120Å,
For 1Mbit DRAM, a thin film of about 80-100Å is desired. The same applies to the oxide film in SRAM cells: 256K SRAM with 200Å, 1MbitSR
AM requires less than 150Å.

一方この様な薄いSiO2膜では耐圧の確保が極めて重要で
あり、またSi表面のクリーニング処理と共にSiO2/Si界
面の表面準位の低減も重要である。
On the other hand, in such a thin SiO 2 film, it is extremely important to secure the breakdown voltage, and it is also important to reduce the surface level of the SiO 2 / Si interface together with the cleaning treatment of the Si surface.

即ち薄いSiO2膜を形成するには通常900℃前後の酸化炉
や酸素、窒素混合ガス(O2+N2)キャリアーを用いた実
効的酸素分圧を低くした低圧酸化法等によるが、これら
の酸化法では酸化膜の緻密性に問題があり、耐圧低下や
界面準位の増加が懸念される。
That is, a thin SiO 2 film is usually formed by an oxidation furnace at about 900 ° C. or a low pressure oxidation method using an oxygen / nitrogen mixed gas (O 2 + N 2 ) carrier with a low effective oxygen partial pressure. The oxidation method has a problem in the denseness of the oxide film, and there is a concern that the breakdown voltage may decrease and the interface state may increase.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述したように、従来より薄いSiO2膜形成のために、低
温・低圧酸化法等が検討されているが、この方法により
得られた膜はSiO2/Si界面にSiOx結合や未結合のSi原子
が存在し、これらが界面準位の増加、耐圧劣化の要因と
なり得ると言われている。
As described above, a low-temperature low-pressure oxidation method or the like has been studied to form a thinner SiO 2 film than before, but the film obtained by this method has no SiO x bond or unbonded at the SiO 2 / Si interface. It is said that there are Si atoms, and these can cause an increase in the interface state and a deterioration in breakdown voltage.

また、高温処理によって膜特性の改善は図れるが、従来
の熱処理では処理時間が長い為に下地接合形状が変化し
三次元素子や微細MOS構造には適さない。
Further, although the film characteristics can be improved by the high temperature treatment, the conventional heat treatment is not suitable for a three-dimensional element or a fine MOS structure because the underlying bonding shape changes due to the long treatment time.

本発明は前述した問題点を改善すべく高温、短時間の制
御性の極めてすぐれたIRアニール炉を用いてSiO2膜の特
性を改善することを目的とする。
It is an object of the present invention to improve the characteristics of the SiO 2 film by using an IR annealing furnace which has excellent controllability at high temperature for a short time in order to solve the above problems.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、半導体基板を酸化雰囲気中で処理すること
により半導体材料と雰囲気中の酸化成分とを反応させて
半導体基板上に酸化膜を形成する工程と、その後IR加熱
法により加熱処理を施すことにより、前記半導体基板材
料と酸化膜との間の未結合種を低減して、界面特性を改
善する工程とを有する半導体装置の製造方法によって、
達成される。IR加熱は短時間でよい。本発明でいうIR加
熱とは、ハロゲンランプ光等による加熱の他、直接試料
に照射されるレーザー光による該試料の加熱なども含ま
れる。
The above-mentioned purpose is a step of reacting a semiconductor material with an oxidizing component in the atmosphere by treating the semiconductor substrate in an oxidizing atmosphere to form an oxide film on the semiconductor substrate, and then performing heat treatment by an IR heating method. By reducing unbonded species between the semiconductor substrate material and the oxide film, and improving the interface characteristics, by a method for manufacturing a semiconductor device,
To be achieved. IR heating should be short. The IR heating referred to in the present invention includes not only heating by halogen lamp light or the like, but also heating of the sample by laser light directly irradiated on the sample.

本発明の構成を具体的に略述すると以下の様である。即
ち例えば通常の酸化法により酸化膜成長した半導体ウェ
ハーに対し、高出力のハロゲンランプ光等をウェハーに
均一に照射し、瞬間的に加熱するように構成できる。
The structure of the present invention is specifically described as follows. That is, for example, a semiconductor wafer on which an oxide film has been grown by a normal oxidation method can be uniformly irradiated with high-output halogen lamp light or the like, and heated instantaneously.

〔作用〕[Action]

本発明において、例えばSiO2膜成長後、高温のIR加熱を
施すことにより、SiO2−Si界面の未結合Si−Oボンドを
十分なSiO2結合とすることができ、これにより界面特性
が改善された半導体装置を得ることができる。また、こ
のIR加熱は短時間で行えるので、これにより、例えば三
次元素子や微細MOS等で問題となる下地接合形状の変化
による特性劣化が防止された。
In the present invention, for example, by performing IR heating at a high temperature after the growth of the SiO 2 film, the unbonded Si—O bond at the SiO 2 —Si interface can be made into a sufficient SiO 2 bond, thereby improving the interface characteristics. The obtained semiconductor device can be obtained. Further, since this IR heating can be performed in a short time, the characteristic deterioration due to the change of the underlying bonding shape, which is a problem in a three-dimensional element or a fine MOS, can be prevented.

〔実施例〕〔Example〕

以下に本発明の実施例を詳述する。なお、当然のことな
がら本発明は以下述べる実施例に限定されるものではな
い。
Examples of the present invention will be described in detail below. Needless to say, the present invention is not limited to the examples described below.

実施例1 本実施例においては、実験サンプルとしてCZ(100)nty
pe2〜3ohm−cmを用い、これに1100℃,O2+HCl(1%)
の雰囲気中でゲート酸化膜(SiO2)を900Å成長させ
た。次に、SiO2膜のPOA(Post−Oxidation−Anneal)処
理としてN2雰囲気中で1000〜1150℃、1秒〜2分のIRア
ニール(ここではハロゲンランプ加熱)処理を施した。
この後Al蒸着、メタルシンター(400℃、60分)を行
い、MOSキャパシターを作成した。
Example 1 In this example, CZ (100) nty was used as an experimental sample.
pe2 ~ 3ohm-cm is used, and this is 1100 ℃, O 2 + HCl (1%)
A gate oxide film (SiO 2 ) was grown to 900 Å in the atmosphere. Next, as a POA (Post-Oxidation-Anneal) treatment of the SiO 2 film, an IR annealing (here, halogen lamp heating) treatment was performed at 1000 to 1150 ° C. for 1 second to 2 minutes in an N 2 atmosphere.
After that, Al vapor deposition and metal sintering (400 ° C., 60 minutes) were performed to create a MOS capacitor.

第1図に、IRアニール処理温度がそれぞれ1000℃(図
中、線IIIで示す)、1100℃(同線Iで示す)、1150℃
(同、線IIで示す)における処理時間と表面電荷Nss(cm
-2exv-1)の関係を示す。
In Fig. 1, the IR annealing temperature is 1000 ° C (indicated by line III in the figure), 1100 ° C (indicated by line I), and 1150 ° C, respectively.
Treatment time and surface charge Nss (cm)
-2 ex v-1 ).

第1図から明らかなように、線I及び線IIで示した1100
℃及び1150℃のIRアニール処理を施した本発明によるサ
ンプルのNss値は、線IIIで示した1000℃処理サンプルの
Nss値よりも低くより優れた界面特性を有することがわ
かる。また1100℃以上のIRアニール処理を施した本発明
によるサンプルのNss値は、瞬間的に0.6〜1×109cm-2e
v-1となり、処理時間0で示されるPOA処理無しのサンプ
ル(Nss=5.9×109cm-2ev-1)と比較して1/5〜1/10に低
減されていることがわかる。
As is clear from FIG. 1, 1100 shown in lines I and II
The Nss value of the sample according to the present invention which has been subjected to the IR annealing treatment of 1 ° C. and 1150 ° C. is the same as that of the 1000 ° C.-treated sample shown by line III
It can be seen that it has lower interfacial properties than the Nss value. Further, the Nss value of the sample according to the present invention which has been subjected to the IR annealing treatment at 1100 ° C. or higher is instantaneously 0.6 to 1 × 10 9 cm −2 e
It is v −1 , which is 1/5 to 1/10 of that of the sample without POA treatment (Nss = 5.9 × 10 9 cm −2 ev −1 ) indicated by the treatment time of 0.

第2図は上述したと同様に成長させたSiO2膜のPOA処理
をウェットO2(図中、線VIで示した)及びドライO
2(同、線Vで示した)の雰囲気中、1000℃の電気炉で
行った比較例であるが1×109cm-2ev-1のNssを得るには
60分以上を要しており、この条件では三次元素子接合や
微細MOSでのウェル層、チャネルストップ領域等、ゲー
ト酸化膜成長時にすでに形成されている接合は大きく再
分布してしまい、これに比べて第1図における線I及び
線IIで示した本発明によるサンプルは瞬間的にNss値が
1×10-9cm-2ev-1以下に低下し、短時間のIRアニール処
理による本発明によれば膜特性が著しく改善されること
が明らかである。
FIG. 2 shows the POA treatment of the SiO 2 film grown in the same manner as described above for wet O 2 (indicated by line VI in the figure) and dry O 2
2 is a comparative example performed in an electric furnace at 1000 ° C. in the atmosphere of 2 (shown by the line V), but to obtain Nss of 1 × 10 9 cm -2 ev -1
It takes more than 60 minutes, and under this condition, the junctions already formed during the gate oxide film growth such as the three-dimensional element junction, the well layer in the fine MOS, the channel stop region, etc. are largely redistributed. On the other hand, the samples according to the present invention shown by lines I and II in FIG. 1 instantaneously have an Nss value of 1 × 10 −9 cm −2 ev −1 or less, and the sample according to the present invention by a short time IR annealing treatment. It is clear that the film characteristics are remarkably improved by the method.

実施例2 実施例1と同じCZ(100)ntype2〜3ohm−cmのSi基板を
用い、約150Åの薄いSiO2膜を形成した。その後N2雰囲
気中で1100℃、10秒のIRアニールによるPOA処理を行っ
た場合の耐圧分布を第3図に示した。また比較例とし
て、同様のSiO2膜を900℃スチーム処理したものの耐圧
分布を第4図に示した。第3図及び第4図はともに横軸
に膜破壊のためにかけた電場、縦軸に破壊割合をとって
いる。第3図に示される本発明による試料は、図中
(イ)で示される破壊電界場9〜10MV/cm付近で集中的
に膜破壊が起きており、第4図に示される比較試料の図
中(ロ)で示される8.5〜9.5MV/cmに比べ、高電界場側
に移動していることがわかる。また、本発明によるIRア
ニール処理したものの方が耐圧分布の集中性がみられ、
ウェハの面内均一性が向上していることがわかる。
Example 2 Using the same CZ (100) ntype 2 to 3 ohm-cm Si substrate as in Example 1, a thin SiO 2 film of about 150 Å was formed. FIG. 3 shows the breakdown voltage distribution when POA treatment was performed by IR annealing at 1100 ° C. for 10 seconds in N 2 atmosphere. As a comparative example, FIG. 4 shows the breakdown voltage distribution of a similar SiO 2 film steam-treated at 900 ° C. In both FIG. 3 and FIG. 4, the horizontal axis represents the electric field applied for film breakdown, and the vertical axis represents the breakdown rate. In the sample according to the present invention shown in FIG. 3, film breakdown occurs intensively in the vicinity of the breakdown electric field field of 9 to 10 MV / cm shown in (a) in the figure, and the figure of the comparative sample shown in FIG. Compared to the 8.5-9.5 MV / cm shown in the middle (b), it can be seen that it is moving to the high electric field side. Further, the IR annealing treatment according to the present invention is more concentrated in the breakdown voltage distribution,
It can be seen that the in-plane uniformity of the wafer is improved.

なお、上記IRアニール処理の雰囲気はN2中の他、O2中、
N2+O2中及びAr中等で行うことができる。また、IR加熱
は、高出力のハロゲンランプ光の他に9−10μm波長CO
2レーザー光照射によってSi−Oの固有吸収ピークとマ
ッチングさせSiO2/Si界面を瞬間的に加熱しても良い。
The atmosphere of the IR annealing treatment is in N 2 as well as in O 2 .
It can be performed in N 2 + O 2 or Ar. In addition, IR heating uses high-output halogen lamp light and CO of 9-10 μm wavelength.
2 The SiO 2 / Si interface may be momentarily heated by being matched with the intrinsic absorption peak of Si—O by laser light irradiation.

〔発明の効果〕〔The invention's effect〕

上述したように、本発明によれば、高温、短時間の制御
性の極めてすぐれたIRアニール炉を用いてPOA処理する
ことにより、下地接合を変化する事なくSiO2膜の特性の
改善が達せられる。
As described above, according to the present invention, the POA treatment is performed using an IR annealing furnace that has excellent controllability at high temperature and for a short time, so that the characteristics of the SiO 2 film can be improved without changing the underlying bond. To be

【図面の簡単な説明】[Brief description of drawings]

第1図は、本発明に係る実施例におけるIRアニール処理
時間とNssとの関係を示す図である。第2図は比較例のP
OA処理時間とNssとの関係を示す図である。第3図は本
発明にかかる実施例におけるIRアニール処理試料の耐圧
分布を示す図であり、第4図は比較例の耐圧分布を示す
図である。 I……1100℃でIRアニール処理した試料 II……1150℃でIRアニール処理した試料 III……1000℃でIRアニール処理した試料 IV……ウェットO2中でPOA処理した試料 V……ドライO2中でPAO処理した試料 (イ)……本発明による試料の集中膜破壊部分 (ロ)……比較試料の集中膜破壊部分
FIG. 1 is a diagram showing the relationship between the IR annealing treatment time and Nss in the example according to the present invention. Fig. 2 shows P of the comparative example
It is a figure which shows the relationship between OA processing time and Nss. FIG. 3 is a diagram showing the withstand voltage distribution of the IR annealing sample in the example according to the present invention, and FIG. 4 is a diagram showing the withstand voltage distribution of the comparative example. I …… Samples IR-annealed at 1100 ℃ II …… Samples IR-annealed at 1150 ℃ III …… Samples IR-annealed at 1000 ℃ IV …… Samples POA-treated in wet O 2 V …… Dry O Sample subjected to PAO treatment in 2 (a) …… Concentrated film destruction part of the sample according to the present invention (b) …… Concentrated film destruction part of comparative sample

フロントページの続き (72)発明者 田島 和浩 東京都品川区北品川6丁目7番35号 ソニ ー株式会社内 (56)参考文献 特開 昭60−12737(JP,A)Front page continuation (72) Inventor Kazuhiro Tajima 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) Reference JP-A-60-12737 (JP, A)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板を酸化雰囲気中で処理すること
により半導体材料と雰囲気中の酸化成分とを反応させて
半導体基板上に酸化膜を形成する工程と、 その後IR加熱法により加熱処理を施すことにより、前記
半導体基板材料と酸化膜との間の未結合種を低減して、
界面特性を改善する工程と を有する半導体装置の製造方法。
1. A step of forming a oxide film on a semiconductor substrate by reacting a semiconductor material with an oxidizing component in the atmosphere by treating the semiconductor substrate in an oxidizing atmosphere, and then performing heat treatment by an IR heating method. This reduces unbonded species between the semiconductor substrate material and the oxide film,
And a step of improving interface characteristics.
JP61147049A 1986-06-25 1986-06-25 Method for manufacturing semiconductor device Expired - Lifetime JPH0770535B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61147049A JPH0770535B2 (en) 1986-06-25 1986-06-25 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61147049A JPH0770535B2 (en) 1986-06-25 1986-06-25 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS634624A JPS634624A (en) 1988-01-09
JPH0770535B2 true JPH0770535B2 (en) 1995-07-31

Family

ID=15421343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61147049A Expired - Lifetime JPH0770535B2 (en) 1986-06-25 1986-06-25 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0770535B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02248046A (en) * 1989-03-22 1990-10-03 Nec Corp Formation of sio2 film
JPH02248047A (en) * 1989-03-22 1990-10-03 Nec Corp Formation of sio2 film
JPH02248045A (en) * 1989-03-22 1990-10-03 Nec Corp Formation of sio2 film
KR100537554B1 (en) * 2004-02-23 2005-12-16 주식회사 하이닉스반도체 Method of manufacturing oxide film for semiconductor device
JP5183969B2 (en) * 2007-05-29 2013-04-17 信越半導体株式会社 Method for forming silicon oxide film on SOI wafer
WO2010033469A2 (en) * 2008-09-16 2010-03-25 Tokyo Electron Limited Dielectric material treatment saystem and method of operating
US8895942B2 (en) 2008-09-16 2014-11-25 Tokyo Electron Limited Dielectric treatment module using scanning IR radiation source

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012737A (en) * 1983-07-01 1985-01-23 Agency Of Ind Science & Technol Manufature of silicon nitride film
JPS62282430A (en) * 1986-05-30 1987-12-08 Citizen Watch Co Ltd Formation of soi element

Also Published As

Publication number Publication date
JPS634624A (en) 1988-01-09

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