JPH0770557B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bonding pad configuration method capable of improving the efficiency of a performance test of a semiconductor chip in a wafer state.

[Prior Art] Conventionally, a plastic mold package has been used as a package of a large scale integrated circuit (LSI) or the like. There is only one bonding pad for the same signal on the semiconductor chip.
Since there is only one semiconductor chip, a plurality of bonding pads for each signal are usually provided on the periphery of the semiconductor chip in the longitudinal or lateral direction so that the semiconductor chip can be enclosed in a package.

FIG. 3 is a plan view showing a conventional structure in which a semiconductor chip having bonding pads arranged therein is enclosed in a plastic mold package. Explaining the structure of this device, a semiconductor chip 1 incorporating an integrated circuit for a 256 Kbit dynamic RAM is enclosed in a plastic mold package 4. AO signal bonding pads 110a are arranged on the semiconductor chip 1 in the longitudinal direction, and A2 signal bonding pads 11b and A1 signal bonding pads 11c are arranged on the semiconductor chip 1 in the lateral direction. It is arranged at intervals. In addition, the plastic mold package 4 encloses the semiconductor chip 1 so that the A0 signal terminals 5a, A2 signal terminals 5b, A1.
Signal terminals 5c are provided at intervals. A0
The signal bonding pad 110a and the A0 signal terminal 5a are bonded by a bonding wire 60a, the A2 signal bonding pad 11b and the A2 signal terminal 5b are bonded by a bonding wire 6b, and the A1 signal bonding pad 11c and the A1 signal terminal 5 are bonded.
It is bonded to c by a bonding wire 6c. The A0 signal terminal 5a, the A2 signal terminal 5b, and the A1 signal terminal 5c are the 5th, 6th, and 7th pins (not shown) for signal input / output exposed on the outer surface of the package, respectively. It is connected to the. Here, and in the figure represent pin numbers.

As described above, the A0 signal bonding pad 110a is arranged in the peripheral portion of the semiconductor chip 1 in the longitudinal direction.
The signal bonding pad 110a is arranged at the left end of the peripheral portion in the lateral direction on the semiconductor chip 1, and this bonding pad (dotted rectangle in the figure) and the A0 signal terminal 5a are bonded by the bonding wire 6a. This is because the bonding wire 6a traverses the edge portion on the semiconductor chip 1 over a long range, and the bonding wire 6a contacts the edge portion on the semiconductor chip 1 during molding.

[Problems to be Solved by the Invention] In a performance test of a conventional semiconductor chip, a plurality of semiconductor chips are tested in parallel in a wafer state (a state before being divided into semiconductor chips by dicing).

FIG. 4A is a diagram showing a state of a performance test of a semiconductor chip in a wafer state in which bonding pads are arranged only on the peripheral portion in the lateral direction on the semiconductor chip. In the figure, the wafer 10 includes semiconductor chips 1, 2, 3, etc.
1, 32, 33, etc. represent dicing lines. For example, bonding pads 11a, 11b, 11c ... 11n and 12a, 12b, 12c ... 12n are arranged at intervals in the lateral direction on the semiconductor chip 1 so as to be aligned with each other. Similarly, for other semiconductor chips, a plurality of bonding pads are arranged. The probe card 7 has a window 71,
Test needles 13a, 13b, 13c… 13n and 14a, 14 on the periphery of 71
b, 14c ... 14n and the like are provided at intervals from each other. At the time of performance test of the semiconductor chips 1, 2, 3, etc., the probe card 7 is arranged on the upper part of the wafer 10, and the bonding pads 11a, 11b, 11c ... 11n and 12a, 12b, 12c ... 13c ... 13n and 14a, 14
b, 14c ... 14n, etc. are applied to perform performance test.

FIG. 4B is a diagram showing a state of a performance test of a semiconductor chip in a wafer state when bonding pads are arranged on peripheral portions in the longitudinal and lateral directions on the semiconductor chip. In the figure, for example, the bonding pads 110a, 120
n and 210a, 220n, etc. are each semiconductor chip in order to optimize the layout of bonding pads when bonding wires.
It is arranged at the peripheral portion in the longitudinal direction such as 1, 2, and 3. For this reason, the test needles 130a, 140n and 2 applied to these bonding pads during the performance test of the semiconductor chips 1, 2, 3 etc.
The length of 30a, 240n, etc. becomes abnormally long and the needle tip position shifts.As a result, it is practically impossible to perform performance tests on the bonding pads arranged in the peripheral portion of the semiconductor chip in the longitudinal direction. It was Therefore, there is a problem that the optimum bonding pad arrangement at the time of wire bonding does not always become the optimum bonding pad arrangement at the time of the performance test of the semiconductor chip in the wafer state.

The present invention has been made in order to solve the above problems, and obtains a semiconductor device that realizes optimum bonding pad arrangements during a performance test of a semiconductor chip in a wafer state and during wire bonding. With the goal.

[Means for Solving the Problems] A semiconductor device according to the present invention is a semiconductor device having bonding provided in alignment along a peripheral portion on a semiconductor chip and bonding pads provided apart from this alignment. , Is characterized by the following. That is, the bonding pads provided in alignment with the bonding pads provided in alignment with the bonding pads provided in the periphery are electrically connected to the internal pads electrically connected to the bonding pads provided in the periphery. Redundant bonding pads that are electrically connected.

[Operation] In the present invention, a redundant bonding pad is provided in alignment with the bonding pad provided in the peripheral portion on the semiconductor chip corresponding to the bonding pad provided separately, and the redundant bonding pad is provided. Is electrically connected to the internal circuit to which the bonding pad provided separately is electrically connected, so that the performance test of the semiconductor chip in a wafer state can be performed using the redundant bonding pad. .

Embodiment An embodiment of the present invention will be described below with reference to the drawings. In addition,
In the description of this embodiment, the description overlapping with the description of the conventional technique will be appropriately omitted.

FIG. 1 is a plan view showing the structure of a semiconductor device according to an embodiment of the present invention. The structure of FIG. 1 differs from the structure of the semiconductor device including the semiconductor chip 1 on which the bonding pads are arranged of FIG. 4B in the following points. That is, in order to optimize the arrangement of the bonding pads at the time of wire bonding, the bonding pads 110a arranged in the peripheral portion in the longitudinal direction on the semiconductor chip 1 are newly provided in the peripheral portion in the lateral direction on the semiconductor chip 1. A redundant bonding pad 11a is arranged, and the redundant bonding pad 11a is aligned with the bonding pads 11b, 11c ... 11n. The bonding pad 110a and the bonding pad 11a are connected by the internal wiring 80,
The internal wiring 80 is connected to a predetermined internal circuit of the semiconductor chip 1. Similarly, in order to optimize the arrangement of the bonding pads at the time of wire bonding, the bonding pads 120a are arranged on the peripheral portion of the semiconductor chip 1 in the longitudinal direction. A redundant bonding pad 12n is newly arranged, and the redundant bonding pad 12n is aligned with the bonding pads 12a, 12b, 12c ... The bonding pad 120n and the bonding pad 12n are connected by an internal wiring 81, and the internal wiring 81 is connected to a predetermined internal circuit of the semiconductor chip 1.

During the performance test of the semiconductor chip 1 in the wafer state, the redundant bonding pads 11a and 12n are used in place of the bonding pads 110a and 120n to replace the semiconductor chip 1
All signals can be input / output only with a plurality of bonding pads arranged in the peripheral portion in the upper lateral direction.
It is possible to test the performance of multiple semiconductor chips in parallel in the state shown in Fig. 4A. In this way, by changing the combination of the bonding pads used during wire bonding and the combination of the bonding pads used during the performance test of the semiconductor chip in the wafer state, not only during the wire bonding but also in the wafer state. The optimum bonding arrangement can be realized during the performance test of the semiconductor chip.

In the above embodiment, the case where one redundant bonding pad is arranged for each bonding pad arranged in the peripheral portion of the semiconductor chip in the longitudinal direction is shown. The increase in input capacitance may cause a problem. FIG. 2 is a plan view showing the structure of a semiconductor device according to another embodiment which solves this problem. In the figure, a switch 9 is provided between the bonding pad 110a on the semiconductor chip 1 and the bonding pad 11a.
Is provided. The contact 9b and the contact 9c are connected during the performance test of the semiconductor chip in the wafer state. Then, at the time of wire bonding, the contact points 9a and 9c are connected to separate the redundant bonding pad 11a to prevent an increase in the input capacitance viewed from the package pin.

As described above, according to the present invention, in the semiconductor device having the bonding pads aligned in the peripheral portion of the semiconductor chip and the bonding pads spaced apart from the alignment, Corresponding bonding pads are provided, redundant bonding pads are provided in alignment with the bonding pads that are aligned in the peripheral portion, and the redundant bonding pads are electrically connected to the bonding pads that are provided separately. Since it is electrically connected to the internal circuit according to the present invention, it is possible to obtain a semiconductor device capable of realizing optimum bonding pad arrangements during a performance test of a semiconductor chip in a wafer state and during wire bonding.

[Brief description of drawings]

FIG. 1 is a plan view showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view showing the structure of a semiconductor device according to another embodiment of the present invention. FIG. 3 is a plan view showing a conventional structure in which a semiconductor chip having bonding pads arranged therein is enclosed in a plastic mold package. FIG. 4A is a diagram showing a state of a performance test of a semiconductor chip in a wafer state in which bonding pads are arranged only on the peripheral portion in the lateral direction on the semiconductor chip. FIG. 4B is a diagram showing a state of a performance test of a semiconductor chip in a wafer state when bonding pads are arranged on peripheral portions in the longitudinal and lateral directions on the semiconductor chip. In the figure, 1, 2 and 3 are semiconductor chips, 4 is a plastic mold package, 5a is an A0 signal terminal, 5b is an A2 signal terminal, 5c is an A1 signal terminal, 6a, 60a, 6b and 6c are bonding wires, 7 is a probe card, 9 is a switch, 10 is a wafer, 10a and 110a are A0 signal bonding pads, and 11b is A2.
Signal bonding pad, 11c A1 signal bonding pad, 11n, 12a, 12b, 12c, 12n, 120n bonding pad, 13a, 130a, 13b, 13c, 13n, 14a, 14b, 14c, 14n, 140n test needle , 80, 81 are internal wiring. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A semiconductor device having a bonding pad provided in alignment with a peripheral portion of a semiconductor chip and a bonding pad provided away from the alignment, wherein the periphery is provided corresponding to the bonding pad provided separately. And a redundant bonding pad electrically connected to an internal circuit electrically connected to the bonding pad provided separately from the bonding pad. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the bonding pads provided separately from each other and the redundant bonding pads are electrically connected. 3. A bonding pad provided on the semiconductor chip between the remote bonding pad and the redundant bonding pad, and the remote bonding pad or the redundant bonding pad is electrically connected to the internal circuit. The semiconductor device according to claim 1, further comprising pad switching means for performing the switching.