JPH0770596B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a method of manufacturing a semiconductor integrated circuit device capable of operating at high speed with low power consumption.

[Background of the Invention]

Recent advances in semiconductor technology have made devices finer and faster, enabling the integration of thousands to tens of thousands of high-speed transistors in a semiconductor chip of several millimeters square. However, if many circuits are incorporated in such a highly integrated semiconductor chip, the connection wiring between the circuits becomes long, and the operation speed of the circuits decreases.

In addition, it is no longer possible to manually design such a highly integrated circuit, and automatic design by a computer has come to be widely used. First in automatic design by computer
As shown in the figure, a plurality of pre-designed possible circuit blocks are automatically arranged on a semiconductor chip, and the functional circuit blocks are automatically wired according to a certain rule to complete an LSI. In FIG. 1, reference numeral 10 is a semiconductor chip, and on the semiconductor chip 10, there are block rows 11-a, 11-b, 11-.
Pre-designed functional circuit blocks 13, 14, 15 and the like are arranged in each block row including c. A blank space around each block row is assigned as a wiring channel for interconnecting the functional circuit blocks, and the wiring shown in the figure is performed by a computer. In the figure, reference numeral 12 is a bonding pad for pulling out the wiring inside the LSI to the outside of the semiconductor chip. As functional circuit blocks, those that consist only of logic gates such as NAND circuits and NOR circuits, combinational logic circuits that combine multiple logic gates, sequential logic circuits such as flip-flops, counters and shift registers, and buffer circuits are designed in advance. Has been done. FIG. 2A is a symbol diagram of a 2-input NAND circuit as an example of a functional circuit block. In the figure, 20 is a functional circuit block region, 21 and 22 are input terminals, and 23 is an output terminal.
Further, FIG. 2 (B) shows a configuration example of a 2-input NAND circuit.
This circuit is known as a TTL NAND circuit, and a description of its configuration and operation will be omitted.

By the way, in such an automatic design, the individual wiring lengths that connect the functional circuit blocks are as short as possible, and if the load driving capability of the signal transmission circuit is low, not only will the delay due to the wiring increase, but also at the receiving side. However, there is a problem in that a plurality of signals arrive at different times, the circuit does not operate normally depending on the type of the circuit, or a hazard occurs, and the hazard causes the next circuit to operate illegally.

One of the practical methods to solve such a problem is to configure all functional circuit blocks with bipolar circuits with high load driving capability, and to minimize fluctuations in the circuit delay time due to wiring delay time and wiring length variations. It is to make it smaller, and a typical example is a bipolar LSI using ECL circuits or TTL circuits. However, the bipolar circuit inherently consumes a large amount of power and has a limit to high integration, and also has a drawback that an expensive package for mounting an LSI must be used. To achieve high integration with low power consumption
The CMOS circuit is the best. However, the CMOS circuit has a much larger load dependency of the delay time than the bipolar circuit, and is extremely inconvenient for high-speed operation. The load dependency of the CMOS circuit can be improved to some extent by increasing the channel width / channel length of all transistors. However, there is a limit to the speedup by this method, and there is a drawback that high integration is hindered.

Another example of the conventional combinational logic circuit shown in FIG. 3 is another method for improving the load dependency of the CMOS circuit. In the figure 30
Is a 3-input NAND circuit, and 31, 32-a to 32-c are inverter circuits, and the load driving capability can be tripled by the inverters 32-a to 32-c connected in parallel. However,
In this method, the delay time of the inverter 31 and the parallel inverters 32-a to 32-c is added to the delay time of the 3-input NAND circuit 30, and therefore, the delay time in the low load region increases. Further, in order to obtain a driving capability equivalent to that of a bipolar transistor, a larger number of parallel connections are required, which has a drawback of hindering high integration.

FIG. 4 shows still another conventional example. In the figure, 41 and 42 are C
Reference numeral 43 is a MOS circuit, and 43 is an intermediate buffer circuit. In this method, since a transistor having a large driving capacity is arranged as an intermediate buffer, not only occupies a considerable area of the chip, but also a wiring channel is occupied for the wiring connecting the CMOS circuit and the intermediate buffer, and other wiring is required. Becomes an obstacle. In addition, the wiring between the CMOS circuit and the intermediate buffer
There is a drawback that the delay time of the CMOS circuit becomes large.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art and provide a method for manufacturing a semiconductor integrated circuit device capable of low power consumption and high speed operation.

[Outline of Invention]

The feature of the present invention for achieving the above object is to input a digital signal onto one semiconductor chip,
A CMOS block configured by performing a logical operation on the digital signal and outputting a digital signal and including a CMOS transistor circuit, or an output unit configured by a bipolar transistor and a drive unit driving the output unit configured by a MOS transistor B
It has a plurality of digital logic circuit blocks each composed of one of the i-MOS blocks, the CMOS block and the Bi-MO
In a method of manufacturing a semiconductor integrated circuit device in which S blocks are mixedly arranged, at least one of the digital logic circuit blocks has a load of another digital logic circuit block connected to this digital logic circuit block,
If the delay time with respect to the load of the block is in the first load region smaller than the delay time with respect to the load of the Bi-MOS block, the CMOS block is selected, and at least one other digital logic circuit block selects the digital logic circuit block. If the load of the other digital logic circuit block connected to the circuit block is in the second load region where the delay time for the load of the CMOS block is larger than the delay time for the load of the Bi-MOS block, the Bi-MOS To choose a block.

In the preferred embodiment of the present invention, the high speed operation of the low power consumption and low load region of the CMOS circuit and the high speed operation of the bipolar circuit,
Focusing on the high load drive capability, the internal circuit of the functional circuit block has a small load and is capable of high-speed operation. Of the required parts and the output signals of the functional circuit blocks, those that require a high load driving capability for the connection between the functional circuit blocks are configured with a bipolar CMOS composite circuit having a bipolar output stage.

Example of Invention

The present invention will be described below with reference to the drawings. FIG. 5 shows the relationship between the load and the delay time of the CMOS circuit and the bipolar circuit. In the figure, 50 is the delay time characteristic of the CMOS circuit, and 51 is the delay time characteristic of the bipolar circuit. As is clear from the figure, the CMOS circuit has a large load dependency and the difference in the delay time between the low load and the high load is remarkable, which is extremely inconvenient for high-speed operation and reliable circuit operation as an LSI. However, in miniaturized CMOS, the load is reduced as shown in the figure.
In the low load region of C ₁ or less, high speed operation equivalent to or higher than that of a bipolar circuit is possible. On the other hand, the delay time of the bipolar circuit has very little load dependency, and the difference between the delay times of low load and high load is small, which is very convenient for high-speed operation and reliable circuit operation as an LSI.

Accordingly, in a semiconductor chip in which a plurality of functional circuit blocks are arranged in a semiconductor chip and the functional blocks are interconnected by wiring conductors to form a semiconductor integrated circuit device, a light load portion of an internal circuit of the functional circuit block is It is composed of a CMOS circuit, and a part requiring high load driving capability is composed of a bipolar CMOS composite circuit using a bipolar transistor formed adjacent to a MOS transistor.

FIG. 6 shows an example of a basic gate of a bipolar CMOS composite circuit suitable for application to the present invention.
IEEE TRANSACTION ON ELECTRON DEVICE, VOL.ED−16,
It was announced by HUNG CHANGLIN in No.11 NOV.1969. In the figure, 60 is a PMOS transistor, 61 is an NMOS transistor, and 62 and 63 are NPN transistors. Also, 64
Is an input terminal, and 65 is an output terminal. Now, when a low level signal is applied to the input terminal 64, the NMOS transistor 61
Turns off, and the NPN transistor 63 turns off. On the other hand, PMOS
Since the transistor 60 turns on and the NPN transistor 62 turns on, the output terminal 65 becomes high level. Also, input terminal 64
When a high level signal is applied to the RMOS transistor
60 turns off and NPN transistor 62 turns off. On the other hand, NMO
Since the S transistor 61 is turned on and the NPN transistor 63 is turned on, the output terminal 65 becomes low level. Therefore, this circuit operates as an inverter. Further, in this circuit, a current path is not formed between the power supply V _DD and the reference potential V _ss in the steady state, so that the low power consumption of the CMOS circuit is maintained.

FIG. 7A shows another example of the basic gate configured by the bipolar CMOS composite circuit.

In the figure, 71 and 72 are PMOS transistors, 73 and 74 are NMOS transistors, and 75 and 76 are NPN transistors. X ₁ and x ₂ are input terminals and y is an output terminal. This circuit is a 2-input NAND
Although it operates as a circuit, description of the operation is omitted. In FIG. 7 (A), 77 and 78 are NPN transistors 75, 76 and N.
This is a resistor that forms a discharge path for promptly extinguishing the accumulated charges when the MOS transistors 73, 74 and the PMOS transistor 73 are turned off.

FIG. 7 (B) shows a layout schematic diagram for constructing the bipolar CMOS composite circuit of FIG. 7 (A), and FIG. 8 shows a device cross-sectional schematic structure for easier understanding.
In these figures, parts corresponding to those in FIG. 7 (A) are indicated by the same numbers. The resistors 77 and 78 are omitted. 7th
In FIG. 1B, 81 and 82 are gate electrodes in contact with the input terminals x ₁ and x ₂ , 83 is a P ⁺ diffusion layer, and 84 is an N ⁺ diffusion layer. PM
The OS transistor 71 is formed under the gate electrode 81 on the P ⁺ diffusion layer 83, and the PMOS transistor 72 is formed under the gate electrode 82 on the P ⁺ diffusion layer 83. Also, the NMOS transistor 73 is
The NMOS transistor 74 is formed below the gate electrode 82 on the N ⁺ diffusion layer 84, and the NMOS transistor 74 is formed below the gate electrode 81 on the N ⁺ diffusion layer. The NPN transistor 75 collector has a power supply V
Connected to _DD , the base is a PMOS transistor by wiring 86
It is connected to the common drain electrode of 71 and 72. The emitter of the NPN transistor 76 is connected to the reference potential V _ss by the wiring 87, and the base is connected to the source electrode of the NMOS transistor 74 by the wiring 88. And the collector is NMOS by wiring 91
Connected to the drain of transistor 73 and wiring 89
Is connected to the emitter of NPN transistor 75 by
It is connected to the output terminal y by 0. Incidentally, FIG. 7 (B)
The middle x mark is a contact hole for connecting the diffusion layer and the wiring.

FIG. 9 shows another preferred configuration example of the functional circuit block. FIG. 9A shows a well-known sequential logic circuit D-TYPE.
This is a flip-flop, and the truth table is shown in FIG. 9 (B). Further, FIG. 9C shows the circuit.
As a preferable configuration of the functional circuit block used in the present invention, CM is used for all 91 parts that can operate at high speed with a small load.
It is composed of an OS circuit, and 92 parts that are required to have a load driving capability are composed of a bipolar CMOS composite circuit.

FIG. 14 (A) shows the configuration of the logic gate circuits G ₅ and G _{6 in} the portion 91 of FIG. 9 (C) by the CMOS circuit. In the figure, PMO
S transistors 451,452,453 and NMOS transistors 461,462,
463 configures a 3-input NAND gate G ₅ , and a PMOS transistor 4
3-input NAN with 54,455,456 and NMOS transistors 464,465,466
It constitutes the D gate G ₆ . The output c of G ₅ is connected to one of the inputs of G ₆ (common gate electrode of PMOS 454 and NMOS 464), and the output d of G ₆ is connected to one of the inputs of G ₅ (PMOS 453 and NMOS 463).
3 input NAND gate
Constitute a flip-flop circuit in G ₅ and G _6.

FIG. 14 (B) shows the bipolar CMOS of the portion 92 in FIG. 9 (C).
A specific circuit example of the logic gate B ₁ configured by a composite circuit is shown. In the figure, PMOS transistor 471, NMOS
Transistor 472, NPN transistor 475,476, resistor 473,4
The inverter circuit is composed of 74. That is, now
When input c is low, NMOS transistor 472 and NPN transistor 476 are off. On the other hand, PMOS transistor 4
The output goes high because 71 and NPN transistor 475 turn on. When the input c is high level, the PMOS transistor 471 and the NPN transistor 475 are turned off. On the other hand, since the NMOS transistor 472 and the NPN transistor 476 are turned on, the output becomes low level. Note that the resistance 473
Forms a discharge path for the accumulated charge of the PMOS transistor 471 and the base accumulated charge of the NPN transistor 475 when the input c is at a high level and the PMOS transistor 471 and the NPN transistor 475 are off. Similarly, the resistance 474 is NMO when input c is low level.
Charge accumulated in the NMOS transistor 472 and the NPN transistor when the S transistor 472 and the NPN transistor 476 are off
A discharge path for the base accumulated charge of 476 is formed.

FIG. 10A shows an example of the configuration of a typical combinational logic circuit of the functional circuit block used in the present invention. In the figure, reference numeral 100 indicates a functional circuit block, and one functional circuit block is included by including four circuit units A, B, C and D (a single gate circuit or a circuit combining a plurality of gate circuits) inside. I am configuring. 101, 102, 103 are input terminals of the functional circuit block, and 104, 105, 106, 107 are output terminals. The signals from 101 and 102 are input to the circuit A, and the output (indicated by ∇ in the figure) is connected to the input of the circuit C by the output of a logic gate configured by a CMOS circuit (indicated by a solid line in the figure below). And is connected to the output terminal 104. The signals from 102 and 103 are input to the circuit B, and one of the outputs is CMO.
The output of the logic gate constituted by the S circuit is connected to the output terminal 107. The remaining output of the circuit B is connected to the inputs of the circuits C and D by the output of the logic gate constituted by the bipolar CMOS composite circuit (shown by the dotted line in the figure below). The input of the circuit C is connected to the output of the circuit A and the output of the circuit B, and the output thereof is connected to the output terminal 105 of the logic gate constituted by the bipolar CMOS composite circuit. The signal of the input terminal 102 and one output of the circuit B are connected to the input of the circuit D, and the output thereof is connected to the output terminal 106 of the logic gate constituted by the bipolar CMOS composite circuit. In short, in this embodiment, CM is provided at each level of the circuit unit inside the functional circuit block which is the array unit on the chip.
The feature is that selection is made between the output of the logic gate configured by the OS circuit and the logic gate configured by the output of the bipolar CMOS composite circuit.

FIG. 10 (B) is an expansion of the functional circuit block of FIG. 10 (A) into an internal circuit unit level.
The same parts as are indicated by the same numbers. In the figure, 110 is a two-input NAND gate configured by a conventionally known CMOS circuit, and constitutes a circuit unit A in FIG. 10 (A). Reference numeral 120 is a two-input NOR gate composed of a bipolar CMOS composite circuit, which constitutes a circuit unit B together with an inverter 150 composed of a CMOS circuit. 130
Is a 2-input NO constructed by a bipolar CMOS composite circuit
It is an R gate and constitutes a circuit unit C. And 1
Reference numeral 40 denotes a 2-input NAND gate formed of a bipolar CMOS composite circuit, which constitutes a circuit unit D.

FIG. 15 is an example of a specific circuit configuration of the functional circuit block including the five circuit units shown in FIG. 10 (B). In the figure, PMOS transistors 501 and 502 and NMOS transistor 5
03 and 504 form the CMOS 2-input NAND gate 110 of FIG. 10 (B). Next, PMOS transistors 511 and 512, NMOS transistors 513 and 514, NPN transistors 517 and 518, and resistors 515 and 516.
The two-input NOR gate 130 is composed of a bipolar CMOS composite circuit. Note that the resistors 515 and 516 form a discharge path for the transistor base accumulated charges, like the resistors 473 and 474 of FIG. 14B. Next, the PMOS transistor 52
1,522, NMOS transistors 523,524, NPN transistor 52
7,528, resistor 525,526 with bipolar CMOS composite circuit 2
It constitutes the input NOR gate 120. Next, the PMOS transistor 531 and the NMOS transistor 532 form the CMOS inverter 150. Finally, PMOS transistors 541 and 542, NMOS transistors 543 and 544, NPN transistors 547 and 548, resistor 54
5,546 constitutes a 2-input NAND gate 140 by a bipolar CMOS composite circuit.

FIG. 11A shows an embodiment of the present invention. In the figure,
Reference numeral 200 denotes a semiconductor chip, which is a block row 201-a to 201-
c are arranged. The block row 201-a includes functional circuit blocks 211, 212, 213, 214, the block row 201-b includes functional circuit blocks 221, 222, and the block row 201-c includes functional circuit blocks 231, 232, 233. When the functional circuit blocks are interconnected to form an LSI, the functional circuit block 211 includes an output of a logic gate formed by a CMOS circuit and a logic gate formed by a bipolar CMOS composite circuit. Of the output of the short-circuited functional circuit block 212 and 221 by wiring 251 and 252.
The output of a logic gate formed by a CMOS circuit is connected, and the functional circuit blocks 213, 214, 231 and 232 at a long distance are connected by a wiring 253 by a bipolar CMOS composite circuit output. Further, the functional circuit block 233 has only a CMOS circuit output and is connected to the functional circuit block 232 by the wiring 261. Furthermore, the functional circuit block 232 has only a bipolar CMOS composite circuit output and is connected to the bonding pad 270 by the wiring 262.

FIG. 11 (B) is a circuit in which, in FIG. 11 (A), a signal is introduced from outside the chip via the bonding pads 201 and 202 to perform a logical operation, and the output is distributed to a plurality of internal functional circuit blocks. The output 253 of the block 211 and the functional circuit block 211 and the output 261 of the functional circuit block 233 are introduced to perform a logical operation, and the output 262 is connected to the bonding pad 2
Functional circuit block 232 that outputs to the outside of the chip via 70
Is taken out. In the figure, a functional circuit block 211 introduces a signal through a bonding pad 201, 202 to perform a logical operation and supply one CMOS circuit output 251 to an internal functional circuit block 221. Similarly, the remaining CMOS circuit output 252 is supplied to the functional circuit block 212. Furthermore, the bipolar CMOS composite circuit output 253 is connected to the functional circuit block 213, 214, 2
31 and the functional circuit block 232. Next, the functional circuit block 232 is the functional circuit block 2
An output 253 of 11 and an output 261 of the functional circuit block 233 are introduced to perform a logical operation, and a bipolar CMOS composite circuit output 262 outputs it via a bonding pad 270 to the outside of the chip.

FIG. 16 shows a specific configuration example of FIG. 11 (B).
In the figure, the functional circuit block 211 is a 2-input NAND gate 6
It is composed of five circuit units 01, 602, 603 and inverters 604, 605. Of these, only the 2-input NAND gate 603 is composed of a bipolar CMOS composite circuit, and the other four are composed of CMOS circuits.

Next, the functional circuit block 232 has 2 input NOR gate 606 1
It consists of individual circuit units, which are composed of bipolar CMOS composite circuits.

FIG. 17 shows an example of the circuit configuration of FIG. In the figure, PMOS transistors 611 and 612 and NMOS transistor 61
3,614 constitute the CMOS 2-input NAND gate 601 in FIG. Similarly, the PMOS transistors 621 and 622 and the NMOS transistors 623 and 624 form a CMOS 2-input NAND gate 602. Next, the PMOS transistors 631 and 632, the NMOS transistors 633 and 634, the NPN transistors 635 and 636, and the resistors 637 and 638 form a 2-input NAND gate 603 of a bipolar CMOS composite circuit. Next, PMOS transistors 661 and 662, NMOS transistors 663 and 664, NPN transistors 665 and 666, and resistor 66.
2-input NOR gate with 7,668 bipolar CMOS composite circuit
It comprises 606. Finally, the PMOS transistor 641
CMOS transistor 604 is composed of OS transistor 642,
The transistor 651 and the NMOS transistor 652 form a CMOS inverter 605.

FIG. 12 shows another embodiment of the present invention. When the degree of integration of the semiconductor integrated circuit device is improved and more circuits can be formed by one semiconductor chip, the connection between the circuits becomes more complicated and longer, which is one of the causes for lowering the performance of the semiconductor integrated circuit. In addition, the processing time of a computer for arranging and wiring these circuits will also become very long. Therefore, one semiconductor chip is computationally divided and defined into a plurality of sub-chips,
A circuit is arranged and wired for each sub-chip unit, and thereafter, interconnection is provided between the sub-chips to complete a semiconductor integrated circuit device. The present invention is also extremely effective for the configuration of the semiconductor integrated circuit having such a sub-chip level as a unit.

In FIG. 12, 300 is one semiconductor chip, and four sub-chips 301 to 304 are defined on the semiconductor chip. The margin between these sub-chips is a wiring channel for connecting the sub-chips to each other. To be

FIG. 13 shows an embodiment of the present invention in the case of constructing a sub chip. In this sub-chip, 13 functional circuit blocks 401 to 413 are arranged. Also, as an input terminal 42
3 of 1 to 423 are provided, and 6 of 431 to 436 are provided as output terminals.
Output terminals are provided. Each functional circuit block has only CMOS circuit output (402,405,412), bipolar CMOS composite circuit output only (403,404,40)
6,407,409,411,413), with both outputs (401,40
8,410), which is used mainly depending on the load driving capacity. That is, the CMOS circuit output is used for the fanout and the light load portion where the total wiring length is short, and the bipolar CMOS composite circuit output is used for the heavy load portion and the portion connected to the output terminal of the complex function circuit block. In the actual design of the composite circuit function block, when designing the layout of the function circuit blocks and the interconnection between them manually, it is necessary to use CMOS circuit output or bipolar CMOS composite circuit output because the interconnection length can be calculated in advance. Choosing a tree is easy.
However, it is difficult to accurately estimate the mutual wiring length when the layout and wiring are automatically designed by a computer.
Therefore, in such a case, it is necessary to judge from the size and complexity of the composite function circuit block that most of the outputs of the function circuit block are bipolar CMOS composite circuits. However, even in this case, since the internal circuit of each functional circuit block except the output part is composed of a CMOS circuit, the increase in area due to the incorporation of the bipolar transistor can be minimized.

The "functional circuit block" referred to in the present invention is a logical circuit such as a NOT circuit, a NAND circuit, and a NOR circuit, a combinational logical circuit in which a plurality of logical gates are combined to perform a desired logical operation, a flip-flop, a counter, and a shift register. This includes not only the sequential logic circuits such as the above, but also the case where an inverter as shown in FIG. 14B is used as an input buffer circuit and an output buffer circuit.

As is clear from the above description, the present embodiment makes use of the features of the CMOS circuit, such as low power consumption and high speed at light load, and the high load driving capability of the bipolar circuit, and at the circuit level in the functional circuit block. Since a bipolar CMOS composite circuit is used as appropriate, high-speed operation with the minimum required chip area increase,
A low power consumption LSI can be realized. The present invention is a manual LSI
It is also effective for the layout and wiring design, but it is particularly effective when the automatic design by a computer in which the wiring length for each signal varies.

〔The invention's effect〕

As described above, according to the present invention, a semiconductor integrated circuit device capable of low power consumption and high-speed operation can be obtained, and the circuit is selectively used according to the load driving capability. An advantageous design method can be obtained.

[Brief description of drawings]

1 is a chip layout diagram of an LSI, FIG. 2 is a diagram showing an example of a functional circuit block, FIG. 3 is a diagram showing an example of parallel driving in CMOS, FIG. 4 is a diagram showing an example of driving by an intermediate buffer,
FIG. 5 is a diagram showing load characteristics of CMOS and a bipolar circuit, FIG. 6 is a diagram showing an example of a bipolar CMOS composite circuit, FIG. 7 is a diagram showing another example of a bipolar CMOS composite circuit, and FIG. FIG. 9 is a diagram showing a schematic cross-sectional structure of the circuit of FIG. 7, and FIG.
FIG. 10 is a diagram showing a general structure of a functional circuit block of the present invention, FIG. 11 is a diagram showing an embodiment of the present invention, and FIG. 12 is a semiconductor consisting of four sub-chips. FIG. 13 is a diagram showing an integrated circuit device, FIG. 13 is a diagram showing another embodiment of the present invention, FIG. 14 is a diagram showing a concrete circuit example of FIG. 9 (C), and FIG. 15 is FIG. 10 (B). 16) is a diagram showing a concrete circuit example, FIG. 16 is a diagram showing a concrete configuration example of FIG. 11 (B), and FIG. 17 is a diagram showing a concrete circuit example of FIG. 10 ... Semiconductor substrate, 13,14,15 ... Functional circuit block, 4
1,42 …… CMOS circuit, 43 …… Intermediate buffer, 60,71,72 ……
PMOS transistor, 61, 73, 74 ... NMOS transistor, 6
2,63,75,76 …… NPN transistor, 91 …… CMOS circuit, 92
...... Bipolar CMOS composite circuit, 200 …… Semiconductor chip, 2
11〜214,221〜222,231〜233 …… Functional circuit block, 300
…… Semiconductor substrate, 301-304 …… Sub chip.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H03K 19/08 A 8839-5J (56) Reference JP-A-57-212827 (JP, A) "Electronic material" Vol. 18 No. 8 (1979.8) P. 44-49 "Electronic Materials" Vol. 21 No. 1 (1982.1) P. 67-73 "Ricoh Technical Report" No. 8 November 1982. P. 40-45

Claims (7)

[Claims] 1. A CMOS configured by inputting a digital signal on one semiconductor chip, performing a logical operation of the digital signal, outputting a digital signal, and comprising a CMOS transistor circuit.
A plurality of digital logic circuit blocks each of which is composed of either a block or a Bi-MOS block whose output section is composed of bipolar transistors and which drives the output section is composed of MOS transistors. In the method for manufacturing a semiconductor integrated circuit device in which the above and the Bi-MOS blocks are mixedly arranged, at least one of the digital logic circuit blocks has a load of another digital logic circuit block connected to the digital logic circuit block, If the delay time with respect to the load of the CMOS block is in the first load region with respect to the delay time with respect to the load of the Bi-MOS block, select the CMOS block, and at least one other digital logic circuit block The load of the other digital logic circuit block connected to the logic circuit block is If the delay time for locking of the load is in the second load range greater than the delay time for the load of the Bi-MOS blocks,
A method of manufacturing a semiconductor integrated circuit device, comprising selecting the Bi-MOS block. 2. The input or output of the CMOS block is connected to at least one other digital logic circuit block or bonding pad, and the input or output of the Bi-MOS block is at least 1. A method of manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is connected to two other digital logic circuit blocks or bonding pads, and is arranged in a mixed manner on the one semiconductor chip. 3. The sub-chip according to claim 1, wherein a plurality of sub-chips are formed by combining a plurality of the digital logic circuit blocks on the one semiconductor chip.
At least one digital logic circuit block forming an output from one sub-chip to another sub-chip has its output part composed of the bipolar transistor, and the control part controlling the output part is composed of a MOS transistor B
A method of manufacturing a semiconductor integrated circuit device including an i-MOS block. 4. Claims 1, 2 or 3
In the paragraph, the digital logic circuit block includes one of a logic gate, a combination logic circuit, a sequential logic circuit, and a driver circuit between logic function blocks, or a circuit in which these are combined, a semiconductor integrated circuit device. Manufacturing method. 5. The Bi-MOS block, which is a composite circuit of the bipolar transistor and the MOS transistor according to claim 1, claim 2, claim 3, or claim 4, wherein the output is at a high level. And a drive unit for driving the output unit including the bipolar transistor, and a drive unit for driving the output unit including the bipolar transistor. Method for manufacturing semiconductor integrated circuit device. 6. Claims 1, 2, 3,
In Claim 4 or 5, at least one of the digital logic circuit blocks is a combination block including the CMOS block and the Bi-MOS block, and the combination block is the CMOS.
A method of manufacturing a semiconductor integrated circuit device, comprising: outputting at least two output signals of a CMOS output signal from a block and a Bi-MOS output signal from the Bi-MOS block. 7. Claims 1, 2, 3,
In paragraph 4, paragraph 5, or paragraph 6, the input portion or output portion of the CMOS block is connected to at least one other digital logic circuit block, and the input portion or output portion of the Bi-MOS block is at least one. Connected to two other digital logic circuit blocks, the output of the combination block is a CMOS output from the CMOS block and a Bi-MOS from the Bi-MOS block.
An output section, the CMOS output section is connected to at least one other digital logic circuit block, and the Bi-MOS output section is connected to at least one other digital logic circuit block. Method for manufacturing semiconductor integrated circuit device.