JPH0770616B2 - Semiconductor memory cell and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor memory including a capacitor section and an insulated gate field effect transistor, and a method for manufacturing the semiconductor memory.

[Conventional technology]

A semiconductor memory cell that stores binary information in the form of electric charge is excellent in high integration, large capacity, and memory cell because of its small cell area. In particular, a memory cell composed of one transistor and one capacitor (hereinafter abbreviated as 1T1C cell) as a memory cell is important as a memory cell for a highly integrated memory because it has few constituent elements and a small cell area. By the way, with the reduction of memory cell size due to high integration of memory, 1T1C
The area of the capacitance part in the cell structure is decreasing. The decrease in the storage charge amount due to the decrease in the area of the capacitance portion causes the problem of α-particle resistance and the deterioration of the sensitivity of the sense amplifier.

Conventionally, in order to solve such a problem, there is known a method of forming a large storage capacity portion despite the reduction of the memory cell area. For example, the International Solid State Conference (Intern
ational Electron Devices Meeting) 1978, 348〜351
The page says `` Novel High Density, Stacked Capacitor MOS
In a paper published under the title of "RAM", as shown in Fig. 3, the capacitor portion of a 1T1C cell is formed of two layers of polysilicon 51,5.
The structure formed by 2 is shown. The first-layer polysilicon 51 is electrically connected to the source side of the switching transistor, and the second-layer polysilicon 52 is kept at a constant potential as an opposite electrode of the first-layer polysilicon 51. The amount of charge stored in this memory cell is determined by the amount of capacitance formed between the two-layer polysilicon 51, 52. Therefore, the memory cell of this structure is designed so as to cover most of the area on the memory cell in order to maximize the storage capacity of the memory cell. In FIG. 3, 53 is a bit line, 54 is a diffusion layer connected to the bit line, 55 is a gate electrode of a switching transistor, and 56 is an insulating film.

[Problems to be Solved by the Invention]

However, in such a structure, there is a problem that the memory cell area is reduced and the storage capacity is gradually reduced as the memory is highly integrated.

An object of the present invention is to eliminate such conventional defects and provide a fine semiconductor memory cell suitable for high integration and a method for manufacturing the same.

[Means for Solving the Problems]

In order to achieve the above object, a semiconductor memory cell according to the present invention is a semiconductor memory cell including one insulated gate field effect transistor and one stacked type capacitor section. The stacked type capacitance portion of the first and second memory cells, which are in contact with each other by sharing the contact hole in which the wiring material to be formed is shared, includes the first charge storage electrode of the first memory cell and the second charge storage electrode of the second memory cell. A first capacitor insulating film, a counter electrode, and a second capacitor insulating film are sandwiched between and, and they are formed over the first and second memory cell regions.

A semiconductor memory cell according to the present invention comprises a step of forming an element isolation region, a gate insulating film, first and second gate electrodes on a semiconductor substrate, and then forming first and second source and drain regions. A step of covering at least the both gate electrodes with a first insulating film, and a step of forming a first charge storage electrode connected to the first source region on the first insulating film over the both gate electrodes. A step of covering at least the first charge storage electrode with a first capacitance insulating film, and a step of forming a counter electrode so as to cover at least the first charge storage electrode via the first capacitance insulating film, A step of forming a second capacitance insulating film on the counter electrode, and the counter electrode and the first charge storage electrode are in contact with each other via the second capacitance insulating film and the second insulation film and connected to the second source region. The second charge storage electrode is Forming over the gate electrode,
Forming a third insulating film over the entire surface of the wafer; forming a bit line in contact with the counter electrode and the first and second charge storage electrodes through a fourth insulating film and connected to the drain region. It is obtained by a manufacturing method including.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional view of a memory cell formed according to the present invention, and FIG. 2 (a), (b), (c), (d),
(E), (f), (g), (h), (i) are schematic cross-sectional views showing the manufacturing process in the present invention in order.

In FIG. 1, the capacitance portion of the first memory cell of the semiconductor memory cell according to the present invention is formed via the first storage electrode 5 connected to the first diffusion layer 2 of the silicon substrate 1 and the first capacitance insulating film 7. Counter electrode 9 formed on the other hand, and the capacitance portion of the second memory cell is formed on the other hand through the second storage electrode 6 connected to the second diffusion layer 3 and the second capacitance insulating film 8. It is formed by and. Reference numerals 10 and 11 are gate electrodes of the switching transistors of the first and second memory cells connected to the word line, and these are the third diffusion layer 4 and the first and second storage electrodes 5 connected to the bit line 12. Controls the transfer of charge between and.

Next, a method of manufacturing the semiconductor memory cell of the present invention shown in FIG. 1 will be described with reference to FIG.

First, as shown in FIG. 2A, an insulating film 22 is formed in an element isolation region on a p-type silicon single crystal substrate 21, and then a gate electrode 23 and a gate electrode 24 are sequentially formed.

Next, as shown in FIG. 2B, the gate electrodes 23 and 24 are
Then, using the insulating film 22 as a mask, an n-type impurity is implanted into the silicon substrate 21 by an ion implantation method to form the first, second,
The third diffusion layer 25, 26, 27 area is formed, and then the thermal oxidation method or the CV method is used.
A gate insulating film 28 is formed by using the D method, and the resist 29 covers the first diffusion layer 25 except a part thereof. Insulation film
It is necessary to grow the film thickness of 28 to a film thickness that does not cause an electrical interaction between the gate electrodes 10 and 11 and the first storage electrode 5 described in FIG.

Then, as shown in FIG. 2C, the insulating film 28 is removed by etching using the resist 29 as a mask, the resist 29 is removed, and then polysilicon 30 is deposited by a CVD method, and then thermal diffusion is performed. Method or ion implantation method is used to implant an n-type impurity into the polysilicon 30, and a resist film 31 having the shape of the first storage electrode 5 is formed.

Subsequently, as shown in FIG. 2D, the polysilicon 30 is removed by etching using the resist 31 as a mask,
Next, after removing the resist 31, a thin insulating film 32 is formed by using a thermal oxidation method or a CVD method, and then a polysilicon 33 is deposited by the CVD method, and then a thermal diffusion method or an ion implantation method is used. A type impurity is injected into the polysilicon 33.

Further, as shown in FIG. 2 (e), the polysilicon 33
Form a thin insulating film 34 using a thermal oxidation method or a CVD method,
After that, polysilicon 35 is deposited by the CVD method and then covered with a resist 36 except a part on the region of the second diffusion layer 26.

Subsequently, as shown in FIG. 2F, the polysilicon 35, the insulating film 34, the polysilicon 33, the insulating film 32, the polysilicon 30, the insulating film are formed by using the reactive sputter etching technique using the resist 36 as a mask. 28 is sequentially removed by etching to form a contact hole A, then the resist 36 is removed, and then an oxide film 37 is formed on the entire surface by a thermal oxidation method or a CVD method, and then the oxide film 37 is formed by using a reactive sputter etching technique. 37 is removed by etching to leave the oxide film 37 only on the side wall of the contact hole A.

Subsequently, as shown in FIG. 2 (g), polysilicon 38 is deposited by CVD so as to fill at least the contact hole A, and then n-type impurities are removed by thermal diffusion or ion implantation. After being injected into the polysilicon 35 and 38, a resist 39 having the shape of the second storage electrode 6 is formed.

Further, as shown in FIG. 2 (h), the polysilicon 38 is removed by etching using the resist 39 as a mask,
Next, after removing the resist 39, the insulating film 4 is formed by the CVD method.
0 is deposited, and then a resist 41 is formed except a part of the third diffusion layer 27.

Finally, as shown in FIG. 2 (i), the insulating film 40, the polysilicon 38, the insulating film 34, the polysilicon 33, the insulating film 32, and the polysilicon are formed by using the reactive sputter etching technique with the resist 41 as a mask. 30, the insulating film 28 is sequentially removed by etching to form a contact hole B, and then the resist 41 is removed. Then, an oxide film 42 is formed on the entire surface by a CVD method or a thermal oxidation method.
After the formation, the oxide film 42 is removed by etching using a reactive sputter etching technique, leaving the oxide film 42 only on the side wall of the contact hole B, and then forming the wiring metal 43 forming the bit line, The semiconductor memory cell shown in FIG. 1 is completed.

〔The invention's effect〕

According to the present invention, the storage electrode formation region, which is one of the factors that determine the stored charge amount, extends over two memory cell regions including the element isolation region.
It is possible to easily secure a charge amount more than double, to have a large storage capacity even in a fine memory cell area, and to easily obtain a memory cell suitable for high integration.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a memory cell formed by the method of the present invention, FIGS. 2 (a) to (i) are schematic sectional views showing an embodiment of the present invention step by step, and FIG. FIG. 1 is a schematic cross-sectional view of a conventionally known 1T1C cell. 1,21 …… Silicon substrate 2,3,4,25,26,27,54 …… Diffusion layer, 5,6 …… Storage electrode 7,8 …… Capacitive insulating film, 9 …… Counter electrode 10,11, 23,24 …… Gate electrode, 12,53 …… Bit line 22,28,32,34,37,40,42,56 …… Insulating film 29,31,36,39,41 …… Resist 30,33, 35,38,51,52 …… Polysilicon 43 …… Wiring metal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/108

Claims (2)

[Claims] 1. In a semiconductor memory cell including one insulated gate field effect transistor and one stacked capacitor section, a contact hole for filling a wiring material forming a bit line is shared between two adjacent memory cells. The stacked capacitive portions of the first and second memory cells, which are adjacent to each other, face each other between the first charge storage electrode of the first memory cell and the second charge storage electrode of the second memory cell. A semiconductor memory cell, wherein the semiconductor memory cell is formed so as to sandwich an electrode and a second capacitance insulating film and extend over the first and second memory cell regions. 2. A step of forming an element isolation region, a gate insulating film, first and second gate electrodes on a semiconductor substrate, and then forming first and second source and drain regions, at least the above. A step of covering both gate electrodes with a first insulating film; a step of forming a first charge storage electrode connected to the first source region over the both gate electrodes on the first insulating film; Covering the first charge storage electrode with a first capacitance insulating film, forming a counter electrode so as to cover at least the first charge storage electrode via the first capacitance insulating film, and the counter electrode A step of forming a second capacitance insulating film thereon, and a second charge in contact with the counter electrode and the first charge storage electrode through the second capacitance insulating film and the second insulating film and connected to the second source region. Form a storage electrode over both gate electrodes A step of, forming a third insulating film over the whole surface of the wafer, the counter electrode and the first,
And a step of forming a bit line in contact with the second charge storage electrode via a fourth insulating film and connected to the drain region.