JPH0770676B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0770676B2 JPH0770676B2 JP61230401A JP23040186A JPH0770676B2 JP H0770676 B2 JPH0770676 B2 JP H0770676B2 JP 61230401 A JP61230401 A JP 61230401A JP 23040186 A JP23040186 A JP 23040186A JP H0770676 B2 JPH0770676 B2 JP H0770676B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead
- semiconductor
- element mounting
- internal lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体素子を搭載するリードフレームに関する
ものである。Description: TECHNICAL FIELD The present invention relates to a lead frame on which a semiconductor element is mounted.
従来の技術 従来の半導体用リードフレームの平面図および断面図を
第４図（ａ），（ｂ）に示す。半導体素子搭載部１は、
内部リード部２および外部リード部３を形成する平板に
対して同一平面に形成されている。半導体素子は、同チ
ップをかかる半導体用リードフレームに搭載し、封止用
樹脂で被覆して使用されている。2. Description of the Related Art A plan view and a sectional view of a conventional semiconductor lead frame are shown in FIGS. 4 (a) and 4 (b). The semiconductor element mounting part 1 is
It is formed on the same plane as the flat plate forming the inner lead portion 2 and the outer lead portion 3. The semiconductor element is used by mounting the same chip on such a semiconductor lead frame and covering it with a sealing resin.
発明が解決しようとする問題点 従来の半導体用リードフレームは、半導体素子搭載部が
リード部と同一平面上に形成されているため、第４図
（ｂ）に示すように封止用樹脂５が厚くなり、パッケー
ジをフラット化する上で薄形化がむずかしいという問題
があった。また、チップ厚みの異なるものを複数半導体
素子搭載部に付設する場合ワイヤボンダーの条件出しを
変更する必要があった。Problems to be Solved by the Invention In the conventional semiconductor lead frame, since the semiconductor element mounting portion is formed on the same plane as the lead portion, the sealing resin 5 is formed as shown in FIG. 4 (b). There is a problem that the thickness becomes thick and it is difficult to reduce the thickness in flattening the package. Further, when a plurality of semiconductor chips having different chip thicknesses are attached to the semiconductor element mounting portion, it is necessary to change the condition setting of the wire bonder.
本発明はこのような問題を解決するもので、簡便な構造
の半導体用リードフレームにより、容易に封止用樹脂を
薄くすることを目的とする。The present invention solves such a problem, and an object of the present invention is to easily thin the sealing resin by using a semiconductor lead frame having a simple structure.
問題点を解決するための手段 上記問題点を解決するために、本発明は半導体素子搭載
部がリード部を形成する平板に対して半導体素子の厚み
を考慮して段差を設けて低くしたものである。半導体素
子の厚みに近い段差としてＬ字形の段差を形成すること
で薄形化が容易となる。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention is one in which a semiconductor element mounting portion is provided with a step in consideration of the thickness of the semiconductor element with respect to a flat plate forming a lead portion, and is made low is there. Forming an L-shaped step as a step close to the thickness of the semiconductor element facilitates thinning.
作用 半導体素子搭載部をリード部平面に対して段差を設ける
ことで半導体素子の高さだけ低くすることにより、封止
用樹脂を薄くすることができる。かつ、半導体素子とリ
ード部を最短の金属細線で配線できるとともに、条件を
一定にした組立が容易となり、厚みの異なる半導体素子
を付設してもワイヤボンダーの条件を変更する必要がな
くなった。By providing the semiconductor element mounting portion with a step with respect to the plane of the lead portion to lower the height of the semiconductor element, the sealing resin can be thinned. In addition, the semiconductor element and the lead portion can be wired with the shortest metal thin wire, and the assembly under the constant conditions is facilitated, so that it is not necessary to change the condition of the wire bonder even if the semiconductor elements having different thicknesses are attached.
実施例 第１図は、半導体素子搭載部１を内部リード部２、外部
リード部３より半導体素子４の高さだけＬ字状に0.2mm
低くした半導体用リードフレームを用いた一実施例であ
る。半導体素子としてホトダイオード４を搭載し、半導
体素子とリード部をAuワイヤ６でつなぎ封止用樹脂５で
被覆してある。封止用樹脂５はエポキシ系透明樹脂を用
いている。Example FIG. 1 shows that the semiconductor element mounting portion 1 is 0.2 mm in L shape from the inner lead portion 2 and the outer lead portion 3 by the height of the semiconductor element 4.
It is an example using a lowered lead frame for a semiconductor. A photodiode 4 is mounted as a semiconductor element, and the semiconductor element and the lead portion are connected by an Au wire 6 and covered with a sealing resin 5. The sealing resin 5 is an epoxy-based transparent resin.
第２図は、ハイブリッド素子のように半導体素子搭載部
が２ヶ所ある場合の実施例であり、半導体素子の厚みに
応じた異なる段差をもつリードフレームを用いている。
かかる方法によりAuワイヤを半導体素子部からリード部
に張る場合、高さがほぼ同じになることで組立が容易と
なり、封止用樹脂の厚みも薄くできる。また、第３図の
ように半導体素子搭載部として段差を設けながら、リー
ド部に対して傾きをもたせておくと、内部での乱反射光
が作用して誤動作を起す現象の顕著に軽減される効果が
ある。FIG. 2 shows an embodiment in which there are two semiconductor element mounting portions such as a hybrid element, and a lead frame having different steps depending on the thickness of the semiconductor element is used.
When the Au wire is stretched from the semiconductor element portion to the lead portion by such a method, the height is almost the same, which facilitates the assembling and the thickness of the sealing resin can be reduced. In addition, as shown in FIG. 3, when the semiconductor element mounting portion is provided with a step and is tilted with respect to the lead portion, the phenomenon of malfunction due to the diffused light internally reflected is remarkably reduced. There is.
本実施例のように半導体素子搭載部をリード部に対して
段差を設けて低くすることにより、封止用樹脂の肉厚を
容易に薄くすることができる。By making the semiconductor element mounting portion lower than the lead portion by providing a step as in the present embodiment, it is possible to easily reduce the thickness of the sealing resin.
発明の効果 以上のように、本発明による半導体用リードフレームを
用いることで容易に封止用樹脂を薄く、かつ、組立ても
容易にでき金属細線を最短にすることができる。EFFECTS OF THE INVENTION As described above, by using the semiconductor lead frame according to the present invention, the sealing resin can be easily thinned and can be easily assembled and the metal thin wire can be minimized.
第１図（ａ），（ｂ）第２図（ａ），（ｂ）および第３
図（ａ），（ｂ）は本発明の各実施例による半導体用リ
ードフレームを封止用樹脂で成型したときの平面図，断
面図、第４図（ａ），（ｂ）は従来例リードフレームを
封止用樹脂で成型したときの平面図，断面図である。 １……半導体素子搭載部、２……内部リード部、３……
外部リード部、４……半導体素子、５……封止用樹脂、
６……金属細線。1 (a), (b) 2 (a), (b) and 3
4A and 4B are a plan view and a cross-sectional view of a semiconductor lead frame according to each embodiment of the present invention molded with a sealing resin. FIGS. 4A and 4B are conventional leads. It is a top view and a sectional view when a frame is shape | molded with the resin for sealing. 1 ... Semiconductor element mounting part, 2 ... internal lead part, 3 ...
External lead, 4 ... Semiconductor element, 5 ... Sealing resin,
6 ... fine metal wire.
Claims (2)
た外部リードと、前記内部リードに設けた半導体素子搭
載部と、半導体素子上面と前記内部リードとを接続する
ワイヤと、前記半導体素子搭載部に少なくとも厚さの異
なる２以上の半導体素子を搭載して前記半導体素子上面
の少なくとも２以上がほぼ同一平面になる段差を有する
前記半導体素子搭載部とを設けたことを特徴とする半導
体装置。1. An internal lead, an external lead connected to the internal lead, a semiconductor element mounting portion provided on the internal lead, a wire connecting the upper surface of the semiconductor element and the internal lead, and the semiconductor element mounting. A semiconductor device, wherein at least two semiconductor elements having different thicknesses are mounted on the portion, and the semiconductor element mounting portion having a step in which at least two or more of the upper surface of the semiconductor element are substantially flush with each other is provided.
た外部リードと、前記内部リードに設けた半導体素子搭
載部と、半導体素子上面と前記内部リードとを接続する
ワイヤと、前記半導体素子搭載部の少なくとも一つをリ
ード部から段差を設けて下げ上方に傾け搭載した半導体
素子上面のワイヤ接続部分が、傾けてない半導体素子搭
載部に搭載された前記半導体素子上面とほぼ同一平面に
なるようにしたことを特徴とする半導体装置。2. An internal lead, an external lead connected to the internal lead, a semiconductor element mounting portion provided on the internal lead, a wire connecting the upper surface of the semiconductor element and the internal lead, and the semiconductor element mounting. At least one of the parts is provided with a step from the lead part and tilted upward so that the wire connection part on the upper surface of the semiconductor element is substantially flush with the upper surface of the semiconductor element mounted on the non-tilted semiconductor element mounting part A semiconductor device characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61230401A JPH0770676B2 (en) | 1986-09-29 | 1986-09-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61230401A JPH0770676B2 (en) | 1986-09-29 | 1986-09-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6384143A JPS6384143A (en) | 1988-04-14 |
| JPH0770676B2 true JPH0770676B2 (en) | 1995-07-31 |
Family
ID=16907301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61230401A Expired - Lifetime JPH0770676B2 (en) | 1986-09-29 | 1986-09-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770676B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582696A (en) * | 1991-09-19 | 1993-04-02 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
| JP7089995B2 (en) * | 2018-09-14 | 2022-06-23 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP7090579B2 (en) * | 2019-05-08 | 2022-06-24 | 三菱電機株式会社 | Semiconductor devices and their manufacturing methods |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5471569A (en) * | 1977-11-17 | 1979-06-08 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
| JPS5640265A (en) * | 1979-09-11 | 1981-04-16 | Nec Corp | Lead frame for semiconductor device |
| JPS56144566A (en) * | 1980-04-11 | 1981-11-10 | Hitachi Ltd | Lead frame and forming method therefor and semiconductor device using the same |
| JPS59146965U (en) * | 1983-03-23 | 1984-10-01 | 日本電気株式会社 | Lead frame for semiconductor devices |
| JPS60126841A (en) * | 1983-12-14 | 1985-07-06 | Hitachi Ltd | Metal mold for resin sealing |
-
1986
- 1986-09-29 JP JP61230401A patent/JPH0770676B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6384143A (en) | 1988-04-14 |
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