JPH0770686B2 - Complementary MIS semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] The present invention relates to a complementary MIS (Metal-Insulat) having high radiation resistance.
or-Semiconductor) relates to a semiconductor integrated circuit.

[Prior art and its problems]

Conventionally, in this type of semiconductor integrated circuit, element isolation is performed using a thick field oxide film.

However, when such a device is irradiated with radiation such as an electron beam, the flat band voltage remarkably changes due to the charge in the oxide film generated by the irradiation of the radiation and the interface state of the oxide film-semiconductor substrate, There is a drawback in that the so-called total dose resistance is lowered because the function of element isolation is significantly impaired.

Furthermore, in a space environment, high-energy heavy particles exist, and when these heavy particles enter a semiconductor integrated circuit, a large number of electron-hole pairs are generated in the semiconductor region. In the circuit, the generated charge triggers latch-up, which causes a problem that the circuit function is lost or the element is damaged.

In order to prevent the above latch-up, it is necessary to fill and separate the diffusion layer and the well interval. Therefore, if the latch-up resistance is increased, it becomes difficult to increase the integration density.
Therefore, it is difficult to realize a semiconductor integrated circuit having high latch-up resistance and high integration density.

As a solution to this problem, a method of using a low resistance substrate and an epitaxial layer grown thereon to improve the latch-up resistance by lowering the parasitic resistance can be considered, but the effect is not sufficient. Even if this method is used, the conventional element isolation technique using a thick field oxide film has a problem that the total dose resistance is still low.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a complementary MIS semiconductor integrated circuit with improved both total dose resistance and latch-up resistance. It is what

[Means for solving problems]

To achieve the above object, in the present invention, a complementary MI
In the S semiconductor integrated circuit device, a second gate electrode of the second conductivity type provided on the first semiconductor element formation region of the first conductivity type through an insulating film, and the first semiconductor element formation region A first shield plate electrode of a second conductivity type, which is provided on the first element isolation region in the semiconductor device via an insulating film and which applies a first voltage, and a second conductivity type second shield plate electrode. A second gate electrode of the second conductivity type provided on the semiconductor element formation region via an insulating film, and provided on the second element isolation region in the second semiconductor element formation region via an insulating film. And a second shield plate electrode of a second conductivity type for applying a second voltage, wherein the at least one of the first and second shield plate electrodes is the first and the second shield plate electrodes. 2 is provided in the groove provided in at least one element isolation region via an insulating film. And the groove electrodes 2 of the conductivity type, and having electrically connects the impurity-doped region of the second conductivity type provided on the periphery of an opening of the groove.

[Action]

With the above configuration, the shield plate electrode of the MIS structure formed in the element isolation region on the semiconductor element formation region improves the total dose resistance and the parasitic gap formed between each element. Since the groove with the transistor is blocked and the positive feedback action between the parasitic transistors is hindered, the latch-up resistance can be improved.

Further, since the above-mentioned groove electrode and the diffusion layer have the same potential, the problem caused by the insulation resistance of the insulating film is prevented, and further, a positive charge is generated in the insulating film due to the irradiation of the electron beam or the like. When the inversion layer is formed around the groove by the charge, the inversion layer and the diffusion layer have the same potential,
The potential difference does not occur in the insulating film sandwiched between the inversion layer and the groove electrode, and the problem caused by the insulation resistance of the insulating film in this portion can be prevented.

The details will be described below with reference to the drawings.

〔Example〕

 FIG. 1 is a sectional view of the first embodiment of the present invention.

In FIG. 1, 1 is a semiconductor element formation region of p-type silicon, 2 is a semiconductor element formation region of n-type silicon, 3 is a gate oxide film, 4 and 5 are shield plate electrodes of n-type polysilicon, and 6 and 7. Is an n-type polysilicon gate electrode, 8
Is a silicon oxide film, 9 is an n-type polysilicon groove electrode, 1
0, 11 and 12 are n ⁺ diffusion layers, 13 is a p ⁺ diffusion layer, and V ₁ , V ₂
And V ₂ 'are each a predetermined voltage.

As shown in FIG. 1, the element isolation region includes shield plate electrodes 4 and 5 formed of n-type polysilicon.
It is composed of an S structure, and a predetermined voltage V is applied to the electrode 4.
₂ is applied, and a predetermined voltage V ₁ is applied to the electrode 5. Since the p-type semiconductor region and the n-type semiconductor region can be prevented from forming an inversion layer by the MIS structure, the oxide film 3 can be thinned to several hundred Å or less, and thus the total dose for radiation is reduced. The withstand amount can be improved.

Further, in the configuration of FIG. 1, a semiconductor element forming region 2 of n-type silicon and a semiconductor element forming region 1 of p-type silicon are provided.
A groove is formed so as to include the boundary of the silicon oxide film, a silicon oxide film 8 is formed as an insulating film on the inner wall surface of the groove, and the inside of the silicon oxide film 8 is filled with n-type polysilicon 9 to form an n-type polysilicon film. It is electrically connected to the shield plate electrode 5 made of silicon and is applied with a predetermined voltage V ₁ . In this case, regarding the latch-up problem due to irradiation of high-energy heavy particles, a parasitic lateral npn transistor formed by the n ⁺ diffusion layer 12, the p-type silicon semiconductor element formation region 1 and the n-type silicon semiconductor element formation region 2 And p ⁺ diffusion layer 13, n
The groove between the semiconductor element forming region 2 of p-type silicon and the parasitic vertical pnp transistor formed in the semiconductor element forming region 1 of p-type silicon blocks the positive feedback action of both transistors. Latch-up resistance can be improved.

Further, in the configuration of FIG. 1, the n-type diffusion layer 11 formed around the opening of the groove in the semiconductor element formation region 2 of n-type silicon and the groove of the groove in the semiconductor element formation region 1 of p-type silicon. The n-type diffusion layer 10 formed around the opening is the MI of the groove inner surface.
The groove electrode 9 of the S structure and the shield plate electrode 5 of the n-type polysilicon of the MIS structure forming the element isolation region on the semiconductor element formation region 2 of the n-type silicon are electrically connected to each other, and the predetermined voltage V ₁ Is being applied. In this example, n ⁺
The diffusion layers 10 and 11 are made of n-type polysilicon without adding a special process such as ion implantation. That is, if a part of the gate oxide film 3 in a predetermined region is removed before the shield plate electrode 5 is formed, it is included in the step of forming the source / drain layer after the shield plate electrode 5 is formed. By the heat treatment step, n-type impurities are diffused from the n-type polysilicon of the shield plate electrode 5 into the semiconductor element forming regions 1 and 2. By having a n ⁺ diffusion layer 10 and 11, n ⁺ diffusion layers 10 and 11
Since the n-type semiconductor element forming region 2 and the groove electrode 9 have the same potential, the oxide film 8 sandwiched between the groove electrode 9 and the n ⁺ diffusion layer 10
Since no voltage difference occurs between the groove electrode 9 and the oxide film 8 sandwiched between the n-type silicon region 2 and the n ⁺ diffusion layer 11, the problem caused by the insulation resistance of the oxide film in this portion is prevented. Also,
A positive charge is generated in the oxide film 8 by irradiation with radiation such as an electron beam. When this charge forms an inversion layer around the groove of the p-type semiconductor element formation region 1, the inversion layer and p Since the n ⁺ diffusion layer 10 in the semiconductor element formation region 1 of the rectangular shape has the same potential, the oxide film 8 sandwiched between the inversion layer and the groove electrode 9 is formed.
Since there is no potential difference between the two, the problem caused by the insulation resistance of the oxide film in this portion is also prevented.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

In FIG. 2, 14 is a p-type low resistance silicon substrate, and 15 is a p-type epitaxial silicon layer.

The present embodiment is a case where the present invention is applied as a semiconductor element forming region using a p-type epitaxial layer grown on a p ^{+ +} -type substrate. In this case, since the parasitic resistance is reduced by the effect of the low resistance substrate 14, the latch-up resistance is further improved together with the effect of the groove separation described in the first embodiment. This improvement effect depends on the depth of the groove, and considering the impurity diffusion from the resistance substrate 14 to the epitaxial growth layer 15 due to the heat treatment during the process, the depth of the groove is 40% or more deeper than the thickness of the epitaxial growth layer. It is necessary to.

FIG. 3 is a sectional view showing a third embodiment of the present invention. In the structure of this embodiment, the n ⁺ diffusion layer 10 in FIG. 2 is omitted. That is, if there is no problem in the breakdown voltage of the oxide film 8 on the inner wall of the groove, the n ⁺ diffusion layer 10 in FIG. 2 can be omitted as in FIG. 3, thereby forming a high density integrated circuit. can do.

FIG. 4 is a sectional view showing a fourth embodiment of the present invention. Up to now, the groove having the oxide film 8 on the inner wall and filled with the n-type polysilicon 9 is arranged so as to include the boundary between the semiconductor element forming region 1 of p-type silicon and the semiconductor element forming region 2 of n-type silicon. However, in FIG. 4, it is arranged under another shield plate electrode, and
The type polysilicon electrode 9 is electrically connected to the shield plate electrode 4 of n type polysilicon, and a predetermined voltage V ₂ is applied thereto. In this way, by frequently using the groove separation, the latch-up resistance is further improved. Further, as shown in FIG. 4, also in the present embodiment, such a groove separation is provided in the semiconductor element forming region 2 of the n-type silicon.
Since it is provided below the plate electrode 5, the groove electrode 9 is electrically connected to the shield plate electrode 5, and the predetermined voltage V ₁ is applied, it is said that this also improves the latch-up resistance. There is no end.

Although the embodiment of the present invention has been described with the structure using the n-well, it is needless to say that the present invention can be applied to the structure using the p-well or the structure using both wells. Further, the present invention can be implemented whether the low resistance semiconductor region 14 is n-type or p-type. Further, the material of the gate electrode and the shield plate electrode of the MOSFET can have a so-called polycide structure in which a metal material is laminated on polysilicon in order to reduce the resistance.

〔The invention's effect〕

As described above, according to the present invention, since the shield plate electrode is provided, the oxide film can be thinned, the total dose resistance due to radiation irradiation can be improved, and the trench can be formed in the element isolation region. By providing the above, it is possible to improve the latch-up resistance.

Further, by partially removing the gate oxide film on the surface of the semiconductor element formation region around the groove and diffusing impurities from the shield plate electrode member to provide the semiconductor element formation region surface and the high impurity concentration layer, The resistance of the oxide film inside the groove can be improved.

Further, since the shield plate electrode and the gate electrode have the same conductivity type, there is an effect that the step of introducing impurities into the electrode material is simple.

[Brief description of drawings]

1 to 4 are sectional views showing an embodiment of the present invention. 1 ... p-type silicon semiconductor element formation region 2 ... n-type silicon semiconductor element formation region 3 ... gate oxide film 4, 5 ... n-type polysilicon shield plate electrode 6,7 ... n-type poly Silicon gate electrode 8 …… Silicon oxide film 9 …… N type polysilicon groove electrode 10, 11, 12 …… n ⁺ Diffusion layer 13 …… p ⁺ Diffusion layer 14 …… P type low resistance silicon substrate 15… … P-type epitaxial silicon layer V ₁ , V ₂ , V ₂ ′ …… Predetermined voltage

Claims (1)

[Claims] 1. In a complementary MIS semiconductor integrated circuit device, a first gate electrode of a second conductivity type provided on a first semiconductor element formation region of the first conductivity type with an insulating film interposed therebetween, A first shield plate electrode of a second conductivity type which is provided on the first element isolation region in the first semiconductor element formation region via an insulating film and which applies a first voltage; A second gate electrode of the second conductivity type provided on the second semiconductor element formation region of the second conductivity type via an insulating film, and a second element isolation region in the second semiconductor element formation region. And a second shield plate electrode of a second conductivity type for applying a second voltage, the shield plate electrode being at least one of the first and second shield plate electrodes. In the groove provided in the at least one of the first and second element isolation regions, A second conductivity type groove electrode provided via an edge film and a second conductivity type impurity-doped region provided around the opening of the groove are electrically connected to each other, and the complementary MIS semiconductor integrated circuit device.