JPH0770691B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Field of Application> The present invention relates to a read-only semiconductor memory device (hereinafter referred to as “EP
ROM for short).

<Prior Art> Conventionally, as this kind of EPROM, there is one having a memory cell array as shown in FIG. 6 or FIG.

The memory cell array shown in FIG. 6 is provided with a drain diffusion line 83 in the column direction formed by diffusing N-type impurities and a source diffusion line 84 parallel thereto, and a floating gate 82 between the two diffusion lines and the above-mentioned diffusion line. By providing word lines 85 in the row direction on the floating gates 82, the memory cells 81 are formed by one floating gate type transistor, and such memory cells are arranged in a matrix. Note that one drain diffusion line is also used as a source diffusion line of memory cells adjacent in the row direction so that the chip area can be reduced.

The memory cell array shown in FIG. 7 includes a pair of parallel source diffusion lines 94 and 104 in the row direction formed by diffusing N-type impurities, and an island-shaped drain diffusion region 93 between the diffusion lines. , Between the drain diffusion region 93 and the source diffusion lines 94, 104, respectively.
02 and word lines 95 and 105 respectively thereon, the drain diffusion region 93 is connected to the bit line 97 at the contact portion 96, and the source diffusion lines 94 and 104 are connected to the source line 98 in the column direction at the contact portions 99 and 100. By doing so, a pair of memory cells 91 and 101 are formed in the column direction, and such a pair of memory cells are arranged in a matrix. Note that the source diffusion lines of the pair of memory cells are also used for the memory cells adjacent in the column direction so that the chip area can be reduced.

<Problems to be Solved by the Invention> By the way, in general, the access time of an EPROM is the delay time of the input buffer unit, the delay time of the address decoder unit,
It is determined by the sum of the delay time in the word line, the delay time in the bit line, the delay time in the sense-up unit, and the delay time in the output buffer unit. Of these, the influence of the delay time in the word line and the delay time in the bit line is particularly large, and the bit line delay time at the time of reading usually reaches 30 to 40% of the total access time. Letting the total resistance of the bit line resistance R ″ from the EPROM cell on-resistance R ′ and the read-out EPROM cell to the sense-up be the total capacitance of the bit line is C, the data read time from the bit line is proportional to the product CR. To do.

The conventional EPROM shown in FIG. 6 has a small memory cell size, but since it has a long drain diffusion line 83 as a bit line that is approximately equal to the entire length of the memory cell in the column direction, it has a bit line capacitance C and a bit line resistance R ″ gets bigger,
There is a drawback that the access time becomes long enough to cause a practical problem.

On the other hand, in the EPROM shown in FIG. 7, since the drain diffusion region 93 is isolated in an island shape, the diffusion capacitance is small and the access time is short, but compared with the memory cell shown in FIG. However, since the structure of the memory cell is complicated, there is a drawback in that the cell size becomes large and the chip area becomes large from the viewpoint of design rules.

Therefore, an object of the present invention is to provide an EPROM having a small chip area and a short access time.

<Means for Solving the Problems> In order to achieve the above object, the present invention provides a memory cell array in which nonvolatile memory cells composed of floating gate type transistors are arranged in a matrix, and a word line and a bit line of the memory cell array, respectively. In a semiconductor memory device including a word line selection circuit and a bit line selection circuit for selection, one column of the memory cell array includes a plurality of segment columns, and each segment column includes a segment column selection line and A column-direction drain diffusion line connected to the drain region of the floating gate type transistor of the memory cell included in the segment column is provided, and the drain diffusion lines arranged in the row direction are connected to the bit line via the transfer gate transistor. , Each of the above transfers lined up in the row direction The gate of the gate transistor is connected to the segment column selection line, and the word line selection circuit selects the segment column so as to select one segment column from the plurality of segment columns according to the received address input signal. A segment column selection circuit that outputs a segment column selection signal to a line, and one word line is selected from a plurality of word lines included in each segment column by the received address input signal,
It is characterized in that a segment word line selection circuit for transmitting a word line selection signal to the word lines included in each segment column in parallel is provided for each segment column.

<Operation> The segment column selection circuit receives the address input signal, selects the segment column including the target memory cell by the address input signal, and applies the segment column selection signal to the segment column selection line of the segment column. Output. Then, each transfer gate transistor connected to the segment column selection line is turned on by the segment column selection signal, and each drain diffusion line arranged in the row direction is electrically connected to the bit line. Further, at the same time, the segment word line selection circuit is included in each segment column in parallel in parallel with each segment column so that one word line is selected from the plurality of word lines included in each segment column. The word line selection signal is sent to the selected word line. As a result, the data of the memory cells arranged in the row direction controlled by one word line of the segment column selected by the segment column selection circuit is output to each bit line. Then, the bit line selection circuit selects the bit line to which the data of the target memory cell is output so that the data can be read.

When reading is performed in this manner, it is the diffusion capacitance of the drain diffusion line divided for each segment column that contributes to the access time of this EPROM. The access time becomes shorter than that in the case of the drain diffusion line having a length substantially equal to the total length of the memory cell array in the column direction.

In addition, since the drain diffusion line in the column direction to which the drain region of the memory cell is connected is provided, the structure of the memory cell is simpler than that of the conventional drain region isolated in an island shape, and the cell size is reduced. It becomes possible to reduce.

When writing data to this EPROM, the word line that controls the target memory cell is selected, the programmable voltage is applied to this word line, and the data to be written is written to the bit line by the same procedure as for reading. And apply it.

<Embodiment> An EPROM of the present invention will be described in detail below with reference to the embodiments shown in the drawings.

This EPROM has a storage capacity of 256K (512
(Row, 512 columns) memory cell array 1, a word line selection circuit 2 for selecting a word line of the memory cell array 1, and a bit line selection circuit 9 for selecting a bit line of the memory cell array 1.

As shown in FIG. 2, the memory cell array 1 includes eight segment columns i (i = 0,
It is divided into 1, ..., 7). Each segment column i above
Is a drain diffusion line 12 in the column direction in which the drain regions of the floating gate type transistor having the floating gate 11a and the control gate 11b are connected by 64, and a source diffusion in the column direction in which the source regions of the transistor are connected by 64. line
It has 13 and. The drain diffusion line 12 and the source diffusion line 13 are bit lines at contact portions 18 and 19 via transfer gate transistors 14 and 15, respectively.
16 and the virtual ground line 17. The gates of the transfer gate transistors 14 and 15 are formed integrally with the segment column selection line 20 in the row direction made of polysilicon. The word line 21 is made of polysilicon and is formed integrally with the control gate 11b. In this way, one column is composed of eight segment columns consisting of 64 memory cells, and the segment columns are arranged in 512 rows in the row direction. The drain diffusion line and the bit line of one segment column are also used as the source diffusion line and the virtual ground line of 64 memory cells in the segment column adjacent to the right. Therefore, the equivalent circuit of this segment column i becomes a circuit as shown in FIG.

As shown in FIG. 4, the word line selection circuit 2 comprises a segment column selection circuit 3 and a segment word line selection circuit 4. The segment column selection circuit 3 is
Input signals A13, A14, from the address buffer 50 shown in FIG.
Receives and decodes A15, and signals B0, B1, B2, B3, B4, B
This circuit generates 5, B6, B7. The signal Bi (i = 1,2,
, 7) are sent to the segment column selection line of each segment column of the memory cell array.

The segment word line selection circuit 4 receives the input signals A6, A7 from the address buffer 50 and decodes them to generate the signals u0, u1, u2, u3, and the input signals A8, A9. And decode and signal v0, v1, v2, v3
V decoder 7 for generating, W decoder 8 for receiving and decoding input signals A10, A11, A12 to generate signals w0, w1, w2, w3, w4, w5, w6, w7, and U decoder 6, V decoder
7. Signals u0 to u3, v0 to v3, w0 to w7 from the W decoder 8 respectively
Word line select signals WL0, WL1
.., WL61, WL62, and R63 for generating WL63. The word line selection signal WLj (j = 0,1, ..., 63)
Are simultaneously transmitted to each segment column and are respectively sent to 64 word lines in the segment.

As shown in FIG. 1, the bit line selection circuit 9 receives the input signals A0, A1 and A2 from the address buffer 50 and decodes them to generate Y0, Y1, ..., Y7 signals. And a Y selector 62 which receives the signals Y0 to Y7, and BS0, BS1, ..., B which receives and decodes the input signals A3, A4, A5.
BS predecoder 61 that generates each signal of S7 and the above signal BS
The BS selector 63 receives 0 to BS7. Above Y
The selector 62 and the BS selector 63 consist of 64 sets of transfer gate transistors shown in FIG. Then, eight sets corresponding to k = 0, ..., 7 in the assembly shown in FIG. 5 are connected to one data terminal Dl shown in FIG. This EPROM has eight data terminals Dl (corresponding to l = 0, 1, ..., 7). The Y selector 62 and the BS selector 63 receive the signals Y0 to Y7 and BS0 to BS7, and output from the 512 bit lines of the memory cell array 1 to the eight bit lines corresponding to the number of the data terminals Dl. Select. At this time, the bit line adjacent to the left of the selected bit line is grounded, and the source diffusion line of the memory cell is grounded (virtual ground method).

This EPROM operates as follows when reading the stored data.

Address input terminals A _0, A _1, ... if each address input signal A ₁₅ is applied, through address buffer 50,
The input signals A _{13 to} A ₁₅ are input to the segment column selection circuit 3
Applied to. The segment column selection circuit 3 decodes the input signals A _{13 to} A ₁₅ to decode a target memory cell,
For example, the segment column i including the memory cell 11 shown in FIG. 2 is selected, and the segment column selection signal Bi is applied to the segment column selection line 20 of the segment column i.
Is sent. Then, in the segment column i, the transfer gate transistors 18 and 19 connected to the segment column selection line Bi are turned on, and the drain diffusion line 12 and the source diffusion line 13 shown in FIG. It is electrically connected to the lines 16 and 17 (note that other drain diffusion lines (not shown) arranged in the row direction are also electrically connected to the respective bit lines). At the same time, the segment word line selection circuit 4 receives the input signals A _{6 to} A ₁₂ from the address buffer 50, decodes them, and selects one word from the 64 word lines included in each segment column. A word line selection signal WLj (j = 0,1,2, ..., 63) is sent to 64 word lines included in each segment column simultaneously in parallel so as to select a line. . As a result, for example, the data in the memory cell controlled by one word line 21 of the segment column i selected by the segment column selection circuit 3 is output to the bit line 16. The bit line selection circuit 9 receives the input signal from the address buffer 50.
Receives and decodes A0-A5 to target memory cell 11
The data line D1 (l = l) is selected through the sense up / output buffer 70 by selecting the bit line 16 to which the data of
Output to any of 0,1, ..., 7). In addition, virtual ground wire 17
The wires are grounded at the same time.

Thus, when reading is performed, it is the diffusion capacitance C ₁ of the drain diffusion line 12 divided into each segment column as shown in FIG. 3 that contributes to the access time of this EPROM. Therefore, as compared with the conventional drain diffusion line having a length substantially equal to the total length of the memory cell array in the column direction as shown in FIG.
Since the diffusion resistance can be reduced at the same time, the access time can be shortened.
Further, since the drain region of the memory cell is provided with the drain diffusion lines connected in the column direction, the memory cell array is different from the case of the conventional drain region isolated in the island shape as shown in FIG. The structure is simplified, and the cell size can be reduced.

When writing data to a memory cell, this EPROM is performed by applying input data to the data terminals Dl (l = 0, 1, ..., 7) and putting the EPROM in a write mode. In the EPROM, when the write mode is entered, the write control circuit 72 shown in FIG.
(Program mode) signal is output. The PGM signal causes the power supply switching circuit 73 to operate, and 12V is applied as the power supply for the data input circuit 71, the word line selection circuit 2, and the bit line selection circuit 9 (5V at the time of reading). At the same time, the PGM signal causes the input data applied to the data terminal by the data input circuit 71 to be converted into a 12V signal and applied to the bit line. Also, for the selected word line,
12V is applied. Here, the method of selecting the bit line and the word line is the same as that at the time of reading, and therefore the description is omitted.

When the "LOW" signal is applied to the data terminal Dl,
12V is applied to the bit line. High voltage is applied to the gate and drain of the selected memory cell to perform writing. The threshold voltage of the written memory cell rises to 5 V or more and is always in the off state, and the "LOW" signal is output to the data terminal Dl at the time of reading.

On the other hand, when the "HIGH" signal is applied to the data terminal Dl, 0V is applied to the bit line. 12V is applied to the gate of the selected memory cell, but the bit line is 0
No data is written because it is held at V. The threshold voltage of the memory cell which is not written is kept at 1 V or less and is always on, and at the time of reading, it is in the state of outputting the “HIGH” signal to the terminal Dl.

<Effects of the Invention> As is clear from the above, the EPROM of the present invention is provided with the drain diffusion lines in which the drain regions of the floating gate transistors of the memory cells are connected in the column direction, and the drain diffusion lines are provided for each segment column. Since the divided drain diffusion line is connected to the bit line via the transfer gate transistor, the access time can be shortened and the chip area can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an EPROM of the present invention, FIG. 2 is a diagram showing a structure of a memory cell array of the EPROM, FIG. 3 is a circuit diagram showing an equivalent circuit of the memory cell array, and FIG. Is a block diagram showing a configuration of a word line selection circuit of the EPROM, FIG. 5 is a circuit diagram showing an equivalent circuit of a Y selector and a BS selector which are a part of the bit line selection circuit of the EPROM, FIG. 6, and FIG. The figure shows the structure of a memory cell array of a conventional EPROM. 1 ... Memory cell array, 2 ... Word line selection circuit, 3
...... Segment column selection circuit, 4 ... Segment word line selection circuit, 5 ... R decoder, 6 ... U decoder,
7 ... V decoder, 8 ... W decoder, 9 ... bit line selection circuit, 11 ... memory cell, 11a ... floating gate, 11b
...... Control gate, 12 …… Drain diffusion line, 13 …… Source diffusion line, 14,15 …… Transfer gate transistor, 16 …… Bit line, 17 …… Virtual ground line, 18,19…
… Contact part, 20 …… Segment column selection line, C ₁ …
… Diffusion capacity, 50 …… Address buffer, 60 …… Y predecoder, 61 …… BS predecoder, 62 …… Y selector, 63
...... BS selector, 70 …… Sense amplifier / output buffer,
71 ... Data input circuit, 72 ... Write control circuit, 73 ...
… Power supply switching circuit, A ₀ , A ₁ ,…, A ₁₅ …… Address input terminal, D ₀ , D ₁ ,…, D ₇ …… Data terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (1)

[Claims] 1. A semiconductor comprising a memory cell array in which nonvolatile memory cells composed of floating gate type transistors are arranged in a matrix, and a word line selection circuit and a bit line selection circuit for selecting a word line and a bit line of the memory cell array, respectively. In the memory device, one column of the memory cell array includes a plurality of segment columns, each of the segment columns includes a segment column selection line, and a drain region of a floating gate transistor of a memory cell included in the segment column. A drain diffusion line in the column direction connected to each other, each drain diffusion line arranged in the row direction is connected to a bit line via a transfer gate transistor, and the gates of the transfer gate transistors arranged in the row direction are connected to each other. Above segment column Connected to a selection line, the word line selection circuit outputs a segment column selection signal to the segment column selection line so as to select one segment column from the plurality of segment columns according to the received address input signal. Included in each segment column in parallel so that one word line is selected from among the plurality of word lines included in each segment column by the segment column selection circuit and the received address input signal. A semiconductor memory device comprising a segment word line selection circuit for transmitting a word line selection signal to a selected word line.