JPH0770728B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0770728B2 JPH0770728B2 JP1296912A JP29691289A JPH0770728B2 JP H0770728 B2 JPH0770728 B2 JP H0770728B2 JP 1296912 A JP1296912 A JP 1296912A JP 29691289 A JP29691289 A JP 29691289A JP H0770728 B2 JPH0770728 B2 JP H0770728B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- channel stopper
- region
- stopper region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は半導体装置の製造方法に、特にLOCOS酸化膜に
よる素子間分離に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more particularly to element isolation using a LOCOS oxide film.
（ロ）従来の技術 第３図に従来のLOCOS酸化膜を用いた素子間分離方法を
説明する。なお先行技術としては特開昭63−194346号公
報（H01L 21/76）等が知られている。(B) Conventional Technology FIG. 3 illustrates a conventional element isolation method using a LOCOS oxide film. As a prior art, JP-A-63-194346 (H01L 21/76) and the like are known.
第３図Ａに示す如く、Ｐ型のシリコン半導体基板（21）
の所定のフィールド領域に周知の選択酸化法によりLOCO
S酸化膜（22）を形成し、このLOCOS酸化膜（22）下には
P+型のチャンネルストッパ領域（23）を形成している。
なお素子領域（24）上のゲート酸化膜（25）にはポリシ
リコンより成るゲート電極（26）が形成されている。As shown in FIG. 3A, a P type silicon semiconductor substrate (21)
LOCO to the prescribed field area of the
S oxide film (22) is formed, and under this LOCOS oxide film (22)
A P + type channel stopper region (23) is formed.
A gate electrode (26) made of polysilicon is formed on the gate oxide film (25) on the element region (24).
次に第３図Ｂに示す如く、ゲート電極（26）をマスクと
してヒ素をイオン注入してN+型のソースドレイン領域
（27）（28）をセルフアラインにより形成している。Next, as shown in FIG. 3B, arsenic is ion-implanted using the gate electrode (26) as a mask to form N + type source / drain regions (27) and (28) by self-alignment.
しかしながら斯る従来の素子間分離方法ではチャンネル
ストッパ領域（23）がLOCOS酸化膜（22）の側面まで広
がり、ソースドレイン領域（27）（28）と隣接する。こ
のため第４図の上面図から明らかな様に、チャンネルス
トッパ領域（23）がゲート電極（26）下で点線で示す様
にチャンネル領域（29）内へはみ出してチャンネル幅を
小さく、狭チャンネル効果を生じる欠点を有していた。However, in such a conventional element isolation method, the channel stopper region (23) extends to the side surface of the LOCOS oxide film (22) and is adjacent to the source / drain regions (27) and (28). Therefore, as is apparent from the top view of FIG. 4, the channel stopper region (23) protrudes into the channel region (29) under the gate electrode (26) as shown by the dotted line to reduce the channel width and narrow channel effect. It had the drawback of causing
（ハ）発明が解決しようとする課題 本発明は斯る欠点に鑑みてなされ、狭チャンネル効果が
小さく且つ素子分離能力の高い半導体装置の製造方法を
提供するものである。(C) Problem to be Solved by the Invention The present invention has been made in view of the above drawbacks, and provides a method of manufacturing a semiconductor device having a small narrow channel effect and a high element isolation capability.
（ニ）課題を解決するための手段 本発明に依れば、不純物濃度の高い埋め込みチャンネル
ストッパ領域を斜めイオン注入により形成することによ
り狭チャンネル効果を抑制した半導体装置の製造方法を
実現している。(D) Means for Solving the Problems According to the present invention, a method for manufacturing a semiconductor device in which a narrow channel effect is suppressed is realized by forming a buried channel stopper region having a high impurity concentration by oblique ion implantation. .
（ホ）作 用 本発明では、LOCOS酸化膜（４）下に設けるチャンネル
ストッパ領域（３）の不純物濃度を低く設定し、斜めイ
オン注入により高い不純物濃度の埋め込みチャンネルス
トッパ領域（10）をLOCOS酸化膜（４）の側面下に形成
しているので、ゲート電極（７）下でのチャンネルスト
ッパ領域（３）および埋め込みチャンネルストッパ領域
（10）のはみ出しを最少限に抑制でき、チャンネル幅を
狭くすることを防止している。(E) Operation In the present invention, the impurity concentration of the channel stopper region (3) provided below the LOCOS oxide film (4) is set low, and the buried channel stopper region (10) having a high impurity concentration is LOCOS oxidized by oblique ion implantation. Since it is formed under the side surface of the film (4), the protrusion of the channel stopper region (3) and the buried channel stopper region (10) under the gate electrode (7) can be suppressed to a minimum and the channel width can be narrowed. To prevent that.
（ヘ）実 施 例 第１図および第２図を参照して本発明の実施例を詳述す
る。(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.
第１図Ａに示す様に、Ｐ型シリコン基板（１）のフィー
ルド領域（２）にボロンをイオン注入してチャンネルス
トッパ領域（３）を形成し、周知の選択酸化法によりLO
COS酸化膜（４）を形成する。この工程でボロンのイオ
ン注入はドーズ量を通常の４×1013cm-2から1.5×1013c
m-2加速エネルギー60KeVで行い、チャンネルストッパ領
域（３）の不純物濃度を通常の半分以下に抑えて、LOCO
S酸化膜（４）の側面へのはみ出しを大幅に抑制してい
る。As shown in FIG. 1A, boron is ion-implanted into a field region (2) of a P-type silicon substrate (1) to form a channel stopper region (3), and LO is formed by a known selective oxidation method.
COS oxide film (4) is formed. In this step, boron ion implantation is performed at a dose of 4 × 10 13 cm -2 to 1.5 × 10 13 c
m −2 acceleration energy is 60 KeV and the impurity concentration in the channel stopper region (3) is suppressed to less than half of the normal level, and LOCO
The protrusion to the side surface of the S oxide film (4) is significantly suppressed.
更に素子領域（５）のゲート酸化膜（６）上にはポリシ
リンコン成るゲート電極（７）を形成している。Further, a gate electrode (7) made of polysilicon is formed on the gate oxide film (6) in the device region (5).
次に第１図Ｂに示す如く、ゲート電極（７）をマスクと
してセルフアラインによりヒ素をイオン注入してN+型の
ソースドレイン領域（８）（９）を形成する。このイオ
ン注入は加速エネルギー60KeV、ドーズ量５×1015cm-2
で行う。Next, as shown in FIG. 1B, arsenic is ion-implanted by self-alignment using the gate electrode (7) as a mask to form N + type source / drain regions (8) and (9). This ion implantation has an acceleration energy of 60 KeV and a dose of 5 × 10 15 cm -2.
Done in.
次に第１図Ｃに示す如く、ボロンイオンを斜めイオン注
入して埋め込みチャンネルストッパ領域（10）を形成す
る。本工程は本発明の最も特徴とする工程であり、ボロ
ンを30〜40゜傾けて、加速エネルギー80KeV、ドーズ量
３×1012cm-2で回転イオン注入装置でイオン注入をして
いる。このため第１図Ｃに点線で示す如く、ソースドレ
イン領域（８）（９）の両端に突出してボロンイオンが
注入される。Next, as shown in FIG. 1C, boron ions are obliquely ion-implanted to form a buried channel stopper region (10). This step is the most characteristic step of the present invention, in which boron is tilted at 30 to 40 °, and ion implantation is performed by a rotary ion implantation apparatus with an acceleration energy of 80 KeV and a dose amount of 3 × 10 12 cm -2 . Therefore, as shown by the dotted line in FIG. 1C, boron ions are implanted so as to project at both ends of the source / drain regions (8) and (9).
更に第１図Ｄに示す如く、950℃、40分でアニールを行
うと、ソースドレイン領域（８）（９）のLOCOS酸化膜
（４）と接する外側にP+型の埋め込みチャンネルストッ
パ領域（10）が形成され、チャンネル領域（11）に接す
るソースドレイン領域（８）（９）の内側にはP+型のポ
ケット領域（12）が形成される。Further, as shown in FIG. 1D, when annealing is performed at 950 ° C. for 40 minutes, a P + -type buried channel stopper region (10) is formed outside the source / drain regions (8) and (9) in contact with the LOCOS oxide film (4). ) Is formed, and a P + type pocket region (12) is formed inside the source / drain regions (8) and (9) in contact with the channel region (11).
第２図に本発明の上面図を示す。斜線部はLOCOS酸化膜
（４）のあるフィールド領域（２）を示し、点線で示す
部分まで埋め込みチャンネルストッパ領域（10）が形成
される。ゲート電極（７）下には埋め込みチャンネルス
トッパ領域（10）は形成されないが、チャンネルストッ
パ領域（３）が通常のものより低不純物濃度に設定され
るのでチャンネル領域（11）へのチャンネルストッパ領
域（３）のはみ出しを最少限に抑制できる。また素子領
域（５）間は高不純物濃度の埋め込みチャンネルストッ
パ領域（10）で分離されているので、通常のものと同様
の素子間分離を実現できる。FIG. 2 shows a top view of the present invention. The hatched portion indicates the field region (2) having the LOCOS oxide film (4), and the buried channel stopper region (10) is formed up to the portion indicated by the dotted line. Although the buried channel stopper region (10) is not formed under the gate electrode (7), the channel stopper region (3) is set to have a lower impurity concentration than usual, so that the channel stopper region (11) to the channel region (11) is formed. The protrusion of 3) can be suppressed to a minimum. Further, since the element regions (5) are separated by the buried channel stopper region (10) having a high impurity concentration, the element separation similar to the usual one can be realized.
（ト）発明の効果 本発明に依れば、ボロンの回転斜めイオン注入によりP+
型の埋め込みチャンネルストッパ領域（10）をソースド
レイン領域（８）（９）とLOCOS酸化膜（４）との間に
形成できるので、チャンネルストッパ領域（３）を通常
より低不純物濃度に形成できチャンネル領域（11）への
チャンネルストッパ領域（３）のはみ出しを抑制でき狭
いチャンネル効果を防止できる。(G) Effect of the Invention According to the present invention, P + is produced by rotating oblique ion implantation of boron.
Since the buried channel stopper region (10) of the mold can be formed between the source / drain regions (8) and (9) and the LOCOS oxide film (4), the channel stopper region (3) can be formed with a lower impurity concentration than usual. The protrusion of the channel stopper region (3) into the region (11) can be suppressed and the narrow channel effect can be prevented.
また本発明では、埋め込みチャンネルストッパ領域（1
0）と同時にポケット領域（12）を形成でき、ソースド
レイン間のパンチスルー耐圧を向上できる利点を有す
る。In the present invention, the buried channel stopper region (1
At the same time, the pocket region (12) can be formed and the punch-through breakdown voltage between the source and drain can be improved.
更に本発明では、ボロンを斜めイオン注入することによ
り浅くイオン注入でき、ソースドレイン領域（８）
（９）下面にイオン注入でＰ型領域を形成されないの
で、PN接合容量の増加も防止できる。Further, according to the present invention, boron can be shallowly ion-implanted by obliquely ion-implanting the source-drain region (8).
(9) Since a P-type region is not formed on the lower surface by ion implantation, an increase in PN junction capacitance can be prevented.
第１図は本発明に依る半導体装置の製造方法を説明する
断面図、第２図は本発明による半導体装置を説明する上
面図、第３図および第４図は従来方法を説明する断面図
および上面図である。FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a top view illustrating a semiconductor device according to the present invention, and FIGS. 3 and 4 are cross-sectional views illustrating a conventional method. It is a top view.
Claims (2)
置の製造方法において、 前記LOCOS酸化膜下に通常の素子間分離に必要な不純物
濃度より低い一導電型のチャンネルストッパ領域を形成
する工程と、 前記LOCOS酸化膜に隣接して逆導電型のソースあるいは
ドレイン領域を形成る工程と、 前記LOCOS酸化膜に隣接して斜めイオン注入により前記
チャンネルストッパ領域より濃度の高い埋め込みチャン
ネルストッパ領域を形成する工程とを具備することを特
徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which elements are isolated from each other by a LOCOS oxide film, a step of forming a channel stopper region of one conductivity type under the LOCOS oxide film, the impurity concentration being lower than an impurity concentration required for normal element isolation. Forming a source or drain region of opposite conductivity type adjacent to the LOCOS oxide film, and forming a buried channel stopper region having a higher concentration than the channel stopper region by oblique ion implantation adjacent to the LOCOS oxide film. A method of manufacturing a semiconductor device, comprising:
で行うことを特徴とする請求項１記載の半導体装置の製
造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the oblique ion implantation is performed by a rotary ion implantation apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296912A JPH0770728B2 (en) | 1989-11-15 | 1989-11-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296912A JPH0770728B2 (en) | 1989-11-15 | 1989-11-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03156975A JPH03156975A (en) | 1991-07-04 |
| JPH0770728B2 true JPH0770728B2 (en) | 1995-07-31 |
Family
ID=17839777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1296912A Expired - Fee Related JPH0770728B2 (en) | 1989-11-15 | 1989-11-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770728B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264384A (en) * | 1991-08-30 | 1993-11-23 | Texas Instruments Incorporated | Method of making a non-volatile memory cell |
-
1989
- 1989-11-15 JP JP1296912A patent/JPH0770728B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03156975A (en) | 1991-07-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |