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JPH0770810B2 - Method for manufacturing multilayer printed circuit board - Google Patents
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JPH0770810B2 - Method for manufacturing multilayer printed circuit board - Google Patents

Method for manufacturing multilayer printed circuit board

Info

Publication number
JPH0770810B2
JPH0770810B2 JP1125359A JP12535989A JPH0770810B2 JP H0770810 B2 JPH0770810 B2 JP H0770810B2 JP 1125359 A JP1125359 A JP 1125359A JP 12535989 A JP12535989 A JP 12535989A JP H0770810 B2 JPH0770810 B2 JP H0770810B2
Authority
JP
Japan
Prior art keywords
printed circuit
circuit board
board
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1125359A
Other languages
Japanese (ja)
Other versions
JPH02303179A (en
Inventor
浩二 中山
勉 今井
則夫 千石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1125359A priority Critical patent/JPH0770810B2/en
Publication of JPH02303179A publication Critical patent/JPH02303179A/en
Publication of JPH0770810B2 publication Critical patent/JPH0770810B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多層印刷回路基板の製造方法に係り、特に、
エポキシ樹脂等の透過不可能な基板に導体パターンを形
成した基板を積層して多層印刷回路基板を製造する場合
の、内層の基板の基板情報の外観からの識別に好適な製
造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer printed circuit board, and in particular,
The present invention relates to a manufacturing method suitable for identifying a substrate information of an inner layer from the appearance when a multilayer printed circuit board is manufactured by laminating a board on which a conductive pattern is formed on an impermeable board such as epoxy resin.

〔従来技術〕[Prior art]

多層印刷回路基板を製造する際、いわゆる電源・グラン
ド層は各印刷回路基板で共用し、信号層の配線パターン
のみを変えて複数品種の印刷回路基板を製造する場合が
ある。従来、このような複数品名に共通な電源・グラン
ド線などの導体パターンが形成された基板を表面層及び
裏面層に配置し、基板品名固有の導体パターンが形成さ
れた基板を内層に配置して多層印刷回路基板を製造する
場合、内層の基板に基板品名や来歴等の基板情報を導体
パターンにより形成し、これを表面層の基板を透過して
表示することにより、各々の印刷回路基板の外観からの
識別を可能にしていた。
When manufacturing a multilayer printed circuit board, a so-called power supply / ground layer may be shared by each printed circuit board, and a plurality of types of printed circuit boards may be manufactured by changing only the wiring pattern of the signal layer. Conventionally, a substrate on which a conductor pattern such as a power supply / ground line common to a plurality of product names is formed is arranged on the front surface layer and a back surface layer, and a substrate on which a conductor pattern unique to the substrate product name is formed is arranged in an inner layer. When manufacturing a multilayer printed circuit board, the board information such as the board name and history is formed on the inner layer board by a conductor pattern, and this is displayed through the board of the surface layer to display the appearance of each printed circuit board. It was possible to identify from.

第2図は、この種の多層印刷回路基板の基板情報表示部
分を拡大して示したもので、(a)は平面図、(b)は
断面図である。図中、1は印刷回路基板表面、3と5は
複数品名に共通な導体パターンを形成した表裏面層の基
板、4は基板品名固有の導体パターンを形成した内層の
基板、6はスルーホールである。ここで、内層の基板4
に、導体パターン2'による基板情報の文字を形成するこ
とにより、これが基板3を透過し、印刷回路基板の表面
1に表示される。
FIG. 2 is an enlarged view of a board information display portion of a multilayer printed circuit board of this type, in which (a) is a plan view and (b) is a sectional view. In the figure, 1 is the surface of a printed circuit board, 3 and 5 are front and back layer substrates on which a conductor pattern common to a plurality of product names is formed, 4 is an inner layer substrate on which a conductor pattern unique to the board product name is formed, and 6 is a through hole. is there. Here, the inner layer substrate 4
By forming a character of the board information by the conductor pattern 2 ', this is transmitted through the board 3 and displayed on the surface 1 of the printed circuit board.

なお、これに関連する公知文献としては、例えば実開昭
56−15076号公報が挙げられる。
Note that, as publicly known documents related to this, for example,
56-15076 is mentioned.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

以上従来技術は、エポキシ樹脂等の透過不可能な基材に
導体パターンを形成した基板を積層して多層印刷回路基
板を製造する場合には採用することができない。したが
って、このような場合には、印刷回路基板表面へ不滅イ
ンク等により基板情報を捺印したり、あるいは、表面層
の基板に導体パターンで内層の基板情報の文字を形成す
るなどして、対処せざるを得なかった。しかし、不滅イ
ンク等による捺印方法は、捺印工程で印字ミスが発生す
る可能性があり、信頼性に欠ける。また、表面層の基板
に導体パターンで内層の基板情報を形成する方法は、表
面層の基板の導体パターンが複数品名に共通なもの(電
源・グランド線など)についても、内層の基板情報に対
応したマスクを作成する必要があり、マスク作成費用の
増加及びマスク枚数の増加にともなうマスク管理工数の
増加を招くことになる。
As described above, the conventional technique cannot be adopted when a multilayer printed circuit board is manufactured by laminating a substrate having a conductive pattern formed on an impermeable base material such as epoxy resin. Therefore, in such a case, the printed circuit board surface is printed with imprintable ink or the like to print the board information, or the surface layer board is formed with characters of the inner layer board information by a conductor pattern. I had no choice. However, the imprinting method using immortal ink or the like has a possibility that a printing error may occur in the imprinting process, and thus lacks reliability. In addition, the method of forming the board information of the inner layer with the conductor pattern on the board of the surface layer also corresponds to the board information of the inner layer even if the conductor pattern of the board of the surface layer is common to multiple product names (power supply / ground line, etc.). Therefore, it is necessary to prepare a mask, and the mask management cost is increased with an increase in the mask manufacturing cost and the number of masks.

本発明の目的は、表裏面層の電源・グランド層などは各
印刷回路基板で共用し、内層の信号層の配線パターンの
みを変えて複数品種の多層印刷回路基板を製造する際、
表裏面層の基板が透過不可能であっても、内層の基板情
報の表示を簡単かつ確実に行い、印刷回路基板の外観か
ら基板情報の識別を可能とすることにある。
An object of the present invention is to share a power supply / ground layer of the front and back layers in each printed circuit board, and to change only the wiring pattern of the signal layer of the inner layer to manufacture a multilayer printed circuit board of a plurality of types.
Even if the substrates on the front and back layers are impermeable, the substrate information on the inner layers can be displayed easily and reliably, and the substrate information can be identified from the appearance of the printed circuit board.

〔課題を解決するための手段〕[Means for Solving the Problems]

上記目的を達成するために、本発明は、複数品名に共通
の導体パターンを形成した第1の基板を表面層及び裏面
層に配置し、各々の印刷回路基板を特徴付ける基板品名
固有の導体パターンを形成した第2の基板を中間層(内
層)に配置して積層した多層印刷回路基板に、前記第2
の基板の基板情報を示す穴明けパターンを、前記積層し
た各基板を貫通するスルーホールにより形成するように
したことである。
In order to achieve the above-mentioned object, the present invention arranges a first substrate on which a conductor pattern common to a plurality of product names is formed on a front surface layer and a back surface layer, and forms a conductor pattern unique to the board product name that characterizes each printed circuit board. The formed second substrate is placed on an intermediate layer (inner layer) and laminated to form a multilayer printed circuit board,
That is, the perforation pattern indicating the board information of the board is formed by a through hole penetrating each of the stacked boards.

〔作用〕[Action]

積層した各基板を貫通するスルーホールの穴明けパター
ンにより、個々の印刷回路基板を特徴づける内層の基板
情報が印刷回路基板表面に表示される。したがって、基
板が透過不可能な場合においても、簡単かつ確実に、外
観より各印刷回路基板の識別が可能となる。
Through hole patterns that penetrate through each of the stacked substrates, board information of the inner layer that characterizes each printed circuit board is displayed on the printed circuit board surface. Therefore, even when the substrate is impermeable, it is possible to easily and surely identify each printed circuit board from the appearance.

〔実施例〕〔Example〕

以下、本発明の一実施例について図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明による多層印刷回路基板の一実施例で、
特に基板情報表示部分を拡大して示したものである。第
1図において、(a)は平面図、(b)は断面図を示
し、1は印刷回路基板表面、3と5は複数品名に共通な
導体パターンを形成した基板(第1の基板)、4は基板
品名固有の導体パターンを形成した基板(第2の基
板)、2は基板4の基板情報を示す穴明けパターン、6
は通常のスルーホールである。
FIG. 1 shows an embodiment of a multilayer printed circuit board according to the present invention.
In particular, it is an enlarged view of the board information display portion. In FIG. 1, (a) is a plan view, (b) is a cross-sectional view, 1 is the surface of a printed circuit board, 3 and 5 are boards on which a conductor pattern common to a plurality of product names is formed (first board), Reference numeral 4 denotes a board on which a conductor pattern unique to the board product name is formed (second board), 2 denotes a perforation pattern indicating board information of the board 4, and 6
Is a normal through hole.

ここで、複数品名に共通な導体パターンを形成した基板
3と基板5は表面層及び裏面層に配置され、基板品名固
有の導体パターンを形成した基板4は内層(中間層)に
配置される。これら基板3、4、5を積層し、該積層し
た各基板3、4、5を貫通するスルーホール6を形成す
る。この時、同様に各基板3、4、5を貫通するスルー
ホールにより、内層基板4の基板情報を示す穴明けパタ
ーン2を形成する。これにより、表面層の基板3が透過
不可能な場合においても、印刷回路基板表面1に該印刷
回路基板を特徴づける内層基板4の基板情報が表示さ
れ、外観より印刷回路基板の品名等を識別することがで
きる。なお、穴明けパターン2は、その穴明けNCデータ
を通常のスルーホール6のNCデータに追加するだけで、
従来の穴明け設備によりスールホール6と一緒に簡単に
形成することができる。
Here, the substrate 3 and the substrate 5 on which a conductor pattern common to a plurality of product names is formed are arranged in the front surface layer and the back surface layer, and the substrate 4 on which a conductor pattern unique to the substrate product name is formed is arranged in an inner layer (intermediate layer). These substrates 3, 4, and 5 are laminated, and a through hole 6 penetrating each of the laminated substrates 3, 4 and 5 is formed. At this time, similarly, the through hole penetrating each of the substrates 3, 4 and 5 is used to form the perforation pattern 2 indicating the substrate information of the inner layer substrate 4. As a result, even when the substrate 3 of the surface layer is impermeable, the substrate information of the inner layer substrate 4 characterizing the printed circuit board is displayed on the surface 1 of the printed circuit board, and the product name of the printed circuit board is identified from the appearance. can do. For the drilling pattern 2, simply add the drilling NC data to the normal through hole 6 NC data.
It can be easily formed with the hole 6 by the conventional drilling equipment.

〔発明の効果〕〔The invention's effect〕

以上の説明から明らかなように、本発明によれば、多層
印刷回路基板の製造の際に、基板品名固有の導体パター
ンの形成された内層基板の基板情報が、各基板を貫通す
るスルーホールの穴明けパターンとして形成されるた
め、表面層の基板が内層パターンを透過することが不可
能な場合も、印刷回路基板表面に、各々の印刷回路基板
を特徴づける内層基板情報を容易かつ確実に表示するこ
とができる。したがって、従来の最外層に内層の基板情
報を導体パターンで表示した場合のように、複数の品名
に共通な最外層の導体パターンを形成するためのマスク
を基板品名に対応して作成する必要もなく、マスク作成
費用及びマスク増加にともなうマスク管理工程数を低減
することができる。
As is apparent from the above description, according to the present invention, when manufacturing a multilayer printed circuit board, the board information of the inner layer board on which the conductor pattern unique to the board item name is formed is the information of the through hole penetrating each board. Since it is formed as a perforated pattern, even when the substrate of the surface layer cannot penetrate the inner layer pattern, the inner layer substrate information characterizing each printed circuit board can be easily and reliably displayed on the surface of the printed circuit board. can do. Therefore, it is also necessary to create a mask corresponding to the board item name to form the outermost layer conductor pattern that is common to multiple product names, as in the case where the inner layer board information is displayed on the outermost layer in the conventional manner. In addition, the number of mask management steps can be reduced due to the mask production cost and the increase in masks.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明による多層印刷回路基板の一実施例を示
す図、第2図は内層パターン透過法による従来の基板情
報表示例を示す図である。 1……印刷回路基板表面、2……穴明けパターン、3、
4、5……基板、6……スルーホール。
FIG. 1 is a view showing an embodiment of a multilayer printed circuit board according to the present invention, and FIG. 2 is a view showing a conventional board information display example by an inner layer pattern transmission method. 1 ... Printed circuit board surface, 2 ... Hole pattern, 3,
4, 5 ... Board, 6 ... Through hole.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭55−50686(JP,A) 実開 昭59−91768(JP,U) 実開 昭61−171271(JP,U) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-55-50686 (JP, A) Actually opened 59-91768 (JP, U) Actually opened 61-171271 (JP, U)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数品名に共通の導体パターンを形成した
第1の基板を表面層及び裏面層に配置し、各々の印刷回
路基板を特徴付ける基板品名固有の導体パターンを形成
した第2の基板を中間層に配置して、多層印刷回路基板
を製造する方法において、 前記第1の基板を表面層及び裏面層に前記第2の基板を
中間層に配置して積層した多層印刷回路基板に、前記第
2の基板の基板情報を示す穴明けパターンを、前積層し
た各基板を貫通するスルーホールにより形成することを
特徴とする多層印刷回路基板の製造方法。
1. A second substrate on which a first substrate on which a conductor pattern common to a plurality of product names is formed is arranged on a front surface layer and a back surface layer, and a conductor pattern peculiar to the substrate product name which characterizes each printed circuit board is formed. A method of manufacturing a multilayer printed circuit board by disposing an intermediate layer, wherein the first substrate is a front surface layer and a back surface layer, and the second substrate is an intermediate layer, and the multilayer printed circuit board is laminated. A method for manufacturing a multi-layer printed circuit board, characterized in that a perforation pattern indicating board information of the second board is formed by a through hole penetrating each of the pre-laminated boards.
JP1125359A 1989-05-18 1989-05-18 Method for manufacturing multilayer printed circuit board Expired - Lifetime JPH0770810B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1125359A JPH0770810B2 (en) 1989-05-18 1989-05-18 Method for manufacturing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1125359A JPH0770810B2 (en) 1989-05-18 1989-05-18 Method for manufacturing multilayer printed circuit board

Publications (2)

Publication Number Publication Date
JPH02303179A JPH02303179A (en) 1990-12-17
JPH0770810B2 true JPH0770810B2 (en) 1995-07-31

Family

ID=14908185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1125359A Expired - Lifetime JPH0770810B2 (en) 1989-05-18 1989-05-18 Method for manufacturing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPH0770810B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5550686A (en) * 1978-10-06 1980-04-12 Tokyo Shibaura Electric Co Method of marking printed circuit board
JPS5991768U (en) * 1982-12-13 1984-06-21 富士通株式会社 Printed board with recognition code
JPS61171271U (en) * 1985-04-12 1986-10-24

Also Published As

Publication number Publication date
JPH02303179A (en) 1990-12-17

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