JPH0771062B2 - Clock distribution device - Google Patents

Description

The present invention relates to a clock distribution device used for multiple conversion of a digital data transmission device, and an object thereof is to select and transmit the minimum clocks and frame pulses necessary for an interface board from a clock board. A clock distribution device having a clock board for generating various clocks and frame pulses, and various interface boards that are detachably mounted on the clock board via a backboard and receive necessary clocks and frame pulses generated by the clock board. Which is applied to the interface board, and package identifier code setting means for selecting the necessary clock and frame pulse for each interface board, and the package board identifier code of the interface board mounted on the clock board backboard. Based on And a selecting means for selecting the minimum clock and frame pulse required for the mounting interface board and sending them to the mounting interface board.

[Industrial application field]

The present invention relates to a clock distribution device used for multiplex conversion of a digital data transmission device.

[Conventional technology]

2. Description of the Related Art Conventionally, as a clock distribution device used for multiple conversion of a digital data transmission device, a system shown in FIG. 2 is known.

In FIG. 2, the clock board 1 generates a clock of a required frequency, for example, a clock for 1.5M, 2M, 6.3M, etc. from a reference clock of 64KHz + 8KHz from a digital clock supply unit (not shown), Creates frame pulses for 2M, 6.3M, etc. Each clock and each frame pulse generated by the clock board 1 is a separate buffer.
Output to the backboard 2 side through 1a, 1b ....

The backboard 2 is for mounting interface boards 3A, 3B, 3C that receive the necessary clock and frame pulses generated by the clock board 1, for 1.5M, 2M, 6.3M
Each clock line such as a clock pulse and each frame pulse line for 1.5M, 2M, 6.3M, etc. are provided. These clock lines and frame lines are connected to the connector 2a mounted on the backboard 2. It

The connector 2a of the backboard 2 is each interface board 3
Common to A, 3B, 3C, each interface board 3A, 3B, 3C, ...
It has A _a , 3B _a and 3C _a .

Interface board 3A is for 1.5M, 1.5M, 6.3M
3A _a that is connected to the corresponding clock line frame pulse line of the backboard 2 so as to capture the clock and the 1.5M and 6.3M frame pulses
Select the pins, connect the buffers 3A _b to 3A _e to each of the selected connector pins, and open the unselected connector pins.

Similarly, in the interface board 3B for 2M,
Corresponding to this, connector 3B can capture the clock for 2M and 6.3M and the frame pulse for 2M and 6.3M.
Select the pin _a, connects the buffer 3B _b ~3B _e to the selected respective connector pins were. Then open the unselected connector pins. Also, interface board for 6.3M
In 3C, the pin of connector 3C _a is selected correspondingly so that the clock for 6.3M and the frame pulse for 6.3M can be taken in, and buffers 3C _b and 3C _c are selected for this selected connector pin. Connect and open unselected connector pins.

In addition, clock board 1 and each interface board 3A, 3B,
3C includes respective internal alarm collection section 1A collects alarm data generated and 3A _f, 3B _f, the 3C _f.
The interface board 3A mounted on the clock board 1 and the backboard 2 is connected to the control / monitoring device 4.
The control / monitoring device 4 controls the clock board 1 and the mounted interface board 3A or 3B, 3C, and also monitors the alarm state.

[Problems to be Solved by the Invention]

However, in the conventional clock distribution device as described above, since the interface boards 3A to 3C of a plurality of types can be mounted on the backboard 2 of the clock board 1 via the common connector 2a, the interface board to be mounted is mounted. Even if unnecessary clocks and frame pulses are used, there are many types of clocks and frame pulses because it is necessary to form a number of wires on the backboard that correspond to the various clocks and frame pulses generated by the clock board. Then, the wiring pattern of the backboard becomes complicated and overcrowded, and the pin assignment of the connector becomes difficult.

Further, since the clock has a high pulse high frequency component, if the wiring pattern becomes overcrowded, the leakage between the wirings becomes large, and further, the supply line for the clock and the frame pulse is opened, resulting in a large reflection. there were.

The present invention has been made in view of the above points, and an object of the present invention is to provide a clock distribution device capable of selecting and transmitting the minimum clocks and frame pulses necessary for the interface board from the clock board.

[Means for Solving the Problems]

The present invention will be described with reference to FIG. 1 which is an embodiment. The present invention is a clock board 10 for generating various clocks and frame pulses, and is detachably mounted on the clock board 10 via a backboard 12. The present invention is applied to a clock distribution device having various interface boards 11A, 11B, 11C that receive the necessary clock and frame pulse generated by the clock board 10, and each interface board
Package identifier code setting means 11A _a , 11B _a and 11C _a provided on 11A, 11B and 11C for selecting respective necessary clocks and frame pulses, and package identifiers of the interface board mounted on the backboard 12 of the clock board 10. Selector 101 for selecting the minimum clock and frame pulse required for the mounting interface board based on the code and sending them to the mounting interface board.

[Action]

Interface board 11A (or 11B, 11C) on clock board 10
When is mounted, the clock board 10 is notified of the package identifier code of the mounting interface board. Based on this, the selection means 101 selects the minimum clock and frame pulse required by the mounting interface board from various clock and frame pulse groups generated by the clock board 10 and sends them to the mounting interface board.

Therefore, each interface board can be easily managed, the number of wires is small, and the clock and frame pulse with easy connector pin assignment can be distributed and transmitted to the mounted interface board.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, reference numeral 10 is a clock that generates a required frequency, for example, a clock of 1.5M, 2M, 6.3M and a frame pulse of 1.5M, 2M, 6.3M from a reference clock of 64KHz + 8KHz from a digital clock supply unit. Boards 11A, 11B and 11C are interface boards for 1.5M, 2M and 6.3M that receive the necessary clock and frame pulses generated by clock board 10, and 12 are each interface board.
A backboard for connecting 11A to 11C to the clock board 10.

The clock board 10 uses the various clocks and frame pulses that are generated to generate the interface board 11
The select circuit 101 for selecting the minimum clock and frame pulse required for A to 11C, for example, two clocks and two frame pulses, and the package identifier code of the interface boards 11A to 11C mounted on the backboard 12 are decoded. Decode circuit 1 that outputs a select signal suitable for the mounting interface board to the select circuit 101
02, four three-state gates 103a to 103d for outputting the clock and frame pulse selected by the select circuit 101 to the backboard 12 side, and an alarm collecting unit 104 for collecting alarm data generated inside the clock board 10.
With.

In addition, each of the interface boards 11A to 11C has an identifier code setting circuit 11 for setting its own package identifier code.
_{A a,} 11B _a, and 11C _a, each interface board 11A
Alarm collection unit 11A that collects the alarms generated at
_b , 11B _b , 11C _b , respectively.

The interface board 11A or 11B, 11C mounted on the clock board 10 and the backboard 12 is connected to the control / monitor device 13. This control and monitoring device 13 is a clock board 10
And the installed interface board 11A or 11B, 11C is controlled, and the installed interface board 11A or 11C
The package identifier information is collected from B and 11C, the identifier information is notified to the clock board 10, and the alarm states of the clock board 10 and the mounting interface board are monitored.

The backboard 12 has two clock lines 12a, which are connected to the three-state gates 103a to 103d of the clock board 10, respectively.
12b and frame pulse lines 12c and 12d. The clock lines 12a and 12b and the frame pulse lines 12c and 12d are connected to the common connector 121 mounted on the backboard 12.

The interface boards 11A to 11C detachably mounted on the backboard 12 are the connectors 12 of the backboard 12.
It has connectors 111A, 111B, 111C to be connected to 1,
The 1.5M interface board 11A includes buffers 11A _{1 to} 11A ₄ for taking in clocks and frame pulses necessary for the interface board 11A. Similarly, the 2M interface board 11B includes buffers 11B _{1 to} 11B ₄ for taking in the clocks and frame pulses necessary for this. Furthermore, the interface board 11C for 6.3M is
It is equipped with buffers 11C ₁ and 11C ₂ to capture the clock and frame pulses required for this.

Next, the operation will be described.

On the backboard 12 of the clock board 10, for example, when the interface board 11A for 1.5M is mounted via the connectors 121 and 111A, the identifier code of the package identifier code setting circuit 11A _a is taken into the control / monitor device 13, Further, it is transmitted to the decoding circuit 102 of the clock board 10. The decoding circuit 102 decodes the transmitted identifier information and outputs a select signal to the select circuit 101. Upon receiving the select signal, the select circuit 101 selects 1.5M or more of the clock and frame pulse generated by the clock board 10.
A 6.3M clock and 1.5M and 6.3M frame pulses are selected and output to the three-state gates 103a to 103d.
At this time, since the gates of the three-steady gates 103a to 103d are in the non-enabled state, the 1.5M and 6.3M clocks and the 1.5M and 6.3M frame pulses selected by the select circuit 101 are three-steady gates. The signals are sent from the 103a to 103d to the interface board 11A through the clock lines 12a and 12b and the frame pulse lines 12c and 12d of the backboard 12 and the connectors 121 and 111A.

In addition, the interface board 11B for 2M is used as the backboard 12
Package identifier setting circuit 11B _a
The select circuit 101 operates so as to select a 2M / 6.3M clock and a 2M / 6.3M frame pulse on the basis of the identifier information of, and sends these clock and frame pulse to the mounted interface board 11B.

On the other hand, the interface board 11C for 6.3M is the backboard 1
2 is mounted on the select circuit 101 based on the identifier information of the package identifier code setting circuit 11C _a.
Select a 6.3M clock and a 6.3M frame pulse, and select the three-state gates 103a, 1 of the selected output line.
03c is set to the non-enabled state and three-state gates 103b and 103d are set to the enabled state. As a result, a clock of 6.3M and a frame pulse of 6.3M are sent to the mounted interface board 11C.

In this embodiment, each interface board
A package identifier code is set for each of 11A to 11C, and this identifier code is collected by the control / monitor device 13 to obtain the clock board
To recognize the interface board mounted by the decoding circuit 102 of the clock board 10, select the minimum clock and frame pulse required for the interface board by the select circuit 101, and three-stead gate 103a ~ Since it is sent to the mounted interface board through 103d, the management of each interface board is facilitated, and the number of wirings of the backboard 12 on which the interface board is mounted can be greatly reduced as compared with the conventional method. Since the number of wires can be reduced, the pin assignment of the interface board connector becomes easy.

Further, by providing a three-state gate on the output line of the selected clock and frame pulse, there is no output line that is open as in the conventional case, and the problem of reflection can be solved.

It should be noted that the present invention is not limited to the configuration of the circuit system shown in the above embodiment, and can be variously modified within the scope of the claims.

〔The invention's effect〕

As described above, according to the present invention, a package identifier code is set on various interface boards detachably mounted on a clock board via a backboard, and a clock generated on the clock board based on the identifier code is set. Since the minimum clock and frame pulse required for the mounted interface board are selected and sent out from the frame and frame pulse, it is easy to manage each interface board, the number of wires is small, and the connector pin assignment is possible. It is possible to distribute and send easy clock and frame pulse to the mounting interface board.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention, and FIG. 2 is a configuration diagram of a conventional clock distribution device. In FIG. 1, 10 is a clock board, 11A to 1C are interface boards, 12 is a backboard, 13 is a control / monitor device, 101 is a select circuit, 102 is a decode circuit, 103a to 103d are three-state gates, 11A _a , 11B _a , 11C _a are package identifier code setting circuits.

Claims (1)

[Claims] 1. A clock board (10) for generating various clocks and frame pulses, which is detachably mounted on the clock board (10) through a backboard (12) and needs to be generated by the clock board (10). In a clock distribution device having various interface boards (11A, 11B, 11C) for receiving clocks and frame pulses, a package provided on each of the interface boards (11A, 11B, 11C) for selecting each required clock and frame pulse Identifier code setting means (11A _a , 11B _a ,
11C _a ) and the mounting interface board by selecting the minimum clock and frame pulse required for the mounting interface board based on the package identifier code of the interface board mounted on the backboard (12) of the clock board (10). A clock distribution device, comprising: a selection unit (101) for sending to the.