JPH0771079B2 - Serial data transfer device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a serial data transfer device, and more particularly, to a bit serial communication system by connecting a transmitting device and a receiving device with one clock line and one data line. A device for transferring data.

[Conventional technology]

Conventionally known serial data transfer devices require a large number of signal lines such as a clock line, a first signal line for data transmission, a second signal line for data reception, and a signal line for device selection. Met. Therefore, reduce the number of signal lines connecting between devices as much as possible, and
A technique for transferring serial data using a signal line of a book is disclosed in Japanese Patent Laid-Open No.
-106262 is proposed. According to this technology,
Basically, a plurality of devices (chips) can be connected by only two signal lines (clock line and data line). Therefore, the structure of the device is very simple, and the number of terminals required for each chip is small, so that the chip cost can be reduced.

[Problems to be solved by the invention]

However, in the technique described in the above publication, both the clock line and the data line are driven by the open drain type drive circuit. That is, the signal line pulled up to the power supply potential via a resistor is used as a data line and a clock line, the drain end of the FET whose source end is grounded is directly connected to both ends of the signal line, and the gate is controlled. Clock and data are transferred by turning on and off the FET. When the transmitter turns off the FET, the discharge path to the signal line is cut off, so that the power level (H level) signal is transferred, while when the FET is turned on, the discharge path is formed and the ground level (L level) signal is generated. Transferred.

However, a signal line having such an open drain type drive circuit is used for transferring signals (clock and data).
There is a big drawback that the rising and falling edges are slow and serial data cannot be transferred at high speed. In particular, when performing data transfer using two lines, that is, a clock line and a data line, it is necessary to send data during the period when the clock is at the level and receive it during the period when the clock is at the H level. In addition, since data cannot be transmitted and received during the period until the L level of the clock is determined and the period until the H level is determined, the above transfer method, which requires a long time for the transition period of the clock, is a major obstacle to speeding up. Moreover, in the case of serial transfer, since bit information must be transferred serially for each clock cycle, the rising and falling delays of the clock become the transfer delay of each bit, and the number of bits to be transferred is large. There is a drawback that the transfer rate becomes slower.

[Means for solving problems]

In order to solve the above problems, the present invention is characterized in that a clock line is driven by a push-pull driver circuit.

That is, instead of pulling up the clock line with a resistor, use a series circuit of two FETs, connect one end of the clock line to the node of both FETs, connect one FET to the power supply and the other FET to ground To do so. Then, both FETs are exclusively turned on and off to transfer the clock. Both FETs
By turning off both of them, the clock line can be electrically disconnected and used as a high impedance state.

According to the present application, it is possible to transfer a clock having a steep rising edge and a steep falling edge, so that the clock transition period can be greatly shortened, and particularly the serial data transfer speed can be greatly improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. For simplification of description, a case where two serial data processing devices are connected will be described here.

First serial data processing device (first chip) 100
In addition to the data processing unit (not shown),
101, serial clock control circuit 102, shift register 103,
A serial clock output unit 120, a serial clock input buffer 113, a serial data output unit 121, and a serial data input buffer 116 are included inside, and a serial clock input / output terminal 104 and a serial data input / output terminal 105 are provided as external terminals.

The serial clock output unit 120 includes the P-ch transistor 107.
A C-MOS push-pull buffer composed of an N-ch transistor 108 and gates 110 to 112 for controlling them, and outputs a power supply voltage level, that is, an H level when the P-channel transistor 107 is turned on. When 108 turns on, it outputs GND level, that is, L level. Both transistors 107 and 108 are turned on / off by a 2-input NAND gate 110 and a 2-input NOR gate 11 respectively.
It is controlled by the output of 1.

A mode register 101 is used to specify whether the chip 100 is used as a master device or a slave device. When the content is "1", the master mode is designated. That is, one input of the NAND gate 110 is “1”,
Since one input of the NOR gate 111 via the inverter 112 becomes "0", when the serial clock output from the serial clock control circuit 102 is at the H level, the output of the NAND gate 110 is "0" and the P channel transistor. 107 is turned on, the output of the NOR gate 111 is "0", and the N-channel transistor 108 is turned off, so that a high level is output to the serial clock input / output terminal 104. On the other hand, when the serial clock output from the serial clock control circuit 102 is at L level, the output of the NAND gate 110 is "1" and the P-channel transistor 107 is off, and the output of the NOR gate 111 is "1" and the N-channel transistor is 108 turns on, so L
The level is output to the serial clock input / output terminal 104. That is, when designated as the master mode,
The serial clock output from the serial clock control circuit 102 is output to the serial clock input / output terminal 104 via the serial clock output unit 120.

On the other hand, when the content of the mode register 101 is "0", the output of the NAND gate 110 is "1", the output of the NOR gate 111 is "0", and both the transistors 107 and 108 are turned off. Therefore, the serial clock output unit 120 is electrically disconnected from the terminal 104. At this time, the operation is performed in the slave mode, and the clock input from the outside is input to the serial clock control circuit 102 via the buffer 113.

The serial data output unit 121 includes an open drain buffer including an N-channel transistor 109, a 2-input NAND gate 115 that controls the open drain buffer, and a data output enable flag 10.
6 and an inverter 114 that inverts its output.
When the data output enable flag 106 is “1”, the NAND gate 115
Since one of the inputs becomes “0”, the inverted output of the output of the shift register 103 is applied to the gate of the transistor 109. That is, when the output of the shift register 103 is "1", the output of the NAND gate 115 is "0", and the N-channel transistor 109 is turned off. On the other hand, when the output of the shift register 103 is “0”, the output of the NAND gate 115 is “1”,
The N-channel transistor 109 turns on. The serial data from the shift register 103 is synchronized with the falling edge of the serial clock supplied from the serial clock control circuit 102. When the data output enable flag 106 is “0”, one input of the NAND gate 115 is “1”, so NAN
The output of the D gate 115 is always "0". Therefore, the N-channel transistor 109 is turned off and electrically disconnected from the serial data input / output terminal 105. At this time, input of serial data from the outside is permitted, and serial data input from the outside via the serial data input / output terminal 105 is input to the shift register 103 via the serial data buffer 116. The input to the shift register 103 is serially shifted bit by bit in synchronization with the rising edge of the serial clock.

When the mode register 101 is "0", the slave mode described above operates, but the serial clock externally input to the serial clock input / output terminal 104 at this time is transmitted via the serial clock input buffer 113. The serial clock control circuit, and further controls the shift operation of the data serially input to the shift register 103.

The second serial data processing device (second chip) 150 may basically have the same configuration as the first serial data processing device 100. That is, although the reference numbers are different, the mode register 151, the serial clock control circuit 152, the shift register 153, the serial clock output unit 170,
The serial clock input buffer 163, the serial data output unit 171, the serial data input buffer 106, the serial clock input / output terminal 154, and the serial data input / output terminal 155 may have the same circuit and the same function as those of the first chip 100.

Next, the actual serial data transfer between the first serial data processing device 100 and the second serial data processing device 150 will be described. The master mode is assigned by setting the mode register 101 of the first serial data processing device 100 to "1" (hereinafter, the first serial data processing device is referred to as a master device). On the other hand, the slave mode is assigned by setting the mode register 151 of the second serial data processing device 150 to "0" (hereinafter, the second serial data processing device is referred to as a slave device). The serial clock input / output terminals 104 and 154 of the master device 100 and the slave device 150 are connected by one serial clock line 180. The serial data input / output terminals 105 and 155 are 1
Connect with serial data line 181 of book, serial data line 1
81 pulls up to a predetermined power supply voltage using a resistor 182.

A change in each signal when serially transferring 8-bit data from the master device 100 to the slave device 150 will be described with reference to the time chart of FIG. Figure 2 shows the serial clock on serial clock line 180 and serial data line 1
81 shows serial data on.

The serial clock control circuit 102 of the master device 100 controls so as to output "1" during non-transfer. Therefore, in this state, the P-channel transistor 107 is turned on, a high level is output to the serial input / output terminal 104, and the serial clock line 180 holds the high level. When the master device is in the transmission mode, the permission flag 106 is set to "1". Then, the output of the shift register 103 at the time of non-transfer is set to "1" to temporarily turn off the N-channel transistor 109. On the other hand, the permission flag 156 of the slave device 150 is cleared to “0” in advance during the reception operation, and the NOR gate 165
Output is "0" and the N-channel transistor 159 is turned off. Therefore, the serial data line 181 at the time of non-transfer is
It has been pre-upped to a high level by 82. When the serial clock control circuit 102 of the master device 100 starts to generate a serial clock, the shift register 103 shifts by 1 bit in synchronization with the falling edge t1 and outputs the 1-bit data at the final stage to the serial data output unit 121. It outputs to the serial data input / output terminal 105 via. Subsequently, the shift register 103 performs a serial shift operation in synchronization with each timing of t3, t5, t7, t9, t11, t13, and t15, which are the falling edges of the serial clock, and serially outputs serial data bit by bit on the serial data line 181. Print on top. After outputting 8 bits of serial data, the high level output is maintained in synchronization with the timing t17. When the serial clock becomes high level at timing t18, it holds high level until the next data transfer.

Here, if the serial data to be transferred is “0”,
The transistor 109 is turned on and the data line 181 is driven to the L level. However, when the serial data is “1”, the transistor 109 is turned off and the high level pulled up by the resistor 182 is output to the data line 181. Therefore, the delay of the serial data output with respect to the falling edge of the serial clock is larger when the data is "1". Specifically, it is determined by the time constant of the bus capacitance of the serial data line 181 and the pull-up resistor 182. For example, if the bus capacitance is 200 pF and the pull-up resistor is 1 kΩ, 200 nsec.
Delay time (td). On the other hand, the slave device 150 on the receiving side transmits the serial data on the serial data line 181 to the serial data input / output terminal 155 and the input buffer 166 in synchronization with the rising edge t2 of the serial clock input from the serial clock input / output terminal 154. It is taken into the shift register 153 via. Continued rising edge t4, t
6, t8, t10, t12, t14, t16, serial data line in sequence
The serial data on 181 is shift-input to the shift register 153.

During such serial transfer, the output of the serial clock output unit 170 of the slave device 150 becomes high impedance, and the serial clock line 180 is not affected at all,
Further, since the permission flag 156 is “0”, the output of the serial data output unit 171 also becomes high impedance and does not affect the serial data line 181.

Conversely, when the master device 100 receives serial data from the slave device 150, the permission flag 106 of the master device 100 is set to “0” and the permission flag 156 of the slave device 150 is set to “1”. To be done. As a result, based on the clock from the master device 100, the contents of the shift register 153 of the slave device 150, the serial data output unit 171,
The data is output to the serial data line 181 via the serial data input / output terminal 155 and shift-input to the shift register 103 via the input / output terminal 105 of the master device 100 and the input data buffer 116. FIG. 3 is a block diagram showing a second embodiment of the serial data transfer device according to the present invention. First
The serial data processing device 300 includes a serial clock control circuit 102, a shift register 103, a serial clock output unit 320, a serial data output unit 321, a serial clock output terminal 304, and a serial data output terminal other than a data processing unit (not shown). Including 305, it always functions as a master device. That is, the P-channel transistor 307 and the N-channel transistor 308 of the serial clock output unit 320
In the CMOS push-pull circuit composed of (1), only one of the transistors is always turned on by the output of the serial clock control circuit 102 inverted via the inverter 322 to drive the serial data line 180. In the serial data output unit 321, the open drain type transistor 309 is turned on or off by the output of the shift register 103 which is always inverted by the inverter 323 to drive the serial data line 181.

The second serial data processing device 350 includes a serial clock control circuit 152, a shift register 153, a serial clock input buffer 163, a serial data input buffer 166, a serial clock input terminal 354 and a serial data input terminal 3.
It includes 55 and operates only as a slave device that receives the serial clock output from the master device 300 and receives the serial data input from the serial data input terminal 355 to the shift register based on this serial clock.

The synchronization timing between the serial clock and the serial data when transferring data bit-serially from the master device 300 to the slave device 350 is substantially the same as the time chart of FIG. 2 shown in the first embodiment. By driving the data line by the open drain circuit instead of the push-pull circuit, a plurality of slave chips can be connected to one data line by wired OR. Therefore, when a plurality of slave chips request data transfer at the same time, the slave chip whose data line has been maintained at the L level for a longer time can be assigned to perform the highest priority data transfer. Further, by providing the receiving chip with means for clamping the data line to the L level, when the receiving chip cannot receive the data, the data line is clamped to the L level to notify the transmitting chip of busy. You can In order to have such a function, it is better to drive the data line with an open drain circuit.

〔The invention's effect〕

As described above, in the serial data transfer device of the present invention, the clock line is driven by the push-pull buffer and the data line is driven by the open drain buffer to make the rising and falling edges of the clock steep, and thereby the data Since the transfer speed can be increased and the data line can be wired connected,
It is possible to connect a plurality of chips with two lines of a clock line and a serial data line. Above all,
Both the rising and falling edges of the clock are steep, so it is possible to synchronize the rising and falling edges.
Each timing of inputting data to the shift register and outputting data from it can be accurately controlled by a very simple timing circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a serial data transfer apparatus according to the first embodiment of the present invention, FIG. 2 is a serial data transfer timing chart for explaining the first embodiment, and FIG. It is a block diagram of a serial data transfer device of an example. 100,300 …… First serial data processor, 150,350…
… Second serial data processing device, 101,151 …… Mode register, 102,152 …… Serial clock control circuit, 10
3,153 …… Shift register, 104,154 …… Serial clock input / output terminal, 105,155 …… Serial data input / output terminal, 304 …… Serial clock output terminal, 354 …… Serial clock input terminal, 305 …… Serial data output terminal, 355… … Serial data input terminal, 106,156 …… Permit flag, 107,157,307 …… p-ch transistor, 108,15
8,308,109,159,309 …… N-ch transistor, 110,160…
… 2-input NAND gate, 111,161,115,165 …… 2-input NOR gate, 112,162,114,164,322,323 …… Inverter, 113,1
63,116,166 …… Input buffer, 120,170,320 …… Serial clock output section, 121,171,321 …… Serial data output section, 182 …… Pull-up resistor, 180 …… Serial clock line, 181 …… Serial data line.

Claims (2)

[Claims] 1. A data transfer device in which a data transmitting chip and a data receiving chip are interconnected by one clock line and one data line, wherein the clock line is driven by a push-pull buffer circuit, and The data line is driven by an open drain circuit, and the data transmission chip drives the data line in response to data to be transmitted by the open drain circuit in synchronization with one of the rising edge and the falling edge of the clock. A data transfer device characterized by the above. 2. The data receiving chip according to claim 1, wherein the data receiving chip receives data on the data line in synchronization with the other of the rising edge and the falling edge of the clock. Transfer device.