JPH0771252B2 - Video signal recording / reproducing device - Google Patents

Description

The present invention relates to a video signal recording / reproducing apparatus, which divides a video signal within one vertical scanning period into a plurality of segments, and divides a signal of each segment into a plurality of segments. The present invention relates to a recording signal generation method and apparatus suitable for recording into a plurality of channels and recording over a plurality of tracks.

[Conventional technology]

As a conventional example of a so-called segment recording type magnetic recording / reproducing apparatus for dividing one vertical scanning period (one field) of a video signal into a plurality of pieces and recording them on a magnetic tape, there is a four-head VTR for commercial use such as a broadcasting station. For details, refer to, for example, the literature (Japan Broadcast Publishing Association, Television Society, edited,
Minoru Inazu, Takashi Iwasawa, VTR Technology). In the above segment recording system VTR, one field of a video signal is recorded by being divided into a plurality of tracks, and therefore, when reproducing the so-called recording head, a so-called error that occurs at the time of track switching due to a mounting error of a rotary head, expansion and contraction of tape, etc. A time axis correction circuit for correcting skew (abrupt change in time axis) is essential. As a method of correcting this skew,
As described in detail in the above-mentioned document (Chapter 7), the delay time of the video signal is made variable according to the skew amount via a variable delay line or the like, and the horizontal blanking period of the video signal, Specifically, a time axis correction method is known in which the phase of the video signal and the horizontal synchronization signal is made continuous by expanding or contracting the period of the front porch immediately before the horizontal synchronization signal.

According to the above-mentioned conventional method, the amount of skew that can be corrected is determined by the time width of the front porch included in the video signal, and the current television system has a limit of about 1 to 2 μsec.

On the other hand, current home VTRs do not use the segment recording as described above, but generally use a so-called helical scan type that records one field of a video signal on one track. In order to further reduce the size and weight of the VTR by reducing the diameter of the drum, or to increase the number of rotations of the rotating drum to achieve high image quality, and in addition to the high definition of the current TV system In order to realize a new VTR capable of recording a video signal having a wide band several times wider than the conventional one, such as a so-called high-definition television that can obtain high image quality, an attempt is made to record the above segment in a home VTR as well. There is. However, in the helical scan type VTR for home use, due to manufacturing restrictions, the finishing accuracy of the mechanical system such as the rotary head system and the tape running system is not always sufficient, and if the storage conditions of the tape in general households are taken into consideration, The amount of skew generation is as long as several microseconds, and it is necessary to allow for a margin to the above value in consideration of compatible reproduction.

In addition, according to the method partially proposed as the above high-definition television, according to the literature (Technical Report of the Television Society VOL.7, No. 4).
4, March, 1984; "High-definition television satellite 1-channel transmission system MUSE"), the horizontal blanking period assigned to a video signal is short (1 μsec or less).

Furthermore, before the high-definition television broadcasting has begun in earnest, it has been considered to operate the high-definition television for commercial use as a closed system in a mini theater or the like. The VTR used in this system is also a helical scan type similar to the above-mentioned household VTR, and is equipped with a mechanism that uses a small diameter cylinder and a small cassette. However, its purpose is to capture a reproduced image on a large screen such as in a mini theater, and by recording a high-definition television signal in a wide band in the baseband without using a band compression technique, a good image quality can be obtained. Need to get Therefore, a recording method has been attempted in which the input video signal is divided into a plurality of channels to narrow the signal band per channel and the data of one field is divided into a plurality of segments. At this time, in addition to the measures against the skew caused by the segment division recording, it is also a big problem to realize the H arrangement between tracks which is caused by recording the plural channel signals on the adjacent tracks.

As described above, it is very difficult to completely remove the skew distortion generated in the reproduction screen by the conventional system in both the current TV system and the high-definition TV system. Further, in a method involving channel division in addition to segment division, a so-called H arrangement on the tape pattern may be realized due to factors such as the head mounting position between channels and the rotational phase control error of the cylinder during recording. A VTR that becomes a major issue and achieves the above objectives
Is difficult to achieve.

Another conventional example of the segment recording is a so-called digital VTR which converts a video signal into a digital signal and records it in the form of a PCM signal.
Since it is necessary to reduce the quantization error associated with the digitization of the above video signal, the number of quantization bits increases, which significantly increases the transmission rate of the PCM signal recorded on the magnetic tape and significantly reduces the recording density of the tape. As a result, a sufficient recording time cannot be obtained, and a signal to be handled has a very wide band, which is technically difficult, which is a big obstacle for popularization for home use. In order to secure a sufficient recording time and obtain a sufficient image quality, it is an important issue for those skilled in the art to realize the segment recording by the analog method instead of the digital method.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, one field is divided into a plurality of tracks for recording, and therefore, it is necessary to completely remove the skew distortion caused by head switching in one field when reproducing. However, when it is necessary to keep the redundancy in the recorded signal as low as possible in order to reduce the recording density, such as in a VTR that records a high-definition television signal, the redundancy used to remove the above skew distortion. There is a problem that the overlap area of the signal and the head must be limited to a large extent.

In view of the above problems, an object of the present invention is to limit the redundancy of recording signals and to eliminate skew distortion in a stable and reliable manner, and to easily realize the above segment recording. It is to provide a reproducing apparatus.

[Means for solving problems]

The above-mentioned object is to provide a redundant blanking signal (hereinafter, referred to as a blanking signal not containing a video signal for head switching between each segment obtained by dividing a video signal of one field into n pieces (n is an integer of 2 or more). (Referred to simply as blanking signal), and when recording the video signal and blanking signal on the tape, the video signal and blanking signal are recorded in synchronization with the pulse synchronized with the rotation phase of the head drum. Can be achieved by

[Action]

According to the method described above, a blanking signal containing no video signal is obtained between the segments of the reproduced signal,
Since the head switching can be performed within the period of the blanking signal, the reproduced video signal does not include the skew distortion due to the head switching, and it is possible to reproduce the video signal with good connection between the segments. It will be possible.

In addition, the signal recorded on the tape during recording is generated in synchronization with the rotation phase of the rotary head, and as a result, the position on the tape for horizontal synchronization between adjacent tracks matches in the direction orthogonal to the track longitudinal direction. The so-called H arrangement can be realized accurately and easily.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples. FIG. 1 is a block diagram showing an embodiment of a recording apparatus in which the present invention is applied to a video signal recording / reproducing apparatus based on a 2-channel division recording system, FIG. 3 is a waveform diagram for explaining the operation, and FIG. FIG. 3 is a diagram showing a track pattern on a magnetic recording medium (tape) obtained by the above device.

In FIG. 1, a magnetic tape 1 is a capstan motor 2
The capstan motor 2 is controlled by the capstan servo circuit 3 at a constant rotation speed. The magnetic heads 4a, 5a and 4b, 5b have different azimuth angles,
The disk 6 is mounted on the disk 6 at an opposing angle of 180 ° and is rotated together with the disk 6 by a disk motor 7.
Further, in the above magnetic head, 4a and 4b, and 5a and 5b also have mutually different azimuth angles and adjacent tracks are formed on the tape 1. At this time, the tape 1 is wound more than 180 ° around the disk 6, so that the heads 4a and 5a or 4b and 5b are in contact with each other on the tape 1 at the same time, that is, on the track, the shaded area in FIG. And an overlap portion corresponding to the front and back thereof is formed. Two magnets 8a and 8b are attached to the disk 6 at an opposing angle of 180 °. The tack head 9 detects this and tacks a tack pulse (c in FIG. 2) synchronized with the rotation of the magnetic head. Obtained from the head 9. The tack pulse from the tack head 9 is phase-adjusted by the phase adjusting circuit 10 so that the heads 4a, 4b, 5a and 5b and the tape 1 have a predetermined relative positional relationship, that is, specifically, shown in FIG. 2c. As time t ₀
After being delayed, the output is supplied to the pulse generation circuit 11. From the pulse generation circuit 11, a pulse having a duty ratio of 50% synchronized with the rotation of the heads 4a-5b (d in FIG. 3, d,
Hereinafter, this is referred to as a head switching signal) is output. On the other hand, reference numeral 140 in FIG. 1 is a synchronization information output circuit, which has terminals 201, 2
The vertical synchronizing information VS (b in FIG. 3) based on the horizontal synchronizing signal HD and the vertical synchronizing signal VD input from 02 is output. The vertical synchronization information VS is supplied to the disk servo circuit 12 as a servo reference signal for recording. This disk servo circuit
In FIG. 12, the vertical synchronization information VS from the circuit 140 and the head switching signal are both phase-synchronized with each other, more specifically, as shown in FIG. 3, the vertical synchronization information VS (b in FIG. 3) and Phase difference time with the head switching signal (d in FIG. 3)
The rotation of the disk motor 7 is controlled so as to be t ₁ .
Also, the above is the information of the vertical synchronization unit as the servo reference signal.
Although VS is used, similar control can be performed even if the servo reference signal is a signal having a frame period.

Here, in general, one field of a video signal is divided into n segments into n segments, and each segment is further divided into, for example, two channels to divide the video signal of one field into 2n tracks. The case of recording will be described below as an example. First, assuming that the field frequency of the video signal is ₀ , the rotation number M of the disk motor is determined by the disk servo circuit 12 so as to satisfy the following equation.

Specifically, assuming a high-definition TV signal with 1125 scanning lines as the input video signal, ₀ = 60Hz, n = 3, therefore, in the case of 3 segment recording with M = 90rps from the above equation (2) explain.

Now, a 180 ° period in the longitudinal direction of the track (see FIGS. 3 and 4).
If the number of horizontal scanning lines (the number of lines) X of the video signal per track that can be recorded during the period (T shown in the figure) is N, and the number of lines per field is N, Given in. Substituting the number of lines per field of high-definition TV signal N = 562.5 into (2) to obtain X, X = 93.75 (book) (3). In the present invention, as will be described later, during the period T of 180 ° in the longitudinal direction of each track, a video signal of [X] (a maximum integer not exceeding X, [X] = 93 in the formula (3)) lines or less is generated. It is to be recorded.

In the embodiment shown in FIG. 1, when the number of lines recorded in the period T is [X] N ₁ = 85: segment 1,3,5 N ₂ = 86: segment 2,4,6 Where the video signal of the first field (odd field) is the segments 1, 2, and 3 and the video signal of the second field (even field) is the segment 4,
Record at 5 and 6. The subscripts 1 to 512 shown in FIGS. 3 and 4 indicate the line numbers of the video signal in one field recorded on the tape.

The signal processing system during recording will be described again with reference to FIG.
In FIG. 1, 200a, 200b and 200c are input terminals for R signal, G signal and B signal respectively, and 300a and 300b are AC terminals respectively.
These are video signal output terminals for h, B-ch to be recorded. 101 is a color difference signal C ₁ , C from the input video signal from terminals 200a, 200b, 200c
₂ A matrix circuit that generates a luminance signal Y. 102,10
3, 104 are input color difference signals C ₁ and C ₂ and input luminance signal Y, respectively.
To a digital signal, 105 is a reference clock generation circuit that generates a reference clock that is phase-locked (GEN LOCK) with the input horizontal synchronization signal, 106 is a write clock generation circuit, 107 is a vertical filter, and 108 and 109 are A line selection circuit for switching and selecting a signal for each line, 110 and 111 are C
System and Y system memory, 112 write address generation circuit, 113 and 114 switching (SW) circuit, 115 synchronous / burst generation ROM, 116 read address generation circuit, 117 read start signal generation circuit, 118 read clock The generation circuits 119 and 120 are D / A converters.

The write clock generation circuit 106 generates a sampling clock by dividing the reference clock generated by the reference clock generation circuit 105, and the C system A / D converters 102, 1
A clock having a frequency of c is supplied to the Y-system A / D converter 104.
To send the clock _Y becomes frequency, further supplies to the write address generating circuit 112 to the clock. The write address generation circuit 112 is composed of a counter and the like, and HS, VS supplied from the synchronization information generation circuit 140 which receives the vertical synchronization signal VD and the horizontal synchronization signal HD and generates synchronization information (horizontal HS, vertical VS). A write address synchronized with is generated and supplied as a write address signal for the memories 110 and 111. This address signal is sequentially updated by the horizontal synchronization information HS every horizontal scanning cycle. Therefore,
The video signals input from the terminals 200a, 200b, and 200c are C ₁ and C _{2 according} to the write clock output from the circuit 106.
The signal is sampled at a frequency of c, and the Y signal is sampled at a frequency of _Y , and the C-system A / D converters 102 and 10 are respectively sampled.
3. The Y system A / D converter 104 sequentially converts the digital data into digital signals, and these digital data are sequentially written in the memories 110 and 111 in units of horizontal scanning periods in accordance with the address from the circuit 112.

Here, the memories 110 and 111 respectively have memories for two channels of A-ch (A channel) and B-ch (B channel), and the input digital data is A-ch, It is distributed to each B-ch memory (divided into two channels). The line selection circuits 108 and 109 realize such a function. For example, data of odd lines (1,3,5, ...) In the A-ch memory and data of even lines (2,4) in the B-ch memory. , 6, ...) data is written.
In the case of the C-system memory, since there are two types of color difference signals C ₁ and C ₂ , for example, C ₁ is written in the odd line and C ₂ is written in the even line, and recorded and reproduced as a line sequential signal. Therefore, C
In the signal, it is necessary to limit the vertical band, and the vertical filter 107 limits the vertical band after A / D conversion.

It should be noted that the approximate memory capacity of the memories 110 and 111 only needs to be able to store information for several tens of lines of the input video signal, and it is not necessary to provide a large capacity memory such as a field memory or a frame memory. An example of the memory configuration is shown in FIG. FIG. 7 shows an example of the configuration of the Y-system memory 111 shown in FIG. 1, which includes an A-chY system memory 111-a and a B-chY system memory 111-.
Each b is composed of _four memory banks a _{1 to} a ₄ and b _{1 to} b ₄ , and one memory bank has a data capacity of, for example, 8 lines. First, 8-bit digital data sampled by the Y-system A / D converter is input to the data input terminal 130. The selection circuit 109 is a circuit for selectively switching which of the A-ch memory and the B-ch memory the input data is sent out. In this embodiment, the odd line data is A-ch and the even line data is B. Input to -ch memory. A-ch memory 111-a, B-ch memory 111-
The input side of b is provided with switches 111-a ₁ and 111-b ₁ for switching the memory bank at the time of writing, and the output side is provided with switches 111-a ₂ and 111-b ₂ for switching the memory bank at the time of reading. . The memory capacity per bank is as described above
Since it is 8H, the line numbers of each memory bank and the data stored in it are as shown in the table of FIG. That is, for example, the first eight lines (1,3,5,7,9,11,13,15 in the line number) of the odd lines are stored in the memory a ₁ , and the 17th and subsequent lines are stored in the memory a ₂ . The data of line 65 and subsequent lines are stored in the memory a ₁ again. With such a memory configuration, the switch 111 for selecting the write memory bank
-A ₁ and switch to select read memory bank 111-a ₂
By appropriately controlling and, it is possible to avoid overlapping of writing and reading on one memory.

Regarding the control of the above switches, switch 111 during writing
-A ₁ and 111-b ₁ operate according to the line number of the input video signal. Designation of these switches and the write address on the memory is performed by the write address generation circuit 112.
Done by

FIG. 9 is a more detailed block diagram of the write address generation circuit 112, and FIG. 10 is a timing diagram showing its operation. As shown in FIG. 9, the write address generating circuit includes a line counter 112-1, which receives the synchronization information VS and HS as inputs, a decoder 112-2 which decodes the output result of the line counter 112-1, and an output result of the decoder. Line counter 112-3 using HS as a clock source and a decoder 112-4 for decoding the output result of the counter, OR gate 112-6, write clock WCK, and the output result of the OR gate as reset input It is composed of a counter 112-5. First, the line counter 112-1 is reset by the vertical synchronization information VS sent only once in each field, and counts the number of horizontal synchronization information HS sent once every horizontal synchronization. . Decoder 112-2
Outputs a signal R1 that changes from L level to H level when the counter 112-1 reaches a predetermined count value, for example, 50. Next, the line counter 112-3 starts counting with HS as a clock from the time when the signal R1 becomes H level. The least significant bit Q ₀ of the line counter 112-3 is used to determine whether the line number is odd or even. When the line number is odd, that is, when Q ₀ or the signal S is at L level, the selection circuit 109 of FIG. As a result, the data is transferred to the memory on the A channel side. Conversely, when the line number is even,
That is, when Q ₀ or the signal S is at H level, the selection circuit 109 selects the B channel side, and the data is transferred to the memory on the B channel side. Next, the _2nd , _3rd , and 4th bits of the line counter 112-3, that is, the 3rd bits of Q ₁ , Q ₂ , and Q ₃ are the address signal A8 for giving the upper 3 bits of each memory bank having the capacity of 8 lines. , A9, A10, and is updated every two lines. Whether the data of which line number to each memory bank is the memory is as shown in FIG. 8, the control Are the SW 111-a _1, and 111-b ₁ of the switch of Figure 7. These switches are the decoder 11 of FIG.
Controlled by the outputs M1 to M4 of 2-4, when M1 is at the L level, SW111-a ₁ and 111-b ₁ select the memories a ₁ and b ₁ ,
Hereinafter, memories a ₂ and b ₂ when M2 is L level, memories a ₃ and b ₃ when M3 is L level, and memories a ₄ and b ₄ when M4 is L level.
Are selected respectively.

On the other hand, the counter 112-5 gives the addresses A0 to A7 for the data in one horizontal synchronization interval, and the write clock
Using the WCK as a clock, the count value is reset for each horizontal synchronization information HS, and when the count value of the line counter reaches 512, for example, the OR gate 112-
Controlled via 6. In this embodiment, the address within one horizontal synchronization period is 8 bits, that is, the addresses 0 to 255 are given. The write address is controlled as described above, and the input video signal is sequentially written in the memory as digital data.

The above operation has been described with respect to the Y-system memory 111, but the basic operation is exactly the same for the C-system memory 110 as well, and within one horizontal period due to the difference in the sampling frequencies _Y 1 and c of the Y-system and the C-system. Only the number of data is different.

Next, the read operation from the memory will be described with reference to FIG. 1 again. First, the read clock generation circuit 118 generates the read clock RCK from the reference clock generated by the reference clock generation circuit 105. The read address generating circuit 116 counts the read clock RCK and generates a read address in synchronization with the read start generated by the read start pulse generating circuit 117 which receives the tack signal of the cylinder or the head switching signal. The above-mentioned read start pulse is the signal shown in FIG. 3, which is a constant delay amount t ₂ and t ₃ from the rising or falling edge of the head switching signal (FIG. 3d) (e in FIG. 3e). ) Indicates a given pulse. Reading of data from the memory is carried out in synchronization with the above read start pulse. Next, FIG. 11 shows an embodiment of a read address generating circuit for realizing this operation.

In FIG. 11, 116-9 is a read start pulse RS sent from the read start pulse generating circuit 117.
, 116-10 is an input terminal of the read clock RCK. The read start pulse RS input from the terminal 116-10 is synchronized with the read clock RCK from the terminal 116-9 in the latch circuit 116-1. The output from the latch circuit 116-1 is input to the reset terminal R of the counter 116-4 via the OR gate 116-3, whereby the counter 116-4 is reset. The read clock RCK from the terminal 116-9 is supplied to the clock terminal CK of the counter 116-4 through the AND gate 116-2. Reference numeral 116-8 is an RS flip-flop, which is set by the output from the circuit 116-1, so that the output Q becomes high level "H". As a result, the clock RCK from the AND gate 116-2 and the terminal 116-9 is supplied to the counter 116-4 to start counting the clock. Reference numeral 116-5 is a decoder that decodes the count value of the counter 116-4, and the count value of the counter 116-4 is N ₀ (in the case of the present embodiment, equal to the number of clocks of the write clock WCK within one horizontal scanning period). Pulse is output when the value of N ₀ is set so that The output pulse (g in FIG. 3) from the decoder 116-5 is supplied to the reset input R of the counter 116-4 via the OR gate 116-3, which resets the counter 116-4 again and the calculation is performed. It will be restarted. The above operation is performed by the decoder 116-
Repeated based on the output pulse from 5. counter
The calculation outputs A0 to A7 from 116-4 are supplied as the lower 8 bits of the read address signal of the memory 111.

In the above series of operations, the output pulse from the decoder 116-5, that is, the pulse generated at the timing g in FIG. 2, is generated at every 1 horizontal synchronization interval in the recording signal, and the head position of 1 horizontal synchronization interval is generated. The signal processing of one horizontal synchronization interval, which will be described later, for example, addition of a horizontal synchronization signal or a burst signal is performed with this signal as a reference.

Next, the output from the decoder 116-5 is the counter 116-6.
Input to the clock input CK of. In addition, the counter 116
The output from the latch circuit 116-1 is supplied to the reset input R of -6, the counter 116-6 is reset by this, the count value of the counter 116-6 is decoded by the decoder 116-7, and the counter 116-6 is decoded. Pulse when the count value of 116-6 becomes N ₁ (N ₁ = 85 is set in this embodiment)
Output N ₁ . On the other hand, the decoder 116-7 is a signal L1~L4 also generates for controlling the switches _{111-a 2, 111-b} 2 in FIG. 7. The signal L1~L4 is a signal that forms the same function as M1~M4 controlling the switches _{111-a 1, 111-b} 1, select whether read data from either bank of the four memory banks Signal to do.

The count values Q ₀ , Q ₁ , Q ₃ of the counter 116-6 are supplied as the upper 3 bits of the read address signal of the horizontal scanning unit of the memory.

Next, the decode pulse N ₁ output from the decoder 116-7 is input to the reset terminal of the flip-flop circuit 116-8, and its output Q (indicated by i in FIG. 3) is low level "L". Become. As a result, the AND gate 116-2 is closed and the counting of the counters 116-4 and 116-6 is temporarily stopped.

The above operation is the read start pulse R from terminal 116-10.
It is repeated in the cycle T of S. Here, data is sequentially read from the memories 110 and 111 according to the read address signal generated by the above operation, and the C of the A channel is read.
The data from the system and Y memories are transferred to the switching circuit 113, B
The data from the C-system and Y-system memories of the channel are input to the switching circuit 114, respectively. On the other hand, 115 is a synchronization and burst generation ROM, which has a function of generating digital data required to generate a horizontal synchronization signal and a burst signal to be added in units of horizontal synchronization of a signal to be recorded. This ROM is also controlled according to the read address generated by the read address generation circuit 116, and RO is controlled at a predetermined timing.
The M output data is sent to the switching circuits 113 and 114. Switching circuit 11
At 3 and 114, continuous data is sent to the next stage by appropriately switching the output data from the synchronous / burst generation ROM, the output data from the Y system memory, and the output data from the C system memory. Here, the data of the A channel is sent from the switching circuit 113 directly to the D / A converter 119, while the data of the B channel is transmitted.
The channel data is once input to the delay circuit 120-1, and is sent to the D / A converter 120 after a predetermined delay time.

It will be described with reference to FIG. 2 that the delay circuit 120-1 as described above is necessary only for B channel data. FIG. 2 (a) shows a magnetic tape 1 and magnetic heads 4a, 4b and 5a, 5b.
It is a figure which shows a part of track formed by. As described above, the magnetic heads 4a and 5a are heads for A channel, and the magnetic heads 4b and 5b are heads for B channel. FIG. 2 (b) shows the mounting position of the head on the cylinder, and among the magnetic heads,
4a and 4b or 5a and 5b are respectively arranged at a distance of 1 in the longitudinal direction of the track as shown. Therefore, these heads have the relative positions on the tape as shown in FIG. 2 (a), and the A channel heads, that is, 4a and 5a, are different from the B channel heads, that is, 4b and 5b. On the tape, it is at a position preceded by a distance l. Therefore, in order to realize the H arrangement between the A channel track and the B channel track, it is necessary to delay the recording signal supplied to the B channel head by a time corresponding to a distance of 1 on the tape. . Here, if the relative speed between the tape heads is v _t , the above delay time is l / v _t
In the delay circuit 120-1, the input data may be delayed by the time l / v _t and then output to the D / A converter 120.

In the above embodiment, a method of delaying the output of the B channel with respect to the output of the A channel is provided with a delay circuit before D / A conversion. However, as another embodiment, the data from the memories 110 and 111 is used. A method of reading only the data of the B channel after delaying the data of the A channel by a predetermined time at the time of reading may be considered, and the effect is the same as that of the above embodiment.

Now, the respective data of the A channel and the B channel input to the D / A converter as described above are converted into the D / A converters 119 and 120.
Are converted into analog video signals by the terminals 300a and 300b
Is output to. The line arrangement in the recorded video signal output to the terminals 300a and 300b is shown in Fig. 3 h ₁ (A channel),
It becomes as shown in h ₂ (channel B).

As a result of the above, the arrangement of the video signals on the tracks recorded on the tape is as shown in FIG.

In FIG. 4, T ₁ a, T ₂ a, T ₃ a, T ₄ a are heads 4a in FIG.
, And 5a are alternately recorded and formed. Tracks T ₁ a, T ₃ a, ... Are recorded by the head 4a, and tracks T ₂ a, T ₄ a, ... Are recorded by the head 5a. On the other hand, T ₁ b, T ₂
b, T ₃ b and T ₄ b are B channel tracks which are alternately recorded and formed by the heads 4b and 5b.
_{T 1 b, T 3 b,} ... are the tracks T ₂ b in the head 5b, T ₄ b, ... it is recorded.

In addition, as the signals to be recorded on each track in FIG.
In order to include the vertical synchronization information of the field period in at least one of the recording video signals output to the recording signal output terminals 300a and 300b in the figure, specifically, the tracks T ₁ a and T ₄ a in FIG. Vertical synchronization information is provided at either or both of the positions indicated by line numbers 1, 3, 5 of ..., or the positions indicated by line numbers 2, 4, 6 of tracks T ₁ b, T ₄ b, ... The vertical synchronization information may be generated and output from the circuit 115 shown in FIG. 1 so as to be recorded.

As described above, if the vertical synchronization information is recorded in the vicinity of the scanning start point of the track in relation to the vertical scanning period of the video signal, its position can be easily detected during reproduction, and the field identification of the reproduction video signal can be performed. It is possible to identify the playback track.

Further, in addition to the above-mentioned vertical synchronization information, a triangular wave-like signal waveform, which has been already proposed, for use in correcting non-linearity of a reproduced video signal, that is, a ramp waveform may be recorded. In this case, the vertical synchronization information is recorded on a line immediately after the line on which the vertical synchronization information is recorded, or on a line near the line. By recording at such a position, it becomes possible to first detect the vertical synchronization information at the time of reproduction and further detect the ramp waveform with the position of the vertical synchronization information as a reference.
There is an advantage that the detection of the ramp waveform for non-linearity correction during reproduction described above becomes more reliable, and the non-linearity correction operation is performed stably and surely.

Further, as the above-mentioned vertical synchronization information, in order to discriminate between odd and even fields, it is possible to make the length of the vertical synchronization information different between the odd field (first field) and the even field (second field). Although not shown, it is also possible to record information for discriminating odd / even of fields after the vertical synchronization information.

The broken lines AA 'and BB' in FIG. 4 correspond to the rising edge and the falling edge of the waveform of j in the waveform diagram shown in FIG. AA ') and end point (BB') are shown. Also, the shaded area in FIG. 4 is a redundant portion that is necessary when the head is switched during reproduction, and the head rotation angle is 180 degrees.
In the range of °, one horizontal synchronization interval (hereinafter referred to as 1H period) in the recorded video signal on the input side of the odd-numbered track, and a period slightly longer than half of the 1H period on the output side of the track, Has become the length of. On the other hand, on the entry side of even-numbered tracks It has a length of ΔH on the output side. In this way, the length of the redundant portion is determined, and at the time of recording, the signal is recorded in synchronization with the rotational phase of the head by the above-described method, so that the relative position shift between tracks is achieved. Also, it is possible to absorb the temporal fluctuation (jitter) of the rotary head at the time of recording, and to realize a so-called H arrangement between adjacent tracks. In addition, during playback,
As shown in FIG. 4, it is possible to eliminate the discontinuity of the video signal due to the head switching by surely performing the head switching in a specific area (that is, the shaded area in the drawing).
The overlapping portion between the heads may be a minute portion including the shaded portion in FIG. 4, and the utilization efficiency of the recordable area on the tape can be improved. That is, according to the recording method shown in FIG. 4, by providing the redundant period (shown by the hatched portion in the figure), head switching is performed during this period during reproduction, so that the video signal portion is not affected at all. It is possible to completely eliminate the skew distortion on the reproduction screen due to head switching without generating a continuous portion.

Next, an example of the number of sample clocks within 1H required for recording and forming the track pattern as shown in FIG.
Shown in Figure 12.

In FIG. 12, (a) shows an area for head switching (hatched area, hereinafter referred to as head switching area) at 1H on the input side in the head scanning direction and on the output side. In the case of (b), the head switching area is on the inlet side. The case of ΔH on the output side is shown. Here, assuming that the frequency of the sampling clock in the recording signal is 25.2 MHz, for example, 1
Assuming that H is formed by 1616 samples, in (a), an effective area (a video signal etc. is recorded, hereinafter referred to as an active area) other than the head switching area is 85H, (b).
Then, the active area becomes 86H, and the track pattern of FIG. 4 can be formed.

Here, if Δ is formed to have a length corresponding to 216 samples, the length of one track is (86.5 + Δ) H in both cases (a) and (b). Is 1616 samples x 86.5H + 216 samples, total
It will be 140,000 samples. It has a clock frequency of 25.2M
Multiplying the reciprocal of Hz, that is, the time required for one sample, gives 14
Scanning time per track is 0,000 × 1 / 25.2 × 10 ⁶ .
5.55msec can be obtained. Strictly speaking, however, the scanning time per track slightly varies due to the control error of the rotation servo system of the cylinder, but as described above, in the present invention, the scanning time per track is synchronized with the rotation phase of the cylinder. Since the recording signal as shown in FIG. 12 is generated, the scanning time of one track and the time determined by the number of samples forming one track always match. Specifically, if the rotation of the cylinder is slightly slower than the normal number of rotations and therefore the scanning time per track becomes long, the number of samples corresponding to the above Δ increases, and one track of the recording signal corresponds to one track. The length also becomes longer according to the scanning time. On the contrary, if the rotation of the cylinder becomes faster, the number of samples corresponding to Δ increases, and the length of one track of the recording signal becomes shorter according to the scanning time. As described above, the fluctuation of the scanning time per track caused by the fluctuation of the rotation speed of the schilling can be absorbed by increasing or decreasing the number of samples corresponding to Δ.

Next, an example of the structure within the above 1H is shown in FIG. In the example of FIG. 13, 1H is formed by 1616 samples, which is made up of horizontal blanking of 84 samples and a video signal of 1532 samples. In addition, the horizontal blanking is composed of a horizontal synchronizing signal of 30 samples, a burst signal of 24 samples, and the like, and one burst signal forms four waves. Therefore, the frequency of the burst signal is 6.3 MHz, which is 1/4 of that of the clock frequency, which is 25.2 MHz.
As will be described later, this burst signal serves as a signal that provides a reference on the time axis when generating the sampling clock (or write clock) during reproduction. At this time, when one wave of the burst signal is 4 clocks as in the present embodiment, the number of samples forming 1H is set to a multiple of 4 (1616 in this case), so that bursts in a certain horizontal synchronization interval are generated. The phase of the burst signal between the signal and the next adjacent horizontal synchronization becomes continuous, and the phase of the write clock obtained at the time of reproduction also becomes continuous, which is convenient for the circuit operation of clock generation.

The recording pattern shown in FIG. 4 has been described above, but the present invention is not limited to the recording pattern shown in FIG. 4 and has the same effect with other recording patterns. 5 and 6 are recording patterns on a magnetic tape in another embodiment according to the present invention, in which the reference numerals in the drawings indicate the third.
It is the same as in the case of the figure.

First, in the recording pattern shown in FIG. 5, the rotation angle of the head
In the 180 ° range, at the head entry side of tracks T ₁ a, T ₁ b, T ₃ a, T ₃ b, ... There is a redundant part of Has a redundant part of. On the other hand, trucks T ₂ a, T ₂ b, T ₄ a,
There is no redundant portion on the inlet side of the head of T ₄ b, ... And εH on the outlet side. Here, generally, in the video signal recording / reproducing apparatus of the helical scan type rotary head system, the winding angle of the tape around the rotary cylinder is larger than 180 °, and the heads facing each other have an overlap of at least about ± 1H. There is. Therefore, the fifth
In the figure, for example, on the head entry side of the track T ₂ a, there is no redundant portion described above, and the video signal, more specifically, the signal of the line number 171 is recorded from the beginning. Prior to the above video signal, the track
The same redundant part as that recorded on the output side of T ₁ a is recorded. The above situation is the same between other tracks, and there is always signal overlap when the head scan changes from one track to the next. Therefore, in the example shown in FIG. There is such a redundant period, and during this period, head switching during reproduction can be appropriately performed.

FIG. 6 shows a recording pattern when ε is set to 0 in FIG. 5, and a redundant period of 1 / 2H always exists between the tracks. In Figure 3-2, T ₁ a, T ₁ b and T
Track deviation between ₂ a and T ₂ b, (denoted here as αH) Therefore, the redundancy period By this, it becomes possible to realize the H arrangement between the tracks T ₁ b and T ₂ a. At this time, the redundant period between each track is Under the above condition, it becomes possible to minimize the redundancy period.

FIG. 14 is a block diagram of an embodiment of a reproducing apparatus for reproducing the video signal recorded on the magnetic tape as described above as shown in FIG. 4, and FIG. Waveform diagrams of respective parts of are shown respectively.

In FIG. 14, since it can be shared with a part of the recording apparatus of FIG. 1, the common parts are denoted by the same reference numerals. Since the operation of these common parts is the same as the above, the description thereof is omitted.

The video signal alternately reproduced from the tape 1 by the heads 4a, 4b and 5a, 5b is amplified to a predetermined level by the reproduction preamplifier 400, and then output from the heads 4a, 5a, that is, the output on the A channel side. Signal 400-1 is A-ch time base correction circuit 4
10 is input, while the output from the heads 4b and 5b, that is, B
The output signal 400-2 on the channel side is input to the B-ch time base correction circuit 420. In A-ch time base correction circuit 410, the reproduced signal is demodulated by first FM demodulator 411, FIG. 15 a ₁
A video signal such as On the other hand, also for B-ch, a video signal in the form of a ₂ is similarly obtained. The following operation will be described only for the A channel, but the same operation is performed for the B channel. Now, the demodulated video signal is next input to the sync separation circuit 412,
Here, the vertical synchronization information and the horizontal synchronization information (FIG. 15d) recorded only once in one field as shown in FIG. 12c are detected and separated and output. Here, the top 1H of one field is assigned as the vertical synchronization information.
Next, the synchronization information is sent to the head switching signal generation circuit 41.
Entered in 8. In the head switching signal generation circuit 418, based on the vertical synchronization information and the horizontal synchronization information, the fifteenth
Find the last horizontal sync information for each segment as shown in Figure e. Next, as shown in FIG. 15, a square wave having a constant delay time τ'is generated from the signal e. When the signal is divided by 2 in synchronization with the falling edge of the above signal, a signal as shown in g is obtained. Controls the input from the head with the reproduction preamplifier so as to select the signal of the head 5a.

FIG. 16 shows an example of a preamplifier capable of selecting an input signal from each head by the above method. As described above, the reproduction signals from the heads 4a and 5a are selected by the switching means 469 controlled by the A-ch head switching signal and then output to the A-ch output terminal 465 as a continuous signal. The above operation is the same for the B-ch, and the head
The reproduction signals from 4b and 5b are selected by the switching means 470 by the B-ch head switching signal, and then the B-ch output terminal 467.
Is output as a continuous signal. According to the method described above, the signals from the two heads facing each other are switched in the head switching area provided in the signals during recording, so that the switching of the heads does not cause loss of the video signal.

The reproduced signal processing operation will be described again with reference to FIG. The signal demodulated by the FM demodulator 411 is then input to the A / D converter 414 and converted into digital data. At this time, the sampling clock used for the A / D conversion is the clock generated by the write clock generation circuit 413, and is the clock synchronized with the synchronization information in the reproduced signal after demodulation or the burst signal shown in FIG. Therefore, the clock is a clock that is synchronized with the temporal fluctuation generated in the reproducing process, that is, the jitter, and the digital data sampled by this clock is processed using the clock from the reference clock generation circuit 438 with the crystal oscillator. As a result, the above-mentioned jitter can be removed from the reproduced video signal. Next, the digital data output from the A / D converter 414 is sequentially transferred to the A-ch memory according to the write address generated by the write address generation circuit 415.
The data is written in 416 and then output from the memory according to the read address generated by the memory address generation circuit 436. Here, the read address is the reference clock generation circuit 43.
It is generated based on the crystal-locked clock from 8 and the jitter is removed from the digital data when it is read from the A-ch memory 416. The digital data output from the A-ch memory 416 is latched by the latch 417.
The C-system data is transferred to the A-ch C-system memory 430 and the Y-system data is transferred to the A-ch Y-system memory 431 at a predetermined timing via the. The series of operations described above is similarly performed for the B-ch signal, and the output data from the B-ch time base correction circuit 420 is the B-ch C system memory 432, the B-ch Y system memory 4
Allotted to 33 and stored. Next, the output data from the A-chC system memory 430 and the B-chC system memory 432 is input to the selection circuit 434, where the data is selected and output in a predetermined order, and the C-system D / A converter 439 and Entered in 440.
On the other hand, the output data from the A-chY system memory 431 and the B-chY system memory 433 is input to the selection circuit 435, and similarly the data is selected and output, and is input to the Y system D / A converter 441.
As a result, C ₁ , C ₂ and Y signals are output from each D / A converter, and these signals are output as R, G, B signals via the matrix circuit 442.

Further, in the synchronization signal generation circuit 437, the reference clock generation circuit 4
Horizontal sync signal HD based on the clock from 38 (Fig. 15i),
And the vertical sync signal VD (FIG. 15j) is generated. Furthermore, a 30 Hz reference signal (R
EF30) is generated, and this signal controls the rotation phase of the cylinder as a reference signal of the servo system during reproduction. Specifically, the reference signal REF30 is a signal shown in h of FIG. 15, and the rotational phase of the disk motor is controlled so that the head switching signal g is always separated from REF30 by τ ″.

The capstan motor 2 is rotationally controlled by a capstan servo circuit 3. The capstan servo circuit 3 controls the relative positions of the magnetic tape 1 and the heads 4a, 4b and 5a, 5b to control the heads. A track control system for accurately scanning the track on which is recorded and reproducing the signal is used, and a conventionally known one is used.

By the servo control described above, the timings of the video signal reproduced from the head, the write operation to the memory in the time axis correction circuits 410 and 420, and the read operation from the memory are always kept in a constant relationship. A series of signal processing is performed. As a result, the reproduced video signals of R, G, B output to the terminals 450a, b, c are, as shown in FIG. 15k, not accompanied by skew distortion, the time axis fluctuation is removed, and the original video signal is removed. Will be a faithful restoration of a stable video signal.

As is apparent from the above, the possible skew correction amount by applying the present invention is (1 + Δ) H. However, H is one horizontal synchronization period of the recording signal (1616 clock periods at 25.2 MHz sampling in this embodiment), and Δ is 216 clock periods. It can be said that this value is a sufficient skew correction allowance for a skew amount of 0.1H or less that occurs during actual reproduction.

Further, since the above-described redundant period (1 + Δ) H is generated in synchronization with the rotation of the head during recording, the redundant period (1 + Δ) H is positioned at a fixed position on the tape as shown in FIG. The recording position does not change. As a result, compatible reproduction becomes easy and reliable, and the performance and reliability of the device can be significantly improved.

Further, in the embodiment of FIG. 1 described above, the generation timing of the read start pulse RS generated by the read start pulse generation circuit 117 (determined by τ ₂ and τ ₃ shown by e in FIG. ₃ ) of the head. By appropriately changing each scanning cycle T, as shown in the track pattern diagram of FIG. 4, it is possible to easily change the relative recording pattern in units of horizontal scanning lines between adjacent tracks and adjacent tracks. , An arbitrary recording pattern without being restricted by the amount of horizontal scanning line misalignment (αH shown in FIG. 4) at the track end determined by the relative speed of the tape 1 and the heads 4a, 4b and 5a, 5b. As a result, it is possible to reduce the interference due to crosstalk from adjacent tracks and adjacent tracks, and to provide a side effect such that a device with good image quality can be provided.

Further, as apparent from the above, according to the recording method of the present invention, all the video signals to be recorded and reproduced are completely processed within the scanning period T of the head (within 180 ° on the track), Further, according to the present invention, it is possible to easily detect the recording position on the tape in the head switching area existing at both ends of each track, and moreover, it is possible to surely detect the recording position from the reproduced video signal. It is possible to reduce the overlap area, which has been indispensable for the analog recording method VTR, up to several H to about 1H. In other words, this means that the effective area on the tape can be expanded by that amount, and as a result, a recording time can be increased, which is a secondary effect. Further, it is utilized as an area in which signals other than video signals, such as a digitized audio signal compressed in a time axis, which is conventionally known, or tracking control signals such as pilot signals, can be recorded by the amount of the overlap reduced. It is also possible to obtain high density recording of various signals.

Further, in the present embodiment, only the example in which the high-definition television signal is divided into two channels and the cylinder is rotated three times to perform the three-segment division recording is shown, but the arbitrary number of channel divisions and the number of segment divisions are also set. The present invention can be applied, of course, and has the same effect as described in the embodiment. Furthermore, the signals to be recorded are not only high-definition television signals in the baseband band, but signals that have undergone some kind of band compression, signals of current television systems such as NTSC, PAL, SECAM, and these current television systems. The present invention can be applied to a system having compatibility and an improved image quality such as resolution.

〔The invention's effect〕

As described above, according to the present invention, in a video signal recording / reproducing apparatus that divides an input video signal into a plurality of channels and divides into a plurality of segments for each channel and records, the skew and time axis from the reproduction signal. Fluctuations can be completely removed, and good and stable video signal recording / reproduction can be performed. Further, the H arrangement between adjacent tracks can be surely and easily realized, and the redundancy period in the recording signal required for head switching at the time of reproduction can be minimized, and the recording density of the tape can be increased. As a result, it is possible to easily realize an improvement in recording density and a longer recording time as compared with the conventional digital recording method, and it is possible to improve the cost, performance,
It is possible to obtain an effect such as a great improvement in reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal recording apparatus according to the present invention, and FIG. 2 is an enlarged view around the head thereof.
FIG. 3 is a waveform diagram of each part in FIG. 1, FIGS. 4 to 6 are tape pattern diagrams thereof, FIG. 7 is a configuration example of a video signal processing memory, and FIG. 8 is each stored in the memory. FIG. 9 is a block diagram showing an embodiment of a write address generation circuit according to the present invention, FIG. 10 is a waveform of each part thereof, and FIG. 11 is an example of a read address generation circuit according to the present invention. FIG. 12 is a block diagram, FIG. 12 is a diagram showing a pattern of one track of a recording signal according to the present invention, and FIG. 13 is a waveform diagram showing a format of a video signal during one horizontal synchronization according to the present invention.
FIG. 14 is a block diagram showing an example of a reproducing apparatus according to the present invention, FIG. 15 is a waveform chart of each part in FIG. 14, and FIG. 16 is a diagram showing an example of the structure of a reproducing head amplifier. 102, 103 ... A / D converter for C signal, 104 ... A / D converter for Y signal, 110 ... C signal memory, 111 ... Y signal memory, 115 ... Synchronization / burst signal generation ROM , 119 …… A
Channel D / A converter, 120 …… B channel D / A converter, 112 …… Write address generation circuit, 116 …… Read address generation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kyoichi Hosokawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-61-177083 (JP, A) 61-166284 (JP, A) JP 61-196407 (JP, A) JP 62-15983 (JP, A)

Claims (2)

[Claims] 1. A means for dividing a video signal of one vertical scanning period, which is composed of N horizontal scanning lines, into m (m is an integer of 2 or more) channels in units of the video signal of one horizontal scanning period. Means for further dividing the signal of each of the m channels into n (n is an integer of 1 or more) segments and at least two heads for each channel are provided. A helical scan rotary head in which the video signals in one vertical scanning period are dividedly recorded into a total of m · n tracks by performing head scanning n times by recording the two tracks adjacent to each other. Type video signal recording / reproducing apparatus, at least two rotary heads corresponding to each of the channels have an overlap area that is in contact with the magnetic tape at the same time. Per block of video signal of the [N /
m ・ n] (however, [N / m ・ n] is the maximum integer not exceeding N / m ・ n) within m ・ n blocks to include video signals corresponding to the number of horizontal scanning lines The dividing means and the recording of the m · n blocks on the m · n tracks in sequence, the video signals in the m · n blocks are arranged so as to be recorded in each block unit. In synchronism with the rotation angle of the rotary head, it has a time axis conversion unit for sequentially converting the time axis of each block in units of the horizontal scanning lines, thereby generating a redundant period of a predetermined length between the blocks, When one horizontal scanning period of the recorded video signal obtained by the time axis conversion means is set to 1H, m tracks adjacent to each other recorded by the one head scan and the next head scan adjacent to this track. Exist between m adjacent tracks recorded by Track deviation amount is αH (however, 0 <α
When ≦ 1), the redundancy period is minimum αH and maximum (1
A video signal recording / reproducing apparatus characterized in that it is set within a range of −Δ + α) H (where 0 <Δ <α), and the redundant period is recorded in the overlap area. 2. The time axis conversion means samples the effective portion in a horizontal scanning line of the video signal, and a signal obtained by time-axis converting the effective portion in units of the horizontal scanning lines has a predetermined number of samples. And a means for adding horizontal synchronization information consisting of a horizontal synchronization signal including a redundant portion of a predetermined period and a burst signal of a predetermined period with a predetermined number of samples, and within one horizontal scanning line of the video signal after the time axis conversion. The video signal recording / reproducing apparatus according to claim 1, wherein the total number of samples is set to be an integral multiple of the number of samples of one cycle of the burst signal.