JPH0771559B2 - Ultrasonic diagnostic equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an ultrasonic diagnostic apparatus for diagnosing a tissue in a subject using ultrasonic waves, and particularly, an improvement of a delay line is aimed at. The present invention relates to an ultrasonic diagnostic apparatus.

[Conventional technology]

Electronic scanning ultrasonic diagnostic devices have become widely used in recent years.

As is well known, an ultrasonic device of an electronic scanning system uses a probe with an ultrasonic transducer array in which a plurality of ultrasonic transducers (hereinafter, simply referred to as transducers) are linearly arranged in parallel. Several adjacent transducers are set as a group, and a driving pulse is given to each of the group of transducers with a predetermined delay time that is determined according to the direction of the transmitted ultrasonic beam and the position of the transducer in the beam. The ultrasonic waves are excited by ultrasonic waves.The excited ultrasonic waves from each transducer propagate in a radial direction and interfere with each other, canceling each other out in a certain region and strengthening each other in a certain region. Is a method of obtaining. Receiving is generally performed by the above-mentioned group of transducers used for transmission, and the detection signals of the group of transducers are delayed by the delay time at the time of transmission to align the time axes and then synthesize them. The received signal. Then, by shifting the above-mentioned group of transducers by one pitch at a time, the position of the generated ultrasonic beam is displaced, so that the transducer to be excited is electrically selected,
By controlling the excitation timing, linear scan can be performed, and sector scan can be performed at a desired position.

In such an ultrasonic diagnostic apparatus, at the time of receiving ultrasonic waves, a phasing addition method is currently used. This is a system in which ultrasonic wave signals from a certain echo source are adjusted to the same wavefront by delaying the respective time differences required to reach the surface of the transducer with a delay element.

An LC delay line, which is a combination of an intagance L and a capacitor C, is used as the delay element of the phased array method.

FIG. 5 shows an example of a receiving circuit using an LC delay line as a delay element. As shown in the figure, the ultrasonic echo from the echo source 2 enters a group of transducers 3 from 1ch (channel) to nch. The reception timing in each channel differs depending on the distance from the echo source 2. The reception echo is converted into an electric signal in each channel and output as a reception signal.

The reception signal output from the vibrator 3 in this way is sent to the reception circuit and delayed by the LC delay lines D ₁ , D _{2 to} Dn provided for each corresponding channel in the reception circuit 1. After that, they are added by an adder, and are added together so that their time axes match. That is, phasing addition is performed. In general
The LC delay line has a structure in which a combination of L and C circuits are connected in series in multiple stages. Some intermediate taps are provided on the way, and the intermediate tap is selected. By extracting the signal, the received signal is extracted with a desired delay time.

However, the LC delay line is expensive, the settable delay time is limited, and it is difficult to obtain the absolute accuracy.

(Problems to be Solved by the Invention) As described above, in the conventional ultrasonic diagnostic apparatus of the electronic scan system, the LC delay line provided in the receiving circuit thereof is a series of a plurality of L and C circuits connected in series. The intermediate taps are provided on the way, and the intermediate tap is selected, and the signal is extracted from the selected intermediate tap so that the received signal is extracted with a desired delay time. is there.

However, the LC delay line is expensive, the delay time that can be set is limited, and there are variations in performance among solids, and there are drawbacks in that the system remains problematic and has poor reliability.

In particular, the received signal input to the delay circuit is an analog signal, and the desired delay time is obtained by selecting the intermediate tap with a switch and extracting the signal, so noise due to this switching, etc. is mixed into the received signal. There is danger. On the other hand, for example, when performing dynamic focus during reception, it is necessary to switch the switch, but at that time, it is necessary to avoid mixing of noise.
However, if the photocass is dynamically changed because the tap is selected by the switch, it is difficult to avoid the switching noise from being mixed into the received signal.

Therefore, it is an object of the present invention to provide a highly reliable ultrasonic diagnostic apparatus without concern about performance variations among solids and noise contamination.

[Structure of Invention]

(Means for Solving Problems) In order to achieve the above object, the present invention is configured as follows.
That is, ultrasonic waves are transmitted to the object from a plurality of transducers arranged side by side in an array, and a delay circuit delays the received signals from the obtained transducers for phasing addition. In the ultrasonic diagnostic apparatus, the delay circuit is provided corresponding to the transducer, and corresponds to the AD conversion means for digitizing an analog reception signal for each channel of the transducer and the AD conversion means. The memory is provided with at least two systems of memory for temporarily storing digitized received signals, and the digital signals are read by alternately switching the read / write of the two systems of memory at a timing according to the delay time of each channel. A delay unit that gives a desired delay to the converted received signal, and divides the plurality of transducers into a plurality of blocks, and from each of the delay units The output signals of (1) are sequentially added between adjacent channels, and the addition results of each block are added to perform phasing addition of the received signals of all channels.

(Operation) In such a configuration, the present apparatus uses two systems of memory as a delay circuit, and these two systems of memory are used alternately for read / write and the read / write mode is set to a predetermined address according to the delay time. Switch every time the number is updated. Therefore, when one memory is in the read state, the other memory is in the write state, and the memory in the write state stores the input data at the addresses that are sequentially updated. Further, the stored data is read from the memory in the read state from the addresses which are sequentially updated, and the required delay is thereby given. In this way, after the analog reception signal is digitized by the AD conversion means provided for each channel of the vibrator, the delay unit gives a predetermined delay to the digitized reception signal. Then, between the adjacent delay units, the received signals given the delay are added,
The operation of sequentially adding the addition result and the reception signal output from the other delay unit is repeated to obtain the phasing-added output.

By this phasing addition, the respective time differences required for the ultrasonic signal from a certain echo source to reach the surface of the array-shaped transducer can be added and synthesized in a state where the same wavefront is adjusted by delay.

As described above, in the device of the present invention, the read / write timing is used to obtain the delay of the data transmission, so that the read / write switching of the memory and the update of the read / write address can be arbitrarily performed. You will be able to get the delay time. Therefore, since the delay time is adjusted by accumulating and sending out the data, there is no switching by the switch unlike the LC delay line, and there is no fear of noise mixing due to the switching. Further, since the delay is due to the writing and reading control of the memory under the control synchronized with the reference signal which is the reference of the operation of the system, the desired delay time can be obtained with high accuracy and the reliability is improved. . Further, since the digital circuit is used, the delay circuit can be constructed at low cost.

Further, according to the device of the present invention, the analog reception signal is digitized by the AD conversion means provided for each channel of the vibrator, and after the predetermined delay is given to the digitized reception signal by the delay unit, By adding the received signals to which an arbitrary delay is given between the delay units and repeating the operation of sequentially adding the addition result and the received signals output from the other delay units to perform phasing addition, Since the number of data stored in the delay unit can be minimized, the delay circuit can be made smaller than before, and since the same delay unit can be connected, the number of components including the bus line can be reduced and the circuit configuration can be simplified. Can be realized.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 is a block diagram showing a configuration of a delay circuit according to the present invention, and FIG. 2 is a block diagram showing a configuration of a delay unit.

The delay circuit is, as shown in FIG. 1, AD conversion circuits AD1 to ADn for obtaining the received signals of the respective channels of the ultrasonic transducer through a buffer and digitizing them, and these AD conversion circuits AD1 to AD.
Delay units DU1, to DUn for receiving signal delays provided corresponding to Dn, these delay units DU1 to DUn
It is composed of an adder circuit ADER for adding the received signal outputs after delay due to. The delay unit DU1 (to DUn) is a buffer register BR which temporarily holds the received signal data of the corresponding channel digitized by the AD conversion circuit AD1 (to ADn) as shown in FIG. register
First and second static memories (RAM; random access memories) SRAMA, SRAMB for storing data given via BR, controlled by a control means (not shown), in synchronization with a clock signal given from the outside. The first and second operations are performed and the addresses are sequentially updated by the number of times corresponding to the set delay time, and when the addresses are updated by the number of times, the original addresses are returned to and the above operations are repeated.
Static memory SRAMA, SRAMB read / write
Read / write address generation circuits RAGA, RAGB for generating address signals, data from the buffer register BR or first or second static memory SRAMA, SRAM
Multiplexer 1 register MR that selects and holds the read data of B for the first time, this multiplexer register MR
The adder circuit ADD for adding the held data and the data from the other delay circuit, and the register REG which temporarily holds and outputs the output of the adder circuit ADD.

Said first and second static memories SRAMA and SRAMB
The control means (not shown) applies a read / write signal so that one is in a read state and the other is in a write state, thereby performing read / write control.

In the delay circuit, the above delay units DU1, ~ DUn
Is, for example, from 1ch to 24c depending on the channel position of the transducer 3.
Up to h, 25ch to 48ch, 49ch to 72ch, 73ch to nch are grouped as a set, and the adder circuit A
Send to DER and add.

That is, taking 1 to 24 ch as an example, the delayed output data of 1 ch is sent to 2 ch and given to the adder circuit ADD of the delay unit DU2, and the output data of 2 ch is 3 ch.
To the adder circuit ADD of the delay unit DU2, and the phasing addition is performed by sequentially adding, and so on. It is divided into four groups in order to perform this processing at high speed and to minimize the data capacity handled by the hardware.
Therefore, if such a problem can be ignored, 1ch to n
It is also possible to adopt a configuration in which all channels up to ch are sequentially sent to the delay unit of the next channel and added, in which case the adder circuit ADER can be omitted.

In the delay circuit having such a configuration, a signal received for each channel is sent to an AD conversion circuit corresponding to each channel, AD-converted, and converted into digital data. Then, it is input to each corresponding delay unit.

Taking the delay unit DU1 as an example, this digital data enters the buffer register BR, is temporarily held there, and then is stored in the first and second static memories.
Given to SRAMA and SRAMB. The first and second static memories SRAMA and SRAMB are read / write controlled by a read / write signal provided by the control means (not shown) so that when one is in a read state, the other is in a write state. It Now, assuming that the first static memory SRAMA is in the write state and the second static memory SRAMB is in the read state, the second static memory SRAMB has no data in the initial state, and there is no external data. A second static memory which receives a read address from the read / write address generation circuit RAGB, which operates in synchronization with a given clock signal and repeats the operation of sequentially updating the address for the number of times corresponding to the set delay time. No data is output from the memory SRAMB.

On the other hand, the first stack memory SRAMA which has received the write address from the read / write address generation circuit RAGA which repeats the operation of sequentially updating the address in the same manner, sequentially transfers the digital signals to the addresses which change in synchronization with the clock signal.・ Data is written. This state is shown in the third.

In the figure, the clock signal is shown in (a), the input digital data is shown in (b), the address of the first static memory SRAMA is shown in (c), and the read / write state of the first stack memory SRAMA (R / W) to (d), the input data (I / O data) of the first static memory SRAMA to (e),
The address of the static memory SRAMB shown in FIG.
The read / write state (R / W) of the static memory SRAMB of FIG. 2 to (g), the input data (I / O data) of the static memory SRAMB of FIG. 2 to (h), and The output data of the delay circuit, that is, the output of the register REG is shown in (i).

As in the input data (b) from the AD converter, it is assumed that they are sequentially transmitted in synchronization with the clock signal.
If the delay time to be obtained is 4 clocks,
The data from to are sequentially stored in the SRAMA from addresses "3" to "0", and then the read mode is set to sequentially read the stored data.

Then, when SRAMA is in the read state, SRAMB is in the write state.
It is stored in order from the address "3" of SRAMB to "0". Then, the SRAMB is placed in the read mode, and the stored data to are sequentially read and output. When the SRAMB is in the read state, the SRAMA is in the write state.
The addresses of A are stored in order from "3" to "0".

By sequentially performing read / write in this manner, a delay corresponding to the number of clocks in the write mode can be obtained.
As shown in FIG. 3 (i), the data string is output from the register REG with a delay of 4 clocks.

To perform dynamic focus, do the following. That is, if it is desired to lengthen the delay time by 2 clocks, the control means gives a command to the read / write address generation circuits RAGA and RAGB at the read / write switching timing at the time of changing. As a result, the read / write address generation circuits RAGA, RAGB are changed to take an extra address for two. For example, if the SRAMA is in the read state, the storage amount is 4 data, so the addresses are from "3" to "0" in sequence, and there is no more. Therefore, at this time point, when the address "0" is reached, the addresses "1" and "0" are repeated for two clocks so as to reproduce. As a result, the read data can take 6 clocks from "5" to "0" for the SRAMB which is overlapped but is in the write state, by the amount corresponding to the repetition of the addresses "1" and "0". become. Then, the SRAMB in the written state sequentially stores 6 pieces of data from "5" to "0". After that, SRAMA can also obtain a delay of 6 clocks by storing data from addresses "5" to "0" in order in the next write mode.

In this way, the RAMs of two systems are alternately used for read / write, and the read / write mode is switched every time a predetermined number of addresses are updated, and the delay of data transmission is performed by utilizing this read / write timing. By doing so, it becomes possible to arbitrarily obtain the delay time depending on the way of switching the read / write of the RAM, that is, the memory and the method of updating the read / write address.

In this way, the data read with a delay is SRAMA,
If the output data of SRAMB and buffer register BR is sent to the adder circuit ADD via the multiplexer register MR that selects the output data, and if the delay data from another delay unit is input here, both are added and combined. After that, it is sent to the register REG and output from the delay unit DU1 as output data.

An example of an ultrasonic diagnostic apparatus using such a delay circuit is shown in FIG. In the figure, 21 is an ultrasonic probe, which is an array type. 22 is a transmission delay circuit, LC delay
It uses the line. Reference numeral 23 is a delay time setting device for setting a desired delay time. 24 is a reference signal generator that generates a reference signal (clock signal), and 25
Is a scan control circuit that sets a necessary transmission / reception delay time for each channel in order to direct an ultrasonic beam in a necessary scanning direction corresponding to ultrasonic scanning.

26 is a controller that controls the entire control, and 27 is an ultrasonic probe.
A preamplifier circuit 21 that preamplifies the output of each ultrasonic transducer for each channel, and 28 is a reception delay circuit that delays the preamplified output of each channel for each channel.
It has the structure shown in the figure. 29 is a detection circuit that detects the delayed output for each channel, 30 is a signal processing circuit that performs logarithmic conversion processing or filtering processing on this detection output, 31 is the ultrasonic scanning of the frame memory for the signal processed output. It is a digital scan converter (DSC) that converts ultrasonic scanning into television scanning by writing in corresponding positions, reading this in correspondence with television scanning, and giving it as a video output to a display device.

In such a configuration, the reference signal (clock signal) is generated from the reference signal generator 24, and the reception delay circuit 27, the delay time setting device 23, and the transmission delay circuit 22 operate in synchronization with this. Now, assuming that the position is set to perform the dynamic focus, under the control of the controller 26,
The scan control circuit 25 controls the delay time setter 23 to perform sector scan scanning with a preset focus up to that position, which causes the delay time setter 23 to generate ultrasonic waves in synchronization with the reference signal. A transmission delay circuit (22) is controlled so that the transmission drive pulse is delayed by a delay time for each channel corresponding to the scanning direction. As a result, the drive pulse is delayed by the delay time for each channel corresponding to the scanning direction, is given to the corresponding transducer of the ultrasonic probe 21, and the ultrasonic beam is transmitted.

The received wave is amplified by the preamplifier circuit 27, and then a delay time corresponding to the delay time at the time of transmission is given by the reception delay circuit 28 whose delay time is set by the delay time setter 23, and phasing addition is performed. It Then, after being detected by the detection circuit and processed by the signal processing circuit 30, the DSC31
Written in. When the received signal reaches the dynamic focus position, the scan control circuit 25
The delay time setting unit 23 is controlled to give a reception delay time corresponding to the focus position. As a result, the setting of the reception delay circuit 28 is changed to the required delay time. The reception wave amplified by the preamplification circuit 27 is delayed by the reception delay circuit 28 whose channel-specific delay time is set by the delay time setting unit 23 with the changed delay time, and phasing addition is performed. Then, it is detected by the detection circuit 29, processed by the signal processing circuit 30, and then written in the DSC 31. When the next ultrasonic wave is transmitted, the original delay time is restored and the dynamic
At the focus position, the delay time is changed as described above. The image data stored in the DSC 31 is read out in accordance with the television scanning and displayed on the display device 32. As a result, a dynamically focused B-mode image is displayed.

In this way, this apparatus uses two systems of RAM for each channel as the reception delay circuit 28, and alternately uses the two systems of RAM for read / write to update the read / write mode by a predetermined number of addresses according to the delay time. By switching each time, the read / write timing is used to obtain the delay of the data transmission, so that the read / write switching of the RAM, that is, the memory, and the update of the read / write address can be performed. The delay time can be arbitrarily obtained.

Therefore, since the delay time is adjusted by accumulating and sending out the data, there is no switching by the switch unlike the LC delay line, and there is no fear of noise mixing due to the switching. Further, since the delay is due to the control of writing and reading under the control synchronized with the clock (reference signal), it is possible to obtain a desired delay time with high accuracy and the reliability is improved. Further, since the digital circuit is used, the delay circuit can be constructed at low cost.

Further, the present apparatus digitizes the analog reception signal amplified by the preamplifier circuit 27, gives a predetermined delay to the digitized reception signal for each channel, and then delays an arbitrary delay between adjacent channels. Phased addition is performed by adding the received signals that have been given and repeating the operation of adding the addition result and the received signals output from other channels. Therefore, since the number of data stored in the delay unit can be minimized, the reception delay circuit 28 can be made smaller than the conventional one, and the same delay unit can be connected, so that the constituent elements including the bus line can be formed. The number can be reduced, and the circuit configuration can be simplified.

The present invention is not limited to the embodiments described above and shown in the drawings, but can be appropriately modified and implemented within the scope of the invention.

〔The invention's effect〕

As described above in detail, according to the present invention, there is no fear of noise mixing, and it becomes possible to obtain a desired delay time with high accuracy, the reliability is high, and the ultrasonic wave having a simple delay circuit configuration is used. A diagnostic device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a delay circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of its delay unit, and FIG. 3 is a timing chart diagram for explaining the operation of the delay circuit. FIG. 5 is a block diagram showing the configuration of an ultrasonic diagnostic apparatus using the delay circuit of the present invention, and FIG.
It is a block diagram which shows the structure of an LC delay line. AD1, ... ADn ... AD conversion circuit, DU1, ... DUn ... delay unit, ADER ... adding circuit ADER, AD1, ... ADn ... AD conversion circuit, BR ... buffer register, SRAMA, SRAMB .... 1st and 2nd static memory, RAGA, RAGB ... Read / write address generation circuit, MR ... Multiplexer register, ADD ... Addition circuit, register ... REG, 21 ...
... ultrasonic probe, 22 ... transmission delay circuit, 23 ... delay time setting device, 24 ... reference signal generator, 25 ... scan control circuit, 26 ... controller, 27 is an ultrasonic probe 21 ... Preamplifier circuit, 28 ... Reception delay circuit, 29 ... Detection circuit, 30 ... Signal processing circuit, 31 ... Digital scan converter (DSC).

Claims (1)

[Claims] 1. An ultrasonic wave is transmitted / received to / from a subject from a plurality of transducers arranged in an array, and a delay circuit delays and adjusts the received signals from the respective transducers. In the ultrasonic diagnostic apparatus that performs phase addition, the delay circuit is provided corresponding to the transducer, AD conversion means for digitizing an analog reception signal for each channel of the transducer, and the AD conversion means Correspondingly provided, it has at least two systems of memory for temporarily storing digitized received signals, and alternately switches read / write of these two systems of memory at a timing according to the delay time of each channel. A delay unit for giving a desired delay to the digitized received signal by dividing the plurality of transducers into a plurality of blocks, and the delay unit for each block. The ultrasonic diagnostic apparatus is characterized in that the output signals from the channels are sequentially added between adjacent channels, and the addition result of each block is added to perform phasing addition of the received signals of all channels.