JPH0772737B2 - Period detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention detects a period of a pulse of a mechanical device such as a belt conveyor by detecting the period of a pulse having a period corresponding to its rotation speed. The present invention relates to a circuit, and more particularly, to a circuit capable of satisfactorily detecting an ultra-low speed and even a stop.

[Background Art and its Problems] When detecting the rotation speed, generally, the pulse cycle from a pulse generator that generates a pulse having a cycle corresponding to the rotation speed is converted into, for example, a voltage. The speedometer indicator is used to read the instruction.

However, in this case, when the rotation speed becomes low, the period of the pulse from the pulse generator becomes long, so that the pointer of the indicator of the tachometer vibrates and it becomes difficult to read the instruction accurately. To avoid this drawback, a large-capacity capacitor is connected, but doing so has the drawback of reducing the response speed of the tachometer.

Therefore, the applicant previously proposed a device that does not cause such a defect.

FIG. 1 shows an example thereof. In the figure,
(1) is an input terminal, and a pulse PI having a period corresponding to the rotation speed from the pulse generator is supplied to the monostable multivibrator (2) through this input terminal (1) and is synchronized with the pulse PI. A pulse PS (Fig. 2A) is obtained. This pulse PS is supplied to the monostable multivibrator (3), and a pulse PR (B in the figure) in which the pulse PS is slightly delayed is obtained from this, and this pulse PR is a 1 / T (T is a period) function generation. It is supplied to the circuit (4) as its reset pulse.
From this 1 / T function generation circuit (4), the voltage is set to a predetermined voltage E _M when reset by the pulse PR, and from this time the input pulse is input from the voltage E _M until the next reset pulse arrives.
A downward sawtooth wave output SA (FIG. 6C) is obtained which is hyperbolicly lowered according to the period T of PI. Therefore, the output SA has a voltage corresponding to the cycle of the input pulse PI immediately before being reset by the pulse PR, that is, the crest value of the downward saw tooth wave in the figure.

The output SA of the function generating circuit (4) is supplied to the sampling gate circuit (6). Then, the pulse PS from the monostable multivibrator (2) is supplied to the sampling gate circuit (6) through the OR gate (5), and the output SA is sampled by the pulse PS through the gate circuit (6). The sampling voltage is stored in the capacitor (7). Since the pulse PS is the pulse immediately before the reset pulse PR, what is sampled by the gate circuit (6) is the downward peak value voltage of the sawtooth wave voltage SA corresponding to the cycle of the input pulse PI as described above. , Which will be stored in the capacitor (7). The voltage SH ₀ (solid line in FIG. 7D) stored in the capacitor (7) is supplied to the indicating instrument (9) through the buffer amplifier (8). Therefore, the pointer of the indicating instrument (9) corresponds to the voltage SH ₀ .

The output of the buffer amplifier (8) is also output to the comparison circuit (10).
On the other hand, the output of the function generation circuit (4) is supplied with SA to this comparison circuit (10), and the comparison output SC becomes high level when the output SA becomes lower than the voltage SH _0. (Fig. 2E) is obtained, and this is supplied to the sampling gate circuit (6) through the OR gate (5),
The high level engine of the output SC, this gate circuit (6) is conducted. As a result, the voltage SH ₀ of the capacitor (7) becomes
The conduction of the gate circuit (6) equalizes the output SA of the function generating circuit (4) during the high level period of the comparison output SC, and this voltage SH ₀ is output SA as shown by the solid line in FIG. 2D.
Changes in a hyperbolic manner. Output SC of comparison circuit (10)
Becomes high level when the speed decreases and the period of the input pulse PI becomes longer. Therefore, according to the circuit of FIG. 1, the pointer of the indicating instrument (9) does not vibrate even when the speed decreases and the cycle of the input pulse PI becomes long, and the pointer decreases in speed. Then, the shake changes sequentially in accordance with, and it becomes possible to satisfactorily detect even an ultra-low speed. By the way, when the above cycle detection circuit is also used as the stop detection circuit, there are the following drawbacks.

That is, in the circuit of FIG. 1, as the speed decreases and the period T increases, the output SA decreases in a hyperbolic manner, and the voltage SH ₀ obtained at the capacitor (7) also corresponds to this.

However, when the rotation of the circuit in Fig. 1 suddenly stops and the input pulse PI does not arrive, the voltage SH
₀ follows a hyperbolic drop of the output SA of the function generator (4). Since this descending hyperbola practically has an asymptotic image output, even if the rotation or the like suddenly stops, the deflection of the pointer does not become zero and it is inconvenient to detect the stop.

[Object of the Invention]

In view of the above points, the present invention is to provide a cycle detection circuit that can perform particularly good stop detection.

[Outline of Invention]

Usually, a mechanical device such as a conveyor, which is a test object at a speed such as a rotation speed, does not change its speed rapidly in use, and operates a continuously variable transmission to gradually change the speed. The input pulse cycle rarely exceeds twice, and the input pulse cycle changes more than three times only when the vehicle suddenly stops due to some accident.

Therefore, in the present invention, means for setting a value corresponding to a cycle in which the cycle of the input pulse suddenly changes and becomes several times longer is provided, and the output of this setting means is synchronized with the input pulse PI Is stored in the storage means at the time of the pulse of, and changes according to the stored value of this storage means and the cycle of the input pulse, and when the cycle of the input pulse becomes longer, it follows the lengthened cycle change. Compare with the cycle detection output,
A stop detection signal is obtained as the comparison output.

〔Example〕

FIG. 3 shows an example of the present invention, which is a case where a stop detection circuit section is added to the cycle detection circuit of FIG.

That is, in this example, the output of the buffer amplifier (8) is divided by the resistors (11) and (12). For example, the resistor (12) is adjusted so that these resistors (11) and (12)
The voltage obtained at the connection point is set to 1/3 to 1/5 of the output voltage value of the buffer amplifier (8). That is, the cycle of the input pulse PI changes rapidly and the previous stable state of 3-5
It will be set equal when doubled. This voltage value is supplied to the sampling gate circuit (13), is sampled by the pulse PS in the gate circuit (13), and the sampled value is stored in the capacitor (14). Memory output voltage SHs of this capacitor (14)
The alternate long and short dash line in FIG. 2D is supplied to the comparison circuit (16) through the buffer amplifier (15). The output of the buffer amplifier (8) is also supplied to the comparison circuit (16).
Therefore, this comparison circuit (16) outputs a comparison output that becomes high level when the storage output voltage of the capacitor (7) becomes lower than the storage output voltage SHs of the capacitor (14).
STP (Fig. 2F) is obtained. In other words, this comparison output STP
Becomes a high level when the input pulse PI has a suddenly long cycle in which the subject can be regarded as a sudden stop, and this is a stop detection signal which cannot be recovered.

In this example, when the stop detection is made, the pointer of the indicating instrument is set to indicate zero, so that the output of the buffer amplifier (8) is passed through the switch circuit (17) to the buffer amplifier (1
The output terminal (19) is supplied to the buffer amplifier (18), and the signal obtained at the output terminal (19) is supplied to the indicating instrument. Then, the output STP of the comparison circuit (16) causes the switch circuit (1
7) is controlled so that the switch circuit (17) is turned off when the stop STP is detected and the output STP becomes high level.

If the stop detection output STP goes high and the stop speed is detected and then the speed of the subject rises and returns to the original speed, the input with a short cycle as shown by the dotted line in FIG. As the pulse arrives, as is clear from Fig. 2, the voltage of the capacitor (7) immediately rises, and the output ST
P goes down to a low level, the switch circuit (17) is turned on, and then the cycle detection is performed in exactly the same manner as in the steady state.

The signal obtained at the output terminal (19) is not limited to being supplied to the indicating instrument, and may be one of the inputs of a computer that controls the operation of the mechanical device that is the subject, for example.

Although the example of FIG. 3 is an example configured in analog, the present invention can also be configured in digital.

That is, the present invention can also perform the above operations by software processing using a microcomputer, for example. For ease of explanation, an example of this digital configuration will be described with reference to the hardware and its flowchart of FIG.

In FIG. 4, (21) is a counter as a function generating circuit for period detection, and a clock pulse CP having a frequency sufficiently higher than the input pulse PI is supplied to the clock terminal through the terminal (22). Then, as described above, the input pulse PI
The pulse PR of the same cycle is supplied to the reset terminal of the counter (21) through the terminal (23). Therefore, the count value of the counter (21) corresponds to the length of the cycle of the pulse PR. The count value output CNT of the counter (21) is supplied to the memory (24), and the pulse PS immediately before the pulse PR is supplied from the terminal (25) to the memory (24) through the OR gate (26). The count value at the time of this pulse PS, and therefore immediately before being reset by the pulse PR, is stored in this memory (24). The stored value M ₁ of this memory (24) is the comparison circuit (2
7) is supplied to the output of counter (21) count value CNT
This comparison circuit when compared with M ₁ ≤ CNT (27)
The AND gate (28) is opened by the output of the AND gate, the clock pulse CP is obtained through this AND gate (28), and this is supplied to the memory (24) through the OR gate (26), and the pulse CP sequentially causes the memory (24). Is rewritten to the count value CNT.

The stored value of the memory (24) thus obtained corresponds to the output value of the capacitor (7) in FIGS. 1 and 3.

The stored value of the memory (24) is supplied to the multiplication circuit (29), its value is tripled, and the tripled value is stored in the memory (30) by the pulse PS. Therefore, the stored value M ₂ of the memory (30) corresponds to the value when the cycle of the input pulse suddenly becomes three times longer. Comparator circuit with the stored value M ₁ of the memory (30) storing values M ₂ and the memory (24) (31)
When the comparison is made in step S1 and M ₂ <M ₁ (= CNT), a stop detection signal is obtained from the comparison circuit (31).

FIG. 5 shows that the cycle of the input pulse becomes longer than the cycle before that, the stored value M ₁ of the memory (24) follows the count value CNT of the counter (24), and the cycle is tripled or longer. 7 is a flowchart showing that stop detection is performed when

〔The invention's effect〕

As described above, according to the present invention, it is possible to consider that a mechanical device, which is an object of speed detection, generally does not show a rapid change in speed in a normal use state, and a rapid decrease in speed can be regarded as a stop. Then, when the period of the pulse to be measured, which is the input pulse, suddenly becomes several times longer, it is determined that the stop detection has occurred, so that the drawbacks of the prior art are eliminated.

Moreover, in the present invention, the circuit for this stop detection has the second storage means for storing the value obtained by multiplying the output of the existing first storage means by the set value, and the storage value of the first storage means. There is an advantage that a simple configuration is sufficient, in which only a comparison unit that obtains a stop detection output when the value stored in the second storage unit is larger than the stored value is provided.

[Brief description of drawings]

FIG. 1 is a system diagram of an example of a conventional cycle detection circuit, FIG. 2 is a waveform diagram for explaining the example and the example of the invention, and FIG. 3 is a system diagram of the example of the circuit of the invention. Is a system diagram of another example of the present invention, and FIG. 5 is a flowchart for obtaining the operation of the main part thereof. (1) is an input terminal for the pulse to be measured, (2) is a monostable multivibrator that obtains the first pulse, (3) is a monostable multivibrator that obtains the second pulse, and (4) is 1 / T function generation Circuits, (6) and (13) are sampling gate circuits, (7) and (14) are capacitors as storage means, and (10) and (16) are comparison circuits.

Claims (1)

[Claims] 1. A cycle detecting circuit for receiving a pulse to be measured and outputting a value according to the cycle, wherein a first storage means for storing a value according to the cycle, and a first storage means for storing the value according to the cycle. Second storage means for storing a value obtained by multiplying the stored content immediately before by a set value, and a stop detection output is obtained when the storage value of the first storage means becomes larger than the storage value of the second storage means. A cycle detection circuit provided with a comparison means.