JPH0772780B2 - Thin film transistor array substrate - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for forming a thin film transistor array substrate, and more particularly to a wiring configuration at a substrate cut portion.

[Conventional technology]

Conventionally, in a thin film transistor array substrate for a liquid crystal display, as shown in FIGS. 5 and 6, the wiring of the terminal part is a shunt pattern 2 outside the element region for both upper layer wiring 1 and lower layer wiring 4 for the purpose of electrostatic protection measures for internal elements. They were extended and connected to each other through the through holes 3, and the metal film was formed also on the substrate cutting portion.

[Problems to be Solved by the Invention]

In the above-mentioned conventional thin film transistor array substrate, since the terminal portion is directly extended to the outer pattern,
When the element portion is cut, the upper wiring 1 is cut, so that conductive dust is generated. This dust is mixed in the element portion to cause a short circuit defect, which causes a reduction in the yield of the thin film transistor array.

[Means for Solving the Problems]

According to the present invention, a thin film transistor array substrate is obtained in which the upper layer wiring on the cut portion is removed in the terminal portion, the upper and lower layer wirings are further through-hole wiring, and the internal element lead-out wiring and the outer shunt pattern are electrically connected. .

According to the thin film transistor array substrate of the present invention, conductive dust is suppressed by removing the upper layer wiring on the terminal portion and the cut portion, and the outer shunt pattern is formed by performing the through-hole wiring of the upper and lower layer wirings. By electrically connecting the lead wire of the internal element and the lead wire of the internal element, there is an advantage that the measures against static electricity of the internal element can be taken.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a first view.
It is an AA 'sectional view of a figure. The lower layer wiring 4 is formed of Cr1400Å on the glass substrate 6 and the interlayer insulation film SiOx1000Å, SiNx4000
Å is formed, and then through holes 3 are formed in the insulating film on the lower layer wiring by etching, and then the upper layer wiring is formed by Cr2000Å to connect with the lower layer wiring and the internal element lead-out wiring without making the upper layer wiring on the cutting line. And shunt pattern can be connected.

Since there is no Cr on the cutting line in the terminal portion formed in this way, the generation of conductive dust due to cutting is small, and therefore short-circuit defects of internal elements due to metal dust can be reduced.

FIG. 3 is a plan view of another embodiment of the present invention, and FIG. 4 is a sectional view taken along the line AA 'in FIG.

The lower layer wiring 4 is formed of Cr on the glass substrate, and the insulating film SiOxSi is formed.
After forming the through hole 3 in Nx, the upper layer wiring is formed of Cr. After that, a second insulating film is formed of SiOx or SiNx only on the cut portion.

In this embodiment, since the insulating film is further formed on the upper layer wiring, there is a problem that the number of steps is increased and a protrusion is formed on the terminal portion, which deteriorates the connection to the terminal in a later step. Since there is no disconnection on the way, there is an advantage that the connection to the shunt pattern can be reliably made.

〔The invention's effect〕

As described above, according to the present invention, by removing the upper layer wiring on the cut portion, the conductive dust can be significantly reduced, and the short-circuit defect of the internal element can be reduced. Further, the upper and lower layer wirings are through-hole wirings, and by connecting the outer shunt pattern and the internal element lead-out line, there is an effect that it is possible to take measures against static electricity of the internal element.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention, and FIG.
FIG. 3 is a sectional view taken along the line AA ′ in FIG. 3, FIG. 3 is a plan view showing another embodiment of the present invention, and FIG. 4 is a sectional view taken along the line AA ′ in FIG. FIG. 5 is a plan view showing an example of a conventional terminal portion, and FIG. 6 is a sectional view taken along the line AA 'in FIG. 1 …… Drawer upper layer wiring, 2 …… Shunt pattern, 3
...... Through hole, 4 ... Lower layer wiring, 5 ... Interlayer insulating film, 6 ... Glass substrate, 7 ... Second insulating film.

Claims (2)

[Claims] 1. A thin film transistor array substrate having a terminal shunt pattern, wherein upper layer wiring on a cut portion of upper and lower layer wirings formed by sandwiching an interlayer insulating film at a terminal portion is removed, and further upper and lower layer wirings are through holes. A thin film transistor array substrate, characterized in that the internal element lead-out wiring and the outer shunt pattern are electrically connected to each other by being connected with each other. 2. A thin film transistor array substrate having a terminal shunt pattern, wherein a second insulating film is provided on an upper layer wiring at a cut portion of upper and lower layer wirings sandwiching the first insulating film of the terminal portion, Further, the thin film transistor array substrate is characterized in that the upper element wiring and the outer shunt pattern are electrically connected by connecting the upper and lower wirings with through holes.