JPH0772876B2 - Memory control circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a memory control circuit for operating a memory mounted in a digital signal processing device (DSP) or the like.

(B) Conventional Technology Conventionally, a DSP is equipped with a memory such as a static RAM in which data can be written and read freely, and input digital data is temporarily stored in the memory. The digital data stored in such a memory is read out and used for a predetermined calculation, and then stored again in the memory.
At this time, new digital data is sequentially input to the memory, and the digital data read from a certain address is written to the address next to that address. Specifically, "1" is added to the address data when the digital data is read, and the digital data is used to specify the write address.

FIG. 5 is a block diagram of a memory control circuit that operates the memory as described above, and FIG. 6 is an operation timing chart thereof.

The memory (2) connected to the data bus (1) is supplied with N-bit address data ADR that changes in a predetermined cycle, and addresses of the memory (2) are sequentially designated according to the address data ADR. Further, the memory (2) is supplied with a read enable signal RE for permitting reading of data and a write enable signal WE for permitting writing of data, and reads out data from an address designated according to address data ADR and Data writing is controlled.

On the other hand, the data bus (1) is connected to the arithmetic circuit (3) having a data hold function, transmits the data read from the memory (2) to the arithmetic circuit (3), and the arithmetic circuit (3) to the memory (2). ) Return the data to.

The address data ADR changes by one address at a constant cycle T and sequentially designates the addresses of the memory (2). Then, the read enable signal RE synchronized with the designation of the address
According to the write enable signal WE, data is read from the predetermined address in the period T ₁ and transmitted to the arithmetic circuit (3), and data is returned from the arithmetic circuit (3) in the next period T ₂ to read the data. Data is written to the address next to the address. That is, as shown in FIG. 6, after the data is read from a certain address of the memory (2), the address data ADR is changed by one address to designate the next address, and the arithmetic circuit (3) is designated at that address. It is configured so that the data held at is written. These read enable signal RE and write enable signal
WE is created from a common basic clock, and by changing the address data ADR according to the basic clock, data reading and writing can be synchronized with address specification.

(C) Problems to be Solved by the Invention However, in the memory control circuit as described above,
In order to move the data stored in one address of the memory (2) to the next address, two steps of reading the data and writing the data are required, which slows down the operation speed and increases the speed. There arises a problem that it is not suitable for signal processing.

Further, by using a memory having a special structure that allows the read data to be written to the next address as it is, the data can be transferred in one step, but the circuit becomes complicated. The cost increases with an increase in the scale, and further, considering the signal delay in a complicated circuit, the operation speed cannot be sufficiently increased to prevent malfunction.

Therefore, an object of the present invention is to provide a memory control circuit that can move data stored at a certain address of a memory to a different address in one step without using a specially configured memory or a complicated circuit. To do.

(D) Means for Solving the Problems The present invention has been made to solve the above problems, and is characterized in that reading and writing of data and designation of an address are independent, and a common data bus is provided for each. Connected first and second memories, means for simultaneously designating addresses of the first and second memories according to address data excluding the least significant bit, and the odd address period according to the least significant bit address data Means for reading data from the first memo and reading data from the second memory in the even-numbered address period and data read in the odd-numbered address period are written in the second memory during the same period and read in the even-numbered address period. Means for writing data in the first memory in the same period, and the address excluding the least significant bit in the odd address period A certain data is added to the data, and the address of the second memory is designated according to the added address data.

(E) Operation According to the present invention, the data read from the first memory is output to the data bus and written to the second memory from the data bus in the odd address period, and the data is written in the second memory in the even address period. The data read from the second memory is output to the data bus and is written to the first memory from the data bus. Then, the address of the second memory is shifted by one address from the first memory during the odd-numbered address period, so that reading and writing of data are repeated between the first memory and the second memory. Data is transferred one address at a time.

(F) Embodiment An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the memory control circuit of the present invention, and FIG. 2 is an operation timing chart thereof.

The ODD memory (11) and the EVEN memory (12) have the same capacity and are connected to the common data bus (10).
The ODD memory (11) is supplied with N-bit address data A _{1 to} A _N excluding the least significant bit, and the EVEN memory (12)
Are supplied with the same address data A _{1 to} A _N via an adder circuit (13). The adder circuit (13) is configured to add "1" to the address data A _{1 to} A _N in the odd address period ODD and output the address data A _{1 to} A _N as it is in the even address period EVEN. There is. Odd address period OD
The determination of the D and the even address period EVEN, address data A ₀ of the least significant bits are used, the address data A ₀
Is "1", it is determined to be an odd address period ODD, and if "0" is to be an even address period EVEN. Further, the address data A ₀ is used as a read enable signal RE for the respective memories (11) (12), the address data A ₀ is directly supplied to the ODD memory (11), and the inverter data is supplied to the EVEN memory (12). Address data A ₀ via (14)
Is supplied. Further, the ODD memory (11) and the EVEN memory (12) are respectively supplied with a write enable signal WE ₁ for permitting writing in the even address period EVEN and a write enable signal WE ₂ for permitting writing in the odd address ODD. Therefore, during the odd address period ODD, data is read from the ODD memory (11) and written in the EVEN memory (12). At this time, EVEN memory (12)
The address of (1) precedes the address of the ODD memory (11) by one address due to the action of the adder circuit (13). On the other hand, in the even-numbered address period EVEN, data is read from the EVEN memory (12) and written in the ODD memory (11). At this time, the addresses of both memories (11) and (12) match, and the addresses are written to the same addresses as the read addresses. For example, in the memory shown in FIG. 3, the data read from the address O ₁₁ of the ODD memory (11) is written to the address E ₂₁ of the EVEN memory (12) and then the data of the EVEN memory (12). It is read from address E ₂₁ and written to address O ₂₁ of the ODD memory (11). After that, each address O ₂₁ , E ₃₁ ,
The data is sequentially transferred to O ₃₁ , E ₄₁ , O ₄₁ ....

FIG. 4 is a circuit diagram showing an example of the adder circuit (13).

This adder circuit (13) has N XOR gates (XOR ₁ ) to (XOR ₁ ).
_N ) and N-1 AND gates (AND ₁ ) to (AND _N-1 ), and N is input to one input of each XOR gate (XOR ₁ ) to (XOR _N ).
Bit address data A _{1 to} A _N are supplied, and outputs A ′ _{1 to} A ′ _N are obtained from the outputs of the XOR gates (XOR ₁ ) to (XOR _N ). Bottom XOR gate (XO
Address data A _{0 of the} least significant bit is input to the other input of R ₁ ).
And the AND of both inputs of this XOR gate (XOR ₁ ) is fed from the AND gate (AND ₁ ) to the other input of the XOR gate (XOR ₂ ) to form a carry signal and in the same way XOR. AND of gate (XOR ₂ ) (XOR ₃ ) ... AND gate (A
ND ₂ ) (AND ₃ ) ... 1 digit higher XOR gate (XOR ₃ ) (XO
R ₄ ) ... Supplied as a carry signal to the other input. Therefore, when the address data A ₀ is “1” (odd address period ODD), “1” is added to the address data A _{1 to} A _N , and its outputs A ′ _{1 to} A ′ _N are stored in the EVEN memory (12 ), And when the address data A ₀ is “0” (even address period EVEN), the address data A _{1 to} A _N are given to the EVEN memory (12) as they are.

According to the above configuration, ODD memory (11) and EVEN memory (1
Data reading and writing are simultaneously and alternately performed between and 2), and the data is sequentially transferred by one address for each reading and writing, that is, for each address period.

In addition, in the present embodiment, even-numbered addresses are used during the odd address period ODD.
Although the case where the memory address is preceded by one address has been illustrated, the address of the ODD memory may be preceded by one address during the even address period EVEN. In this case, a subtraction circuit for subtracting "1" from the address data A _{1 to} A _N is provided in place of the addition circuit (13), and the even address period EV
It may be configured so that “1” is subtracted from EN from the address data A _{1 to} A _N and is given to the EVEN memory (12).

(G) Effect of the Invention According to the present invention, it becomes possible to move the data stored at a certain address of the memory to a different address in one step without significantly increasing the circuit scale, and the operating speed can be increased. Can be improved. Further, the memory itself does not require a special configuration, and it is sufficient if at least two memories having a capacity half that of the conventional memory are used, and the cost does not increase.

Therefore, an inexpensive memory control circuit suitable for high-speed signal processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory control circuit of the present invention, FIG. 2 is an operation timing of FIG. 1, FIG. 3 is a schematic diagram of a memory, FIG. 4 is a circuit diagram of an adder circuit, and FIG. 5 is a conventional memory. FIG. 6 is a block diagram of the control circuit, and FIG. 6 is an operation timing chart of FIG. (1) …… Data bus, (2) …… Memory, (10) ……
Data bus, (11) …… ODD memory, (12) …… EVEN memory, (13) …… Adding circuit, (14) …… Inverter,
(XOR ₁ ) to (XOR _N ) …… XOR gate, (AND ₁ ) to (AND
_N-1 ) …… AND gate.

Claims (2)

[Claims] 1. A first and a second memory connected independently to a common data bus for reading and writing data and specifying an address, and the least significant bit of address data that changes in a predetermined order. Means for simultaneously designating the addresses of the first and second memories according to the higher-order bit data excluding, and the least significant bit of the address data,
The data is read from the first memory and written to the second memory during the odd address period that forms the first value, and the data is read from the second memory during the even address period that forms the second value. 1 means for writing to the memory, adding constant data to the upper bit data during the odd address period, and designating an address of the second memory according to the upper bit data to which the constant data is added. Memory control circuit characterized by. 2. A first and a second memory connected independently to a common data bus for reading and writing data and specifying an address, and the least significant bit of address data that changes in a predetermined order. Means for simultaneously designating the addresses of the first and second memories according to the higher-order bit data excluding, and the least significant bit of the address data,
The data is read from the first memory and written to the second memory during the odd address period that forms the first value, and the data is read from the second memory during the even address period that forms the second value. 1 means for writing to the memory, constant data is subtracted from the upper bit data in the even-numbered address period, and the address of the second memory is designated according to the upper bit data from which the constant data is subtracted. Memory control circuit characterized by.