JPH0772983B2 - Digital signal regenerator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing apparatus applied to reproduce a digital signal such as an audio PCM signal from a magnetic tape by a rotary head.

[Outline of Invention]

According to the present invention, a preamble section for pulling in a PLL is added before a data section of a predetermined length, and the data section is inserted in each block in a digital signal reproducing apparatus in which each block is encoded by an error detection code. Prevents erroneous operation of error detection by forming a start signal that starts the decoding operation of the error detection signal by detecting the marker and invalidating the signal processing by the start signal generated at the timing before the detection of the preamble section It is something that is done.

[Conventional technology]

A VTR (so-called 8 mm VTR) having a magnetic tape width of 8 mm and a small tape cassette is standardized for recording / reproducing a digital audio signal (called a PCM signal). As the error correction code for the 8 mm VTR PCM signal, the one described in Japanese Patent Laid-Open No. 58-198935 has been proposed. In this error correction code, the PCM signal corresponding to one field of the video signal is coded with two series by the cross interleave method,
A CRC code (one of error detection codes using a cyclic code) is encoded for each block consisting of 10-word data and 1-word address in the order of recorded data. A marker having a specific bit pattern is added to the beginning of this block for synchronization. In the playback circuit,
By detecting this marker, the CRC code calculator starts its operation, and the presence or absence of an error is detected for each block.

In the 8mm VTR, the standard method is to record the FM-modulated audio signal on the inclined track together with the recording video signal. Also, at the end of the truck as an option
A dedicated area for PCM signals is provided. Therefore, the PCM signal is intermittently reproduced so as to be included in the first part of one field. At the start of the dedicated area of the PCM signal, 3H (H: 1
A preamble section having a length of (horizontal section) is set. In the 8mm VTR, bi-phase modulation is used as the modulation method, so all "1" data is, for example, 5.8MHz.
The pulse signal has a frequency of.

Each field PLL performs a pull-in operation so that the PLL is locked to the reproduction signal in the preamble section, and a clock for extracting reproduction data is generated by the PLL. Digital data reproduced when the PLL is pulled in is completely unreliable and can be processed as reproduced data only after the PLL is locked.

[Problems to be solved by the invention]

In the conventional 8 mm VTR, since completely random data is reproduced when the reproduction PLL is pulled in, part of the data in the preamble section may be erroneously detected as a marker during this period. Due to this erroneous detection, the error detection operation by the CRC code starts. However, performing the error detection operation in the preamble section is completely meaningless, and the result of the error detection operation causes a wrong correction, which deteriorates the quality of reproduced sound such as scratch noise.

Therefore, an object of the present invention is to provide a digital signal reproducing apparatus which prevents an error detection operation from being erroneously caused by erroneous detection of a marker when pulling in a PLL.

[Means for solving problems]

According to the present invention, a preamble section for pulling in is added to a PLL before a data section of a predetermined length consisting of a plurality of blocks, and a digital signal in which the data section is coded by an error detection code is recorded on an oblique track. In the digital signal reproducing device for reproducing the recorded magnetic tape, the marker signal for synchronization inserted in each block is detected,
Starting means for starting the decoding operation of the error detection code, first detecting means for detecting the preamble section, and detecting that the output signal of the starting means occurs before the detection signal from the first detecting means A digital signal reproducing apparatus comprising: a second detecting means; and an invalidating means for invalidating the decoding operation when the output of the second detecting means is obtained.

[Action]

In the preamble section, only "1" data is continuously recorded. This preamble section is detected by the preamble detection circuit 6. Further, by detecting the marker added to the beginning of the block (CRC block) of the error detection code of the data section 53 in the reproduced data, a start signal for starting the CRC calculation is formed. By the time the PLL locks in the preamble section, C
Incorrect results may occur as a result of RC operation.
There is a pointer that indicates whether there is an error in each word of the playback data.
It is formed by CRC calculation and stored in RAM. However, the result of the incorrect CRC calculation as described above occurs before the preamble detection signal.
The result of the C operation is treated as invalid.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The description of this embodiment will be made in the following order.

a. Head and tape system of 8mm VTR and track pattern b. Overall configuration of reproduction circuit c. Control operation of RAM d. Preamble detection circuit 6 and area pointer generation circuit 7 e. Modification a. Head and tape system of 8mm VTR Track Pattern In FIG. 1, a reproduction PCM signal in a reproduction signal of 8 mm VTR is supplied to an input terminal indicated by 1. Although not shown, the video signal component in the reproduction signal is separated into an FM-modulated luminance signal and a carrier color signal frequency-converted to a low-frequency carrier frequency, and FM demodulation and frequency conversion processing are performed respectively to obtain the luminance. The reproduced color video signal is obtained by adding the signal and the carrier color signal.

FIG. 3 shows the positional relationship between the head and the tape system of this embodiment. In FIG. 3, 42 is the frame frequency (NTSC
In the case of the system, a drum rotating at 1800 rpm) is shown, and rotating heads 41A and 41B are attached to the drum 42 at angular intervals of 180 °. The extension directions of the magnetic gaps of the rotary heads 41A and 41B are made different, and the crosstalk from the adjacent tracks can be suppressed by the azimuth loss. 8 mm wide magnetic tape on the outer surface of the drum 42
Run at a constant speed with the 3 wound diagonally. The winding angle θ (= θ1 + θ2) of the magnetic tape 43 is
For example, it is set to 221 ° (= 185 ° + 36 °). Within the winding angle θ of the magnetic tape 43, the range of θ1 is the video area, and the range of θ2 where the scans of the rotary heads 41A and 41B overlap is the PCM area.

On the magnetic tape 43, as shown in FIG.
And 1B form alternately inclined tracks. When the rotary head 41A starts scanning the magnetic tape 43, P
The CM area 44A is formed, and then the video area 45A is formed. Similarly, the rotary head 41B forms a PCM area 44B and a video area 45B. The signal (FM modulated luminance signal, FM
The modulated audio signal and the pilot signal for automatic tracking control) are recorded. PCM signals are recorded in the PCM areas 44A and 44B.

The track format of the PCM areas 44A and 44B is the fifth.
This is shown in more detail in the figure. In the same figure, from the right side where the rotary head 41A or 41B starts to contact the magnetic tape 43, first, at the tip, a rotative angle of the head is 5 °, which is a rush 51, and 2.06 ° in the latter half of the rush 51 3H of signal
A period (corresponding to H is a horizontal period) is a preamble 52 for the run-in of the subsequent PLL. Following this preamble 52, a recording area 53 for PCM data is provided over 26.32 °. The 2.06 ° (3H) period following the PCM data recording area 53 is a postamble 54 that serves as a back margin for the recording position deviation at the time of after-recording, and 2.62 ° after that is the video area 45A or 45B and the PCM area. It is used as a guard part 55 with 44A or 44B.
Following the card section 55, video areas 45A and 45B in which a video signal for one field is recorded are provided over 180 °.

Also, in the 8mm VTR, a multi-PCM format for recording only PCM signals is standardized. In the case of multi-PCM, in the winding angle of 221 °, the 216 ° section excluding the terminal 5 ° section is divided into six sections of 36 °.
The six sections are referred to as channel 1, channel 2, ..., Channel 6 according to the order of the head scanning direction. One section has the same format as shown in FIG.

In 8mm VTR, PCM signal for one field, that is, PCM area 44A,
The encoding process and the decoding process of the error correction code are performed with the data recorded in 44B as a unit. FIG. 6 shows a two-dimensional array of data, in which the data contained in each row in the horizontal direction are represented as Q, W0, W1, W2, W3, P, W4, W5, W6, W7 in order. Each row contains 132 pieces of data. Therefore, 8-bit data is arranged in a matrix of (10 × 132). This data includes a stereo PCM signal for one field and six pieces of control data.

In the above data array, each column in the vertical direction is called a block. In FIG. 6, one parity code sequence including the parity data P is formed by 9 pieces of data shown by black dots, and 10 pieces of data shown by white dots are formed by 10 pieces of data shown by white dots.
The other parity code sequence including the parity data P and Q is formed. One parity code sequence including the policy data P is formed from data included in blocks separated by 15 blocks or 14 blocks. Parity data P
And the other parity code sequence including Q is formed from data included in blocks that are equally spaced 12 blocks apart. Each data in one two-dimensional array is included in two different parity code sequences.

Further, a 16-bit CRC code (a type of error detection code using a cyclic code) is added to each block composed of (Q, W0, ... W6, W7). The CRC code detects whether or not there is an error in each block. Since the simple parity is used, the error can be corrected in the case where there is only one data which is determined to have an error by the CRC check in one code sequence. At the time of decoding, the error correction capability is improved by repeatedly performing the decoding on the code sequence including the parity data P and the decoding on the code sequence including the parity data P and Q.

The data on which the error correction code has been encoded is recorded in order from the first block to the 132nd block. At the beginning of each block to be recorded, a 3-bit marker for synchronization and an address code indicating an 8-bit block address are added. The error data that cannot be corrected by the error correction code described above is replaced by the average value of the correct data located before and after it.

b. Overall structure of reproduction circuit In FIG. 1, a reproduction signal is supplied to the PLL indicated by 2 and P
LL2 generates a clock at the same time as the reproduced data. Data processing on the reproducing side is performed by this clock. The reproduction signal is supplied to the marker detection circuit 3 and the demodulation circuit 4.

The demodulation circuit 4 is for demodulating the biphase-modulated signal into a signal having an NRZ waveform, and the output signal of the demodulation circuit 4 is supplied to the CRC calculation circuit 5 and the preamble detection circuit 6. A start signal generated each time a marker is detected is supplied from the marker detection circuit 3 to the CRC calculation circuit 5, and one of the CRC blocks is synchronized with this start signal.
The CRC calculation circuit 5 fetches the block and performs the CRC calculation. The result of the CRC calculation, that is, the CRC pointer indicating the presence or absence of an error in the data of the block is supplied to the area pointer generation circuit 7.

The reproduced PCM signal subjected to the CRC calculation is supplied to the RAM 106 having a capacity of 64 Kbits, for example, via the input terminal 9A of the switch circuit 8. The amount of PCM signal data for one field is
Since it is about 16 Kbits, four memory areas can be secured in RAM10. Preamble detection circuit 6
The area pointer generation circuit 7 generates an area pointer as described later. This area pointer generates a 2-bit area pointer that specifies the memory area of the RAM 10 described above.

The switch circuit 8 selects the input terminal 9A when writing the PCM signal in the RAM 10, and selects the input terminal 9C when correcting the PCM signal written in the RAM 10 by the correction circuit 12 and outputs the corrected PCM signal. The input terminal 9B is selected when the data is read from the RAM 10 and sent to the interpolation circuit 13. Although only one switch circuit 8 is shown in FIG. 1 for simplicity, a switch circuit similar to the switch circuit 8 is provided for each of the four memory areas of the RAM 10.
That is, the period in which the PCM signal is written in one memory area of the RAM 10 and undergoes the correction process and the period in which the corrected PCM signal is sent from the other memory area to the interpolation circuit 13 overlap.

The address of the RAM 10 is generated from the address generation circuit 11. The write address of the RAM 10 is generated based on the block address added to each CRC block, and the read address is formed from the reference clock. RAM1
In each memory area of 0, a PCM signal and parity are written as shown in FIG. 6, and a CRC pointer corresponding to each word is written. The interpolation circuit 13 interpolates by the average value of correct words located before and after the word whose error cannot be corrected. The output signal of the interpolation circuit 13 is converted into an analog signal by the D / A converter 14 and taken out to the output terminal 15.

c. RAM control operation The RAM 10 is controlled by the area pointer from the area pointer generation circuit 7 as shown in FIG. In FIG. 7, each of 0, 1, 2, and 3 is a number for distinguishing the area of the RAM 10. FIG. 7A shows a memory area of the RAM 10 for performing CRC calculation, that is, error detection operation and error correction operation. Detection processing in which the reproduction data output from the CRC calculation circuit 5 and the CRC pointer are written in the RAM 10.
ED is performed, then the reproduction data and the CRC pointer are read from the RAM 10, and the correction processing EC is performed. The area pointer shown in FIG. 7A designates a memory area in which the detection processing ED and the correction processing EC are performed.

If there is an error when pulling in PLL2, this error is removed when writing to RAM10. That is, when the reproduction data is written to the memory area n, if an error at the time of pulling in the PLL is detected, the writing to this memory area is stopped and the writing to the memory area (n + 1) is started. In the example shown in FIG. 7, an error at the time of pulling in PLL2 is detected at the timing shown in FIG. 7B while the reproduction data and the CRC pointer are being written in the memory area 1 of the RAM 10, and therefore the memory area 2
The area pointer has been modified to write data to.

FIG. 7c shows a memory pointer for the memory area in which the data read from the RAM 10 is sent to the interpolation circuit 13 for the sending process DO. With the area pointers shown in FIGS. 7A and 7C, the four memory areas of RAM 10 are
Performs detection processing ED, correction processing EC, and transmission processing DO. As described above, when an error at the time of pulling in the PLL is detected during the writing to the memory area 1, the data written in the memory area 1 halfway (indicated by the diagonal lines in FIG. 7D) is invalidated, Valid data is written in the memory area 2. Therefore, detection processing ED and correction processing EC
Is performed in the memory area 0 and then in the memory area 2.

d. Preamble detection circuit 6 and area pointer generation circuit 7 As described above, the preamble detection circuit 6 and the area pointer generation circuit 7 for generating the area pointer of the RAM 10 are shown in FIG. 2, FIG. 8 and FIG. It will be described with reference to FIG.

As shown in FIG. 2, the preamble detection circuit 6 is set by a counter 21, a decoder 22 to which the 7-bit output of the counter 21 is supplied, and an output of the decoder 22.
26 and an RS flip-flop 23 which is reset by a field switching pulse. The demodulated data from the demodulation circuit 4 is supplied to the clear terminal of the counter 21, and the bit clock is supplied to its clock input terminal.

One CRC block consists of a 3-bit marker, 8-bit address, 80-bit PCM signal and parity, 1
It consists of a total of 107 bits including a 6-bit CRC code. Therefore, in this example, a section in which a preamble pattern (that is, all bits are “1”) continues for 107 bits or more is detected as a preamble. Counter 21
The bit clock is up-counted while the data is "1", and the decoder 22 outputs a decode pulse when 107 counted "1" s continue. The decode pulse from this decoder 22 becomes the preamble detection signal. The RS flip-flop 23 is for holding the output of the decoder 22 until the field switching pulse is supplied from the terminal 26.

A CRC pulse indicating the CRC calculation result from the terminal 30 is supplied to the set terminal of the RS flip-flop 27 provided in the area pointer generation circuit 7. If this CRC pulse goes low when there is no error, RS flip-flop 27
Is set. The RS flip-flop 27 has an OR gate 31
Is reset by the output of. The output () of the RS flip-flop 23 of the preamble detection circuit 6 and the field switching pulse are supplied to the OR gate 31. Therefore, the RS flip-flop 27 holds the CRC pulse and is reset every time the field is switched.

The output pulse of the RS flip-flop 27 and the decode pulse of the decoder 22 are supplied to the OR gate 32. The output of the OR gate 32 and the field switching pulse are supplied to the NAND gate 33. The output of this NAND gate 33 is a 2-bit counter 28
It is supplied to the clock input terminal of. The 2-bit output of the counter 28 is supplied to the 2-bit D-flick flop 29 and taken out to the output terminal 35. The field switching pulse inverted by the inverter 34 is supplied to the clock input terminal of the D flip-flop 29. The output of the D flip-flop 29 is taken out at the output terminal 36.

An area pointer designating a memory area of the RAM 10 is taken out from each of the output terminals 35 and 36. The area pointer obtained at one of the output terminals 35 is for designating a memory area for performing the detection processing ED and the correction processing EC (see FIG. 7A). The area pointer obtained at the other output terminal 36 is for designating a memory area in which the transmission processing DO is performed. When the number of the area pointer obtained at the input side of the D flip-flop 29 is n, the number of the area pointer obtained at the output side thereof is (n-1).

The operations of the preamble detection circuit 6 and the area pointer generation circuit 7 described above will be described with reference to FIGS. 8 and 9.

With the field switching pulse shown in FIG. 8A, the counter
21 is cleared, and thereafter, the counter 21 counts the bit clock, and when 107 bits of "1" are continuously counted, the decoder 22 generates a decode pulse as a preamble detection signal shown in FIG. 8B. RS flip-flop 23 is
Since it is reset by the field switching pulse and set by the decode pulse, its output is as shown in FIG. 8D.

Further, in FIG. 8C, a detection signal is generated from the marker detection circuit 3 at the timing shown by the broken line arrow, and the operation of the CRC calculation circuit 5 is started by this detection signal, and a CRC pulse is generated. FIG. 8C shows the case where the CRC pulse is at the low level (that is, there is no error). this
The CRC pulse is supplied to the set terminal of the RS flip-flop 27. The RS flip-flop 27 is a reset-priority type, and when the reset terminal is at a low level, it is held in the reset state even if the set terminal is at a low level. Therefore, the output (terminal) of the RS flip-flop 27 remains at the high level as shown in FIG. 8E.

The output pulse of the NAND gate 33 becomes high level is 2
Since one of the two inputs is low level,
NAND gate when the field switching pulse shown in
The clock for counter 28 is generated at the output of 33. Therefore, the output of the counter 28 changes stepwise by +1 for each field, and the area pointer advances.

A case where a low-level CRC pulse is generated due to an error when a part of the preamble is used as a marker as shown in FIG.

The output pulse shown in FIG. 9D is generated from the flip-flop 23 by being reset by the field switching pulse shown in FIG. 9A and set by the decode pulse shown in FIG. 9B. If an accidentally generated CRC pulse is supplied to the set terminal of the flip-flop 27 while this output pulse is at the high level, the flip-flop 2
7 is set. Therefore, as shown in FIG. 9E, the output () of the flip-flop 27 becomes low level.

The output () of the flip-flop 27 and the decode pulse are
Since it is supplied to the OR gate 32,
As shown in FIG. F, a pulse signal similar to the decode pulse is generated. Therefore, not only the field switching pulse but also the clock pulse corresponding to the decode pulse is generated from the NAND gate 33 and supplied to the counter 28. In other words, the field switching pulse causes the counter 28, which has been incremented for each field, to be counted up. Therefore, the area pointer obtained at the output terminal 35 is
It advances to (n → n + 1) and immediately changes to (n + 2).
As a result, the memory area (n + 1) in which the false detection data is written is discarded as an invalid one.

e. Modified Example In the above-described embodiment, the memory area for 4 fields is set in the RAM 10. However, a RAM having a memory area for 2 fields or 3 fields may be used. In the case of a RAM having a memory area for two fields, when the wrong CRC is detected, it is necessary to re-initialize the memory area in which the reproduction data of that field and the CRC pointer have already been written.

〔The invention's effect〕

Like the 8mm VTR, the playback data is supplied intermittently, so the playback PLL pull-in operation is performed for each field.
In the present invention, when the CRC operation is performed and the CRC output indicating that there is no error is generated, the erroneous CRC output generated before the detection of the preamble is invalidated in the present invention. Therefore, according to the present invention, it is possible to determine that completely incorrect data is correct due to an erroneous CRC output, and as a result, avoid problems such as occurrence of scratch noise in reproduced sound.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an essential portion of an embodiment of the present invention, and FIGS. 3, 4, and 5 are applicable to the present invention. 8mmVTR head / tape system schematic diagram, track pattern schematic diagram and track format schematic diagram, FIG. 6 is a schematic diagram used for explaining the error correction code of the 8mmVTR to which the present invention can be applied. , FIG. 7, FIG. 8 and FIG. 9 are time charts used for explaining the operation of one embodiment of the present invention. Description of main symbols in the drawings 1: Playback data input terminal, 2: PLL, 3: Marker detection circuit, 5: CRC operation circuit, 6: Preamble detection circuit, 7: Area pointer generation circuit, 10: RAM.

Claims (1)

[Claims] 1. A digital signal in which a preamble section for pulling in a PLL is added before a data section of a predetermined length composed of a plurality of blocks and the data section is encoded by an error detection code for each block is diagonal. In the digital signal reproducing apparatus for reproducing the magnetic data recorded in the track, the starting means for detecting the synchronizing marker signal inserted for each block and starting the decoding operation of the error detecting code, and the preamble section are A first detecting means for detecting; a second detecting means for detecting that an output signal of the starting means has occurred before a detection signal from the first detecting means; and a second detecting means for detecting the second detecting means. A digital signal reproducing device comprising: invalidating means for invalidating the decoding operation when an output is obtained.