JPH0773124B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0773124B2 JPH0773124B2 JP59281627A JP28162784A JPH0773124B2 JP H0773124 B2 JPH0773124 B2 JP H0773124B2 JP 59281627 A JP59281627 A JP 59281627A JP 28162784 A JP28162784 A JP 28162784A JP H0773124 B2 JPH0773124 B2 JP H0773124B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- fet
- forming
- conductivity type
- well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、CMOS−FETと抵抗とを兼備する半導体装置の
製造方法に関するものである。The present invention relates to a method for manufacturing a semiconductor device having both a CMOS-FET and a resistor.
従来の技術 上記の様な半導体装置は、例えば螢光表示管の駆動回路
に使用されている。第４図は、この様な駆動回路の一例
を示している。この例では、第４図に示す様なグリッド
11aの電位を制御して螢光表示管11を点滅させるために
ｐチャネル高耐圧MOS−FET12と抵抗13とが使用されてお
り、第４図には示されていないが更にその他にCMOS−FE
Tが使用されている。2. Description of the Related Art The semiconductor device as described above is used, for example, in a driving circuit of a fluorescent display tube. FIG. 4 shows an example of such a drive circuit. In this example, the grid as shown in Fig. 4
A p-channel high breakdown voltage MOS-FET 12 and a resistor 13 are used to control the potential of 11a to blink the fluorescent display tube 11. Although not shown in FIG.
T is used.
抵抗13は、FET12がオフの時にグリッド11aの電位をカソ
ード11bの電位に引き戻すためのプルダウン抵抗であ
り、高耐圧で且つ高抵抗という特性が要求される。The resistor 13 is a pull-down resistor for returning the potential of the grid 11a to the potential of the cathode 11b when the FET 12 is off, and is required to have high withstand voltage and high resistance.
発明が解決しようとする問題点 ところが従来は、CMOS−FETの製造工程とは別個の工程
で抵抗13を製造しており、半導体装置の製造工程が全体
として多かった。Problems to be Solved by the Invention However, conventionally, the resistor 13 is manufactured in a process separate from the manufacturing process of the CMOS-FET, and the manufacturing process of the semiconductor device is large in total.
なお本発明に関連する先行技術としては、実公昭47−38
942号公報に記載されている技術等が考えられる。The prior art related to the present invention is as follows.
The technology described in Japanese Patent No. 942 may be considered.
問題点を解決するための手段 本発明による半導体装置の製造方法は、第１導電型の半
導体基板14のうちで第１及び第２の領域にCMOS−FET35
を形成し、第３の領域に抵抗13を形成する半導体装置の
製造方法において、前記第１の領域に第２導電型の第１
のウエル15を形成すると同時に、前記第３の領域のうち
の両端部に第２導電型の第２のウエル15を形成する工程
と、前記第１の領域に第２導電型のチャネルストッパ21
を形成すると同時に、前記第３の領域のうちで前記両端
部同士を結ぶ中間部に相対的に低濃度の第２導電型の第
４の領域41を形成する工程と、前記半導体基板14の表面
を選択的に熱酸化することによって、少なくとも前記チ
ャネルストッパ21及び前記第４の領域41上にフィールド
酸化膜23を形成する工程と、前記第２の領域に第２導電
型のソース・ドレイン27を形成すると同時に、前記第２
のウエル15中に相対的に高濃度の第２導電型のオーミッ
ク接続部42を形成する工程とを夫々具備している。According to the method of manufacturing a semiconductor device of the present invention, the CMOS-FET 35 is formed in the first and second regions of the first conductivity type semiconductor substrate 14.
And a resistor 13 is formed in the third region in the method of manufacturing a semiconductor device, wherein the first conductivity type first region is formed in the first region.
Simultaneously forming the well 15 of the second region, a step of forming second wells 15 of the second conductivity type at both ends of the third region, and a channel stopper 21 of the second conductivity type in the first region.
And forming a fourth region 41 of the second conductivity type having a relatively low concentration in an intermediate portion connecting the both ends of the third region, and a surface of the semiconductor substrate 14. Forming a field oxide film 23 on at least the channel stopper 21 and the fourth region 41 by selectively thermally oxidizing the second conductive type source / drain 27 in the second region. At the same time as forming, the second
And forming a relatively high concentration second conductivity type ohmic contact portion 42 in the well 15.
作用 本発明による半導体装置の製造方法では、抵抗13を構成
する第４の領域41及び第２のウエル15がCMOS−FET35の
夫々チャネルストッパ21及び第１のウエル15と同時に形
成され、抵抗13のオーミック接続部42もCMOS−FET35の
ソース・ドレイン27と同時に形成され、しかも、オーミ
ック接続部42は第２のウエル15中に形成される。In the method of manufacturing a semiconductor device according to the present invention, the fourth region 41 and the second well 15 forming the resistor 13 are formed simultaneously with the channel stopper 21 and the first well 15 of the CMOS-FET 35, respectively. The ohmic connection 42 is also formed at the same time as the source / drain 27 of the CMOS-FET 35, and the ohmic connection 42 is formed in the second well 15.
従って、CMOS−FET35の製造工程に特別な工程を追加す
ることなく、CMOS−FET35の製造と同時に高耐圧且つ高
抵抗でしかもオーミック接続部42を有する抵抗13を製造
することができる。Therefore, without adding a special step to the manufacturing process of the CMOS-FET 35, it is possible to manufacture the resistor 13 having high withstand voltage and high resistance and having the ohmic connection portion 42 simultaneously with the manufacturing of the CMOS-FET 35.
しかも、CMOS−FET35のチャネルストッパ21上のみなら
ず抵抗13を構成する第４の領域41上にもフィールド酸化
膜23を形成しているので、抵抗13に対する寄生MOS効果
が少ない。Moreover, since the field oxide film 23 is formed not only on the channel stopper 21 of the CMOS-FET 35 but also on the fourth region 41 forming the resistor 13, the parasitic MOS effect on the resistor 13 is small.
実施例 以下、螢光表示管の駆動回路に適用した本発明の一実施
例を、第１図〜第３図を参照しながら説明する。本実施
例で使用されているCMOS−FETの製造方法を第２図によ
って最初に説明する。EXAMPLE An example of the present invention applied to a driving circuit for a fluorescent display tube will be described below with reference to FIGS. 1 to 3. A method of manufacturing the CMOS-FET used in this embodiment will be described first with reference to FIG.
まず第2A図に示す様に、ｎ型半導体基板14のｎチャネル
MOS−FETとなるべき領域に通常の方法でボロンを拡散す
ることによって、ｐウエル15を形成する。その後、基板
14の表面全体に薄いパッド酸化膜16を成長させる。次に
酸化膜16上の全体に窒化膜17をCVD成長させ、ｎチャネ
ルMOS−FET及びｐチャネルMOS−FETの活性領域となるべ
き部分にのみこの窒化膜17を残る。First, as shown in FIG. 2A, the n-channel of the n-type semiconductor substrate 14
The p-well 15 is formed by diffusing boron in the area to be the MOS-FET by a conventional method. Then the substrate
A thin pad oxide film 16 is grown on the entire surface of 14. Next, a nitride film 17 is grown on the entire surface of the oxide film 16 by CVD, and the nitride film 17 is left only in the portions to be active regions of the n-channel MOS-FET and the p-channel MOS-FET.
次に第2B図に示す様に、窒化膜17をマスクとしてｐウエ
ル15にボロンをイオン注入することによってｎチャネル
ストッパ21を形成し、更にｐウエル15以外の領域にリン
をイオン注入するこによってｐチャネルストッパ22を形
成する。その後、素子分離用のフィールド酸化膜23を選
択酸化法で成長させてから、窒化膜17を除去する。Next, as shown in FIG. 2B, the n-channel stopper 21 is formed by ion-implanting boron into the p-well 15 using the nitride film 17 as a mask, and phosphorus is ion-implanted into regions other than the p-well 15. A p-channel stopper 22 is formed. After that, a field oxide film 23 for element isolation is grown by a selective oxidation method, and then the nitride film 17 is removed.
続いて第2C図に示す様に、パット酸化膜16の除去後にゲ
ート酸化膜24を成長させる。そしてこのゲート酸化膜24
及びフィールド酸化膜23上に多結晶シリコンをCVD成長
させてパターニングするとによって、ゲート電極25を形
成する。Subsequently, as shown in FIG. 2C, a gate oxide film 24 is grown after removing the pad oxide film 16. And this gate oxide film 24
A gate electrode 25 is formed by growing polycrystalline silicon on the field oxide film 23 by CVD and patterning it.
その後に第2D図に示す様に、ゲート電極25とフィールド
酸化膜23とをマスクとして、ｐウエル15にヒ素をイオン
注入することによって、ｎチャネル側のソース・ドレイ
ン26を形成する。またｐウエル15以外を領域にボロンを
イオン注入することによって、ｐチャネル側のソース・
ドレイン27を形成する。After that, as shown in FIG. 2D, arsenic is ion-implanted into the p-well 15 using the gate electrode 25 and the field oxide film 23 as a mask to form the source / drain 26 on the n-channel side. Also, by implanting boron ions in regions other than the p-well 15, the p-channel source
The drain 27 is formed.
最後に第2E図に示す様に、PSG（リンシリケートガラ
ス）を成長させて絶縁膜31を形成し、更にこの絶縁膜31
とゲート酸化膜24とに開孔を形成して通常の方法でAl電
極32を形成する。これによって、ｎチャネルMOS−FET33
とｐチャネルMOS−FET34とを有するCMOS−FET35が製造
される。Finally, as shown in FIG. 2E, PSG (phosphosilicate glass) is grown to form an insulating film 31.
An opening is formed in the gate oxide film 24 and the gate oxide film 24, and an Al electrode 32 is formed by a usual method. As a result, the n-channel MOS-FET33
A CMOS-FET 35 having a p-channel MOS-FET 34 is manufactured.
次に、ｐチャネル高耐圧MOS−FET12の製造方法を第３図
によって説明する。このFET12は、基板14のCMOS−FET35
とは異なる領域に形成されるが、第2C図に示した工程ま
ではｐチャネルMOS−FET34と全く同様の工程によって形
成される。Next, a method of manufacturing the p-channel high breakdown voltage MOS-FET 12 will be described with reference to FIG. This FET 12 is a CMOS-FET 35 on the substrate 14.
Although it is formed in a region different from that of the above, it is formed by the same process as the p-channel MOS-FET 34 up to the process shown in FIG. 2C.
そして第2C図に示した工程の次に、ゲート電極25とフィ
ールド酸化膜23とをマスクとして、ボロンを比較的低濃
度にイオン注入する。その後、高耐圧を要求されるドレ
イン側に、ゲート電極25から離間した開孔を有するフォ
トレジストを形成する。そしてｐチャネルMOS−FET34の
ソース・ドレイン27の形成時にこのFET12の領域にもボ
ロンを高濃度にイオン注入することによって、このFET1
2のソース・ドレインを形成する。Then, after the step shown in FIG. 2C, boron is ion-implanted at a relatively low concentration using the gate electrode 25 and the field oxide film 23 as a mask. After that, a photoresist having an opening separated from the gate electrode 25 is formed on the drain side where high breakdown voltage is required. Then, when the source / drain 27 of the p-channel MOS-FET 34 is formed, boron is also ion-implanted at a high concentration in the region of the FET 12 to form the FET 1
Form the source and drain of 2.
この様にすると、第３図に示す様に、FET12のドレイン
側では、ボロンの濃度が高いp+領域36が濃度の低いp-領
域37に囲まれており、オフセットゲート型の高耐圧MOS
−FET12が製造される。By doing so, as shown in FIG. 3, on the drain side of the FET 12, the p + region 36 having a high concentration of boron is surrounded by the p − region 37 having a low concentration, and the offset gate type high withstand voltage MOS is formed.
-FET 12 is manufactured.
次に、抵抗13の製造方法を第１図によって説明する。こ
の抵抗13は基板14のCMOS−FET35及び高耐圧MOS−FET12
とは異なる領域に形成するが、この抵抗13の両端部を構
成するｐウエル15はｎチャネルMOS−FET33のｐウエル15
と同時に形成する。また抵抗13の両端部を構成するｐウ
エル15上にのみ窒化膜17のパターンを残しておき、その
他の領域には残さない。Next, a method of manufacturing the resistor 13 will be described with reference to FIG. This resistor 13 is a CMOS-FET 35 and a high voltage MOS-FET 12 on the substrate 14.
Although it is formed in a region different from that of, the p well 15 forming both ends of the resistor 13 is the p well 15 of the n-channel MOS-FET 33.
Form at the same time. Further, the pattern of the nitride film 17 is left only on the p-well 15 which constitutes both ends of the resistor 13, and is not left in other regions.
その後、ｎチャネルMOS−FET33のｎチャネルストッパ21
の形成時に、この抵抗13の中間部つまりｐウエル15間に
もボロンをイオン注入してｐ領域41を形成する。またｐ
チャネルMOS−FET34のソース・ドレイン27の形成時に、
この抵抗13の両端部つまりｐウエル15中にもボロンをイ
オン注入してオーミック接続部42を形成する。Then, n channel stopper 21 of n channel MOS-FET 33
At the time of formation, boron is also ion-implanted into the intermediate portion of the resistor 13, that is, between the p wells 15 to form the p region 41. Also p
When forming the source / drain 27 of the channel MOS-FET 34,
Boron is also ion-implanted into both ends of the resistor 13, that is, the p-well 15, to form the ohmic contact portion 42.
本実施例では、CMOS−FET35の製造に際してｐウエル15
を形成してから窒化膜17のパターンを形成する様にした
が、これらの工程は互いに逆でもよい。つまり、窒化膜
17のパターンを形成してからこの窒化膜17を打ち抜く様
にイオン注入を行うことによって、ｐウエル15を形成す
る様にしてもよい。この場合には、抵抗13の製造に際し
ても、まず窒化膜17のパターンを形成し、その後にｐウ
エル15を形成する。In this embodiment, the p-well 15 is used in manufacturing the CMOS-FET 35.
Although the pattern of the nitride film 17 is formed after forming the above, these steps may be reversed. That is, the nitride film
The p well 15 may be formed by forming the pattern of 17 and then performing ion implantation so as to punch out the nitride film 17. In this case, also when manufacturing the resistor 13, the pattern of the nitride film 17 is first formed, and then the p well 15 is formed.
以上の様な本発明の実施例によれば、抵抗13の中間部を
構成しているｐ領域41が、ｎチャネルMOS−FET33のｎチ
ャネルストッパ21と同時に形成される。従って、ｐ領域
41は不純物の濃度が低くしかも厚さが薄いので、抵抗13
は高抵抗である。According to the embodiment of the present invention as described above, the p region 41 forming the intermediate portion of the resistor 13 is formed simultaneously with the n channel stopper 21 of the n channel MOS-FET 33. Therefore, the p region
Since 41 has a low impurity concentration and a thin thickness,
Is high resistance.
またｐウエル15及び基板14の不純物の濃度も低いので、
ｐ領域41及びｐウエル15で構成されている抵抗13と基板
14との接合が不純物濃度の低いもの同士の接合であり、
抵抗13は高耐圧である。Also, since the concentration of impurities in the p well 15 and the substrate 14 is low,
Resistor 13 composed of p region 41 and p well 15 and substrate
The junction with 14 is a junction of those with low impurity concentration,
The resistor 13 has a high breakdown voltage.
また、ｐ領域41上にも厚いフィールド酸化膜23を成長さ
せているので、ｐ領域41上に配線（図示せず）がレイア
ウトされても、この配線からの電界によってｐ領域41の
不純物濃度が変動して導電率も変動するという寄生MOS
効果が少ない。Further, since the thick field oxide film 23 is grown also on the p region 41, even if a wiring (not shown) is laid out on the p region 41, the electric field from the wiring causes the impurity concentration of the p region 41 to increase. Parasitic MOS that changes and conductivity also changes
Less effective.
なお、以上の実施例では、ｎ型半導体基板14を用いて、
ｐウエル15を有するCMOS−FET35及びｐチャネル高耐圧M
OS−FET12の製造と同時に抵抗13を製造する様にした
が、ｐ型半導体基板を用いて、ｎウエルを有するCMOS−
FET及びｎチャネル高耐圧MOS−FETの製造と同時に抵抗1
3を製造する様にしてもよい。この場合、抵抗13の製造
はｐチャネルストッパの形成と同時に行う。In the above embodiment, the n-type semiconductor substrate 14 is used,
CMOS-FET 35 with p-well 15 and p-channel high breakdown voltage M
Although the resistor 13 is manufactured at the same time as the OS-FET 12 is manufactured, a CMOS-type having a n-well is formed by using a p-type semiconductor substrate.
Simultaneous production of FET and n-channel high voltage MOS-FET
3 may be manufactured. In this case, the resistor 13 is manufactured simultaneously with the formation of the p-channel stopper.
発明の効果 上述の如く、本発明による半導体装置の製造方法によれ
ば、CMOS−FETの製造工程に特別な工程を追加すること
なく、CMOS−FETの製造と同時に高耐圧且つ高抵抗でし
かもオーミック接続部を有する抵抗を製造することがで
きるので、半導体装置の製造工程が全体として少なくて
済む。しかも、抵抗に対する寄生MOS効果が少ないの
で、抵抗の抵抗値が安定な半導体装置を製造することも
できる。EFFECTS OF THE INVENTION As described above, according to the method for manufacturing a semiconductor device of the present invention, a high breakdown voltage, high resistance, and ohmic resistance can be achieved simultaneously with the manufacture of the CMOS-FET without adding a special step to the manufacturing process of the CMOS-FET. Since the resistor having the connection portion can be manufactured, the number of manufacturing steps of the semiconductor device can be reduced as a whole. Moreover, since the parasitic MOS effect on the resistance is small, it is possible to manufacture a semiconductor device in which the resistance value of the resistance is stable.
第1A図及び第1B図は本発明の一実施例における抵抗を示
す夫々側断面図及び平面図、第2A図〜第2E図は一実施例
におけるCMOS−FETの製造工程を順次示す側断面図、第
３図は高耐圧MOS−FETを示す側断面図、第４図は本発明
を適用可能な螢光表示管の駆動回路を示す回路図であ
る。 なお図面に用いられた符号において、 13……抵抗 14……ｎ型半導体基板 21……ｎチャネルストッパ 23……フィールド酸化膜 27……ソース・ドレイン 35……CMOS−FET 41……ｐ領域 42……オーミック接続部 43……p-領域 である。1A and 1B are side sectional views and a plan view, respectively, showing a resistance in one embodiment of the present invention, and FIGS. 2A to 2E are side sectional views sequentially showing a manufacturing process of a CMOS-FET in one embodiment. FIG. 3 is a side sectional view showing a high voltage MOS-FET, and FIG. 4 is a circuit diagram showing a driving circuit of a fluorescent display tube to which the present invention can be applied. In the reference numerals used in the drawings, 13: resistance 14: n-type semiconductor substrate 21: n-channel stopper 23: field oxide film 27: source / drain 35: CMOS-FET 41: p region 42 …… Ohmic connection 43 …… is a p - region.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/06 27/08 ３３１ Ｂ 9170−4Ｍ (56)参考文献 特開 昭56−83961（ＪＰ，Ａ) 特開 昭56−130960（ＪＰ，Ａ) 特開 昭57−118662（ＪＰ，Ａ) 特開 昭58−32448（ＪＰ，Ａ) 特開 昭52−103979（ＪＰ，Ａ)Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication location H01L 27/06 27/08 331 B 9170-4M (56) Reference JP-A-56-83961 (JP, A) JP-A-56-130960 (JP, A) JP-A-57-118662 (JP, A) JP-A-58-32448 (JP, A) JP-A-52-103979 (JP, A)
Claims (1)
第２の領域にCMOS−FETを形成し、第３の領域に抵抗を
形成する半導体装置の製造方法において、 前記第１の領域に第２導電型の第１のウエルを形成する
と同時に、前記第３の領域のうちの両端部に第２導電型
の第２のウエルを形成する工程と、 前記第１の領域に第２導電型のチャネルストッパを形成
すると同時に、前記第３の領域のうちで前記両端部同士
を結ぶ中間部に相対的に低濃度の第２導電型の第４の領
域を形成する工程と、 前記半導体基板の表面を選択的に熱酸化することによっ
て、少なくとも前記チャネルストッパ及び前記第４の領
域上にフィールド酸化膜を形成する工程と、 前記第２の領域に第２導電型のソース・ドレインを形成
すると同時に、前記第２のウエル中に相対的に高濃度の
第２導電型のオーミック接続部を形成する工程とを夫々
具備する半導体装置の製造方法。1. A method of manufacturing a semiconductor device, wherein a CMOS-FET is formed in first and second regions and a resistor is formed in a third region of a semiconductor substrate of a first conductivity type, wherein Forming a first well of the second conductivity type in the region and simultaneously forming second wells of the second conductivity type in both ends of the third region; and forming a second well in the first region. Forming a channel stopper of conductivity type and simultaneously forming a fourth region of a second conductivity type of relatively low concentration in an intermediate portion connecting the both ends of the third region; Forming a field oxide film on at least the channel stopper and the fourth region by selectively thermally oxidizing the surface of the substrate; and forming a second conductivity type source / drain in the second region. At the same time, the phase in the second well The method of manufacturing a semiconductor device that a process respectively including the formed ohmic connection portion of the second conductivity type high concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59281627A JPH0773124B2 (en) | 1984-12-27 | 1984-12-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59281627A JPH0773124B2 (en) | 1984-12-27 | 1984-12-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61156763A JPS61156763A (en) | 1986-07-16 |
| JPH0773124B2 true JPH0773124B2 (en) | 1995-08-02 |
Family
ID=17641750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59281627A Expired - Lifetime JPH0773124B2 (en) | 1984-12-27 | 1984-12-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0773124B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9172987B2 (en) | 1998-07-07 | 2015-10-27 | Rovi Guides, Inc. | Methods and systems for updating functionality of a set-top box using markup language |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52103979A (en) * | 1976-02-26 | 1977-08-31 | Nec Corp | Semiconductor resistor element |
| JPS5683961A (en) * | 1979-12-13 | 1981-07-08 | Toshiba Corp | Semiconductor device |
| JPS56130960A (en) * | 1980-03-17 | 1981-10-14 | Fujitsu Ltd | Manufacture of semiconductor integrated circuit |
| JPS57118662A (en) * | 1981-01-16 | 1982-07-23 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS5832448A (en) * | 1982-02-24 | 1983-02-25 | Nec Corp | Manufacture of complementary mos field-effect transistor |
-
1984
- 1984-12-27 JP JP59281627A patent/JPH0773124B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9172987B2 (en) | 1998-07-07 | 2015-10-27 | Rovi Guides, Inc. | Methods and systems for updating functionality of a set-top box using markup language |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61156763A (en) | 1986-07-16 |
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| Date | Code | Title | Description |
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| EXPY | Cancellation because of completion of term |