JPH0773132B2 - Semiconductor light emitting device and method of manufacturing the same - Google Patents
Semiconductor light emitting device and method of manufacturing the sameInfo
- Publication number
- JPH0773132B2 JPH0773132B2 JP6872286A JP6872286A JPH0773132B2 JP H0773132 B2 JPH0773132 B2 JP H0773132B2 JP 6872286 A JP6872286 A JP 6872286A JP 6872286 A JP6872286 A JP 6872286A JP H0773132 B2 JPH0773132 B2 JP H0773132B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitting device
- light emitting
- mesa stripe
- semiconductor light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体発光装置及びその製造方法に関する。The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.
[従来の技術] 従来の埋込みヘテロ構造を有する半導体発光装置は、第
4図に示す如く、GaAs半導体層からなる活性層3をGa
1-xAlxAsx (X〜0.3)からなる埋込み層6で囲んだ構造
を有している。この半導体発光装置の構造を以下の第5
図を参照してその製造工程に従って説明する。第5図
(A)に示す如く、n型GaAs基板1上にn型Ga0.7Al0.3
Asクラッド層2、p型GaAs活性層3,p型Ga0.7Al0.3Asク
ラッド層4及びp型GaAsキャップ層5を順次連続的に結
晶成長させる。この際結晶成長法としては、液相エピタ
キシャル成長法(LPE法)、分子線エピタキシャル成長
法(MBE法)、有機金属化学気相成長法(MO−CVD法)等
が用いられる。[Prior Art] In a conventional semiconductor light emitting device having a buried hetero structure, as shown in FIG.
It has a structure surrounded by a buried layer 6 made of 1-x Al x As x (X to 0.3) . The structure of this semiconductor light emitting device is described in the following fifth
The manufacturing process will be described with reference to the drawings. As shown in FIG. 5 (A), n-type Ga 0.7 Al 0.3 is formed on the n-type GaAs substrate 1.
The As clad layer 2, the p-type GaAs active layer 3, the p-type Ga 0.7 Al 0.3 As clad layer 4, and the p-type GaAs cap layer 5 are successively and successively grown. At this time, as the crystal growth method, a liquid phase epitaxial growth method (LPE method), a molecular beam epitaxial growth method (MBE method), a metal organic chemical vapor deposition method (MO-CVD method), or the like is used.
次に、第5図(B)に示す如く、p型GaAsキヤップ層5
上に所定パターンのSiO2膜からなるマスク9を載置し、
これをマスクにしてn型Ga0.7Al0.3Asクラッド層2,p型G
aAs活性層3,p型Ga0.7Al0.3Asクラッド層4及びp型GaAs
キャップ層5にGaAs基板1に達するメサエッチングを施
す。Next, as shown in FIG. 5 (B), the p-type GaAs cap layer 5 is formed.
A mask 9 made of a SiO 2 film having a predetermined pattern is placed on the above,
Using this as a mask, n-type Ga 0.7 Al 0.3 As clad layer 2, p-type G
aAs active layer 3, p-type Ga 0.7 Al 0.3 As clad layer 4 and p-type GaAs
The cap layer 5 is subjected to mesa etching to reach the GaAs substrate 1.
次に、第5図(C)に示す如く、メサエッチングにて露
出したGaAs基板1の主面上にp型GaAs活性層3を完全に
埋込み覆うようにしてGa0.7Al0.3As埋込層6を液相エピ
タキシャル成長法にて形成し、半導体発光装置を得る。
ここで、液相エピタキシャル成長法を使用するのは、マ
スク9を誘電体薄膜としてキャップ層5上に結晶成長が
起きるのを防ぐためである。また、注入電流を活性層3
の部分にのみ集中させて発光装置の動作電流を低減させ
るためにGa0.7Al0.3As埋込層6の電気抵抗を高抵抗とす
ることや、或は第5図(D)に示す如く、埋込層6′を
GaAs基板1からp型Ga0.7Al0.3As層6′aと、n型Ga
0.7Al0.3As層6′bを順次積層してnpn構造にすること
等が行われている。Next, as shown in FIG. 5 (C), the Ga 0.7 Al 0.3 As embedded layer 6 is formed so as to completely cover the p-type GaAs active layer 3 on the main surface of the GaAs substrate 1 exposed by mesa etching. Are formed by a liquid phase epitaxial growth method to obtain a semiconductor light emitting device.
The liquid phase epitaxial growth method is used here to prevent crystal growth on the cap layer 5 by using the mask 9 as a dielectric thin film. In addition, the injection current is applied to the active layer 3
In order to reduce the operating current of the light-emitting device by concentrating only on the portion of (7), the electric resistance of the Ga 0.7 Al 0.3 As embedded layer 6 is made high, or as shown in FIG. Include layer 6 '
From the GaAs substrate 1, p-type Ga 0.7 Al 0.3 As layer 6′a and n-type Ga 0.7
For example, 0.7 Al 0.3 As layers 6'b are sequentially laminated to form an npn structure.
なお、第4図中7は、GaAs基板1の裏面側に形成された
負電極用蒸着膜であり、8は、埋込層6及びキャップ層
5の主面側に形成された正電極用蒸着膜である。In FIG. 4, 7 is a negative electrode vapor deposition film formed on the back surface side of the GaAs substrate 1, and 8 is a positive electrode vapor deposition film formed on the main surface sides of the embedding layer 6 and the cap layer 5. It is a film.
[発明が解決しようとする問題点] このような従来の半導体発光装置は次のような問題点を
有する。活性層3の側壁部がメサエッチングの際に空気
にさらされるため、活性層端部及びその近傍に生じる結
晶欠陥や不純物の蓄積等が素子特性を悪くする。すなわ
ち、結晶欠陥等に付随する界面準位に関与した注入キャ
リアの非発光再結合が発光効率を低下させ、更には結晶
欠陥の増殖による素子劣化が素子の長期間の信頼性を著
しく損わせていた。[Problems to be Solved by the Invention] Such a conventional semiconductor light emitting device has the following problems. Since the side wall of the active layer 3 is exposed to the air during the mesa etching, the crystal characteristics, the accumulation of impurities and the like generated at the end of the active layer and the vicinity thereof deteriorate the device characteristics. That is, the non-radiative recombination of the injected carriers involved in the interface states associated with crystal defects and the like reduces the light emission efficiency, and further, the element deterioration due to the multiplication of crystal defects significantly impairs the long-term reliability of the element. It was
また、従来の半導体発光装置の製造方法は、次のような
問題点を有する。すなわち、結晶成長が2度必要であ
り、製造工程が複雑になる。更に近年膜厚制御性や膜厚
の均一性を考慮して、LPE(Liquid phase epitaxy)法
に代わる結晶成長法として量産化の観点からMO CVD(Me
tal Organic Chemical Vapor Peposition)法が注目さ
れているが、これらの気相成長法では第5図(C)及び
第5図(D)に示すような選択エピタキシー技術が確立
されておらず第4図に示したような半導体発光装置を容
易に量産することができない問題があった。In addition, the conventional method for manufacturing a semiconductor light emitting device has the following problems. That is, the crystal growth is required twice, which complicates the manufacturing process. Furthermore, in recent years, considering the film thickness controllability and film thickness uniformity, MO CVD (Me) has been adopted from the viewpoint of mass production as a crystal growth method that replaces the LPE (Liquid phase epitaxy) method.
tal Organic Chemical Vapor Peposition) method is drawing attention, but in these vapor phase growth methods, selective epitaxy technology as shown in FIGS. 5 (C) and 5 (D) has not been established. There is a problem that the semiconductor light emitting device as shown in (3) cannot be easily mass-produced.
本発明は、かかる点に鑑みてなされたものであり、活性
層部分のエッチング処理を不要にして、一度で一連の結
晶成長処理によって活性層を埋込む埋込層までの形成が
可能であり、長期に亘って高い信頼性を発揮することが
できる半導体発光装置及びその製造方法を開発したもの
である。The present invention has been made in view of the above points, and it is possible to form an embedded layer in which the active layer is buried by embedding the active layer by a series of crystal growth processes at one time, without the need for etching the active layer. The present invention has developed a semiconductor light emitting device capable of exhibiting high reliability for a long period of time and a manufacturing method thereof.
[問題点を解決するための手段] 本発明は、半導体基板の主面に<110>方向またはこれ
と等価な結晶軸方向に略平行に筋状に突出したメサスト
ライプと、該メサストライプ上に積層され、両側面が
{}B面である活性層を含むダブルヘテロ構造
と、前記メサストライプを除く前記半導体基板の露出し
た主面上に該ダブルヘテロ構造を埋込むように形成さ
れ、該活性層よりも屈折率が小さく、かつ、禁則帯幅の
大きい半導体層とを具備することを特徴とする半導体発
光装置である。[Means for Solving the Problems] The present invention provides a mesa stripe protruding in a stripe shape substantially parallel to a <110> direction or a crystal axis direction equivalent to the main surface of a semiconductor substrate, and a mesa stripe on the mesa stripe. A double heterostructure including an active layer that is laminated and has {} B planes on both sides, and the double heterostructure is formed on the exposed main surface of the semiconductor substrate except the mesa stripe so as to be embedded in the active layer. A semiconductor light emitting device comprising: a semiconductor layer having a refractive index smaller than that of the layer and a bandgap larger than that of the layer.
本発明における半導体発光装置は、前記ダブルヘテロ構
造が、二綾面が{}B面である断面二等辺三角形
形状であることが好ましい。In the semiconductor light emitting device according to the present invention, it is preferable that the double hetero structure has an isosceles triangular cross section in which a double cross is a {} B plane.
また、本発明は、半導体基板の主面に<110>方向また
はこれと等価な結晶軸方向に略平行に筋状に突出したメ
サストライプを形成する工程と、該メサストライプ上に
両側面が{}B面である活性層を含むダブルヘテ
ロ構造を積層する工程と、前記メサストライプを除く前
記半導体基板の露出した主面上に該ダブルヘテロ構造を
埋込むようにして該活性層よりも屈折率が小さく、か
つ、禁則帯幅の大きい半導体層を前記ダブルヘテロ構造
の結晶成長工程と一連の結晶成長工程で形成する工程と
を具備することを特徴とする半導体発光装置の製造方法
である。In addition, the present invention comprises a step of forming a mesa stripe projecting in a stripe shape on the main surface of a semiconductor substrate in a direction substantially parallel to the <110> direction or a crystal axis direction equivalent to the <110> direction. A step of stacking a double hetero structure including an active layer which is a B-plane, and having a refractive index smaller than that of the active layer by embedding the double hetero structure on the exposed main surface of the semiconductor substrate excluding the mesa stripe. A method of manufacturing a semiconductor light emitting device, comprising: a crystal growth step of the double hetero structure and a step of forming a semiconductor layer having a large bandgap by a series of crystal growth steps.
ここで、本発明の半導体発光装置及びその製造方法の重
要な構成は次の点にある。すなわち、第3図に示ず如
く、半導体基板20の<110>方向またはこれと結晶学的
に等価な結晶軸方向に筋状に突出したメサストライプ21
を形成しておくと、半導体基板20上にMO−CVD法等にて
結晶成長を施した場合、メサストライプ21の両側の半導
体基板20の主面上には成長層22が形成されるが、メサス
トライプ21面上には成長層22を分離した形で{}
面(B面)に相当する面によって制限された断面が二等
辺三角形形状のストライプ構造23が形成される。更に、
この{}面(B面)上への結晶成長速度は他の面
上への結晶成長速度に比べて極めて小さいことが実験的
に確認されている。かかる技術的事項に基づいて本発明
は創作されたものである。Here, the important points of the semiconductor light emitting device and the manufacturing method thereof according to the present invention are as follows. That is, as shown in FIG. 3, the mesa stripes 21 protruding linearly in the <110> direction of the semiconductor substrate 20 or in the crystal axis direction which is crystallographically equivalent thereto.
When the crystal growth is performed on the semiconductor substrate 20 by MO-CVD method or the like, the growth layer 22 is formed on the main surface of the semiconductor substrate 20 on both sides of the mesa stripe 21. The growth layer 22 is separated on the surface of the mesa stripe 21 {}
A stripe structure 23 having an isosceles triangular cross section, which is limited by a surface corresponding to the surface (B surface), is formed. Furthermore,
It has been experimentally confirmed that the crystal growth rate on the {} plane (B plane) is extremely smaller than the crystal growth rate on other planes. The present invention was created based on such technical matters.
[作用] 本発明に係る半導体発光装置によれば、活性層を含むメ
サストライプ構造23の部分が一回の連続的な結晶成長に
よって形成され、かつ、埋込まれているので、活性層端
部及びその近傍に結晶欠陥や不純物の蓄積が見られず、
結晶欠陥等に付随する界面準位に関与した注入キャリア
の非発光再結合を防止して、高い発光効率を得ることが
できる。また、長期に亘って高い信頼性を発揮できるも
のである。[Operation] According to the semiconductor light emitting device of the present invention, since the portion of the mesa stripe structure 23 including the active layer is formed and embedded by one continuous crystal growth, the active layer edge portion is formed. And no accumulation of crystal defects and impurities in the vicinity,
It is possible to prevent non-radiative recombination of the injected carriers associated with the interface states associated with crystal defects and to obtain high luminous efficiency. In addition, it can exhibit high reliability for a long period of time.
また、本発明方法によれば、エッチング処理に不要して
メサストライプ構造23の部分を形成することができる。
しかも、一連の一回の結晶成長処理にてメサストライプ
構造23及びその埋込層を形成することができる。更にメ
サストライプ構造23の形成をMO−CVD法等の結晶成長法
にて行うことができる。このため量産性を向上させるこ
とができる。その結果、上記半導体発光装置を高い歩留
りで容易に得ることができる。Further, according to the method of the present invention, the portion of the mesa stripe structure 23 can be formed without being necessary for the etching process.
Moreover, the mesa stripe structure 23 and its embedded layer can be formed by a series of one-time crystal growth processes. Further, the mesa stripe structure 23 can be formed by a crystal growth method such as MO-CVD method. Therefore, mass productivity can be improved. As a result, the semiconductor light emitting device can be easily obtained with a high yield.
[実施例] 以下、本発明の実施例について図面を参照して説明す
る。なお、本発明の一実施例の半導体発光装置の構造の
説明は、本発明方法の以下に述べる工程順に従った説明
をもってその説明に代える。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. The description of the structure of the semiconductor light emitting device of one embodiment of the present invention will be replaced with the description of the method of the present invention in the order of the steps described below.
先ず、第1図(A)に示す如く、例えばn形GaAs基板30
の(100)面上に、<110>方向と平行なストライプ状の
SiO2膜31をフォトリソグラフィ法にて形成する。First, as shown in FIG. 1A, for example, an n-type GaAs substrate 30
On the (100) plane of the stripes parallel to the <110> direction
The SiO 2 film 31 is formed by the photolithography method.
次に、第1図(B)に示す如く、SiO2膜31をマスクにし
てGaAs基板30に選択エッチングを施し、GaAs基板30の主
面に筋状に突出したメサストライプ32を形成する。Next, as shown in FIG. 1B, the GaAs substrate 30 is subjected to selective etching using the SiO 2 film 31 as a mask to form a mesa stripe 32 protruding in a stripe shape on the main surface of the GaAs substrate 30.
次に、第1図(C)に示す如く、SiO2膜31を除去した
後、メサストライプ32を含むGaAs基板30上にMO−CVD法
により結晶成長処理を施す。この結晶成長処理によって
メサストライプ32上には、n型Ga0.7Al0.3Asクラッド層
33,ノンドープGaAs活性層34,p型Ga0.7Al0.3Asクラッド
層35を順次積層してなるストライプ状のダブルヘテロ構
造36が形成される。ストライプ状のダブルヘテロ構造36
は、結晶成長が{}面(B面)によって制限され
極めて遅い結晶成長となるため、断面が二等辺三角形状
のものとなる。また、ストライプ状のダブルヘテロ構造
36の形成と同時にメサストライプ32を挟むGaAs基板30の
主面((100)面)上には、n型Ga0.7Al0.3As層33′,
ノンドープGaAs層34′,p型Ga0.7Al0.3Asクラッド層35′
が順次積層される。ここで、p型Ga0.7Al0.3Asクラッド
層35′がメサストライプ32上のp型Ga0.7Al0.3Asクラッ
ド層35に接触しないように、予めメサストライプ32の高
さ(t1)及びn型Ga0.7Al0.3Asクラッド層33等の厚さを
所定のものに設定しておく。このような各層33…35,3
3′…35′の厚さ制御は、MO−CVD法によれば極めて容易
にできるものである。Next, as shown in FIG. 1C, after the SiO 2 film 31 is removed, a crystal growth process is performed on the GaAs substrate 30 including the mesa stripes 32 by the MO-CVD method. The n-type Ga 0.7 Al 0.3 As clad layer is formed on the mesa stripe 32 by this crystal growth process.
A striped double heterostructure 36 is formed by sequentially stacking 33, the non-doped GaAs active layer 34, and the p-type Ga 0.7 Al 0.3 As cladding layer 35. Striped double heterostructure 36
The crystal growth is extremely slow because the crystal growth is limited by the {} plane (B plane), so that the cross section has an isosceles triangular shape. Also, a striped double heterostructure
At the same time as the formation of 36, the n-type Ga 0.7 Al 0.3 As layer 33 ′, on the main surface ((100) surface) of the GaAs substrate 30 sandwiching the mesa stripe 32,
Non-doped GaAs layer 34 ', p-type Ga 0.7 Al 0.3 As clad layer 35'
Are sequentially stacked. Here, as the p-type Ga 0.7 Al 0.3 As cladding layer 35 'does not contact the p-type Ga 0.7 Al 0.3 As cladding layer 35 on the mesa stripe 32, advance the height of the mesa stripe 32 (t 1) and the n-type Ga 0.7 Al 0.3 As The thickness of the cladding layer 33 and the like is set to a predetermined value. Each layer 33… 35,3
The thickness control of 3 '... 35' can be extremely easily performed by the MO-CVD method.
次に、第1図(D)に示す如く、上述のMO−CVD法によ
る結晶成長処理を所定の反応ガスを用いて上述のものと
連続して行い、ストライプ状のダブルヘテロ構造36のノ
ンドープGaAs活性層34を完全に埋込むノンドープGa0.7A
l0.3As埋込層37をp型Ga0.7Al0.3Asクラッド層35上に積
層する。次いで、ノンドープGa0.7Al0.3As埋込層37上に
p型キャップ層38を形成する。Next, as shown in FIG. 1 (D), the crystal growth treatment by the MO-CVD method described above is continuously performed using the specified reaction gas, and the striped double hetero structure 36 of the non-doped GaAs is subjected to the above-mentioned process. Non-doped Ga 0.7 A that completely fills the active layer 34
A 0.3 As buried layer 37 is laminated on the p-type Ga 0.7 Al 0.3 As cladding layer 35. Next, the p-type cap layer 38 is formed on the non-doped Ga 0.7 Al 0.3 As embedded layer 37.
然る後、第1図(E)に示す如く、p型キャップ層38上
にp型電極39を蒸着形成すると共に、GaAs基板30の裏面
側にn型電極40を形成して半導体発光装置45を得る。Then, as shown in FIG. 1E, the p-type electrode 39 is formed on the p-type cap layer 38 by vapor deposition, and the n-type electrode 40 is formed on the back surface of the GaAs substrate 30 to form the semiconductor light emitting device 45. To get
このように構成された半導体発光素子45によれば、その
両側面が{}B面である活性層を含むダブルヘテ
ロ構造36が、一回の連続的な結晶成長処理によりメサス
トライプ32上に形成されているので、ノンドープ活性層
34の端部及びその近傍に結晶欠陥や不純物の蓄積がな
く、長時間に亘って優れた組成特性を発揮することがで
きる。According to the semiconductor light emitting device 45 having such a structure, the double heterostructure 36 including the active layer having {} B planes on both sides is formed on the mesa stripe 32 by one continuous crystal growth process. Since it is a non-doped active layer
Crystal defects and impurities do not accumulate at the edge of 34 and its vicinity, and excellent composition characteristics can be exhibited for a long time.
また、上述の半導体発光装置の製造方法によれば、スト
ライプ状のダブルヘテロ構造36の形成に際してエッチン
グ処理が不要で、しかも、一連の一回の結晶成長処理に
よってストライプ構造36の形成及びその埋込層37,キャ
ップ層38を形成できると共に、MO−CVD法による結晶成
長処理を採用できるので、優れた素子特性を長時間に亘
って発揮することができる半導体発光装置45を高い歩留
りで容易に得ることができる。According to the method for manufacturing a semiconductor light emitting device described above, an etching process is not required when forming the stripe-shaped double hetero structure 36, and furthermore, the stripe structure 36 is formed and embedded by a series of single crystal growth processes. Since the layer 37 and the cap layer 38 can be formed and the crystal growth process by the MO-CVD method can be adopted, the semiconductor light emitting device 45 capable of exhibiting excellent element characteristics for a long time can be easily obtained with a high yield. be able to.
以上説明した図1に示す実施例に係る半導体発光装置で
は、メサストライプ32の上に、n型クラッド層33、活性
層34、p型クラッド層34が順次形成され、これらの積層
からなるメサストライプ構造36は、略2等辺三角形の断
面を有する。そして、このメサストライプ構造36を有す
る構造の上に埋込層(電流阻止層)37を堆積すると、成
長はメサストライプ構造36の側面に沿って進行し、メサ
ストライプ構造36の構造上、その頂部に成長することは
ない。In the semiconductor light emitting device according to the embodiment shown in FIG. 1 described above, the n-type clad layer 33, the active layer 34, and the p-type clad layer 34 are sequentially formed on the mesa stripe 32, and a mesa stripe formed by stacking these layers is formed. The structure 36 has a cross section of a substantially isosceles triangle. When a buried layer (current blocking layer) 37 is deposited on the structure having the mesa stripe structure 36, the growth proceeds along the side surface of the mesa stripe structure 36, and the top of the mesa stripe structure 36 is formed. Never grow to.
これに対し、メサストライプ構造36が2等辺三角形では
なく、台形状の場合には、台形の上辺に相当する頂部に
おいて容易に成長が行われ、活性層への電流を妨げてし
まう。これを防止するため、埋込層(電流阻止層)37の
堆積前にあらかじめ基板にZnを拡散することが考えられ
るが、工程の増加につながり、好ましくない。On the other hand, when the mesa stripe structure 36 is not an isosceles triangle but a trapezoidal shape, growth easily occurs at the apex corresponding to the upper side of the trapezoid, which hinders current flow to the active layer. In order to prevent this, Zn may be diffused into the substrate in advance before the buried layer (current blocking layer) 37 is deposited, but this is not preferable because it leads to an increase in the number of steps.
第2図は、ノンドープGa0.7Al0.3As埋込層37をp型Ga
0.7Al0.3As埋込層46にn型Ga0.7Al0.3As埋込層47を積層
して二重構造にした他の実施例を示すものである。ここ
で、p型Ga0.7Al0.3As層35′とp型Ga0.7Al0.3As埋込層
46は、必ずしも同一組成、同一キャリヤ濃度である必要
はない。また、埋込層46,47以外の部分は、上記実施例
のものと同様の構造を有している。Fig. 2 shows the non-doped Ga 0.7 Al 0.3 As buried layer 37 with p-type Ga.
7 shows another embodiment in which an n-type Ga 0.7 Al 0.3 As embedded layer 47 is laminated on a 0.7 Al 0.3 As embedded layer 46 to form a double structure. Here, the p-type Ga 0.7 Al 0.3 As layer 35 'and the p-type Ga 0.7 Al 0.3 As buried layer
46 does not necessarily have the same composition and the same carrier concentration. The portions other than the buried layers 46 and 47 have the same structure as that of the above-mentioned embodiment.
なお、実施例ではn型GaAs基板30を採用したものについ
て説明したが、p型の基板を採用しても良いことは勿論
である。In the embodiment, the n-type GaAs substrate 30 is used, but it goes without saying that a p-type substrate may be used.
また、活性層34もノンドープGaAs層の他にp型GaAs,n型
GaAs層で形成しても良いことは勿論である。更に、活性
層を量子井戸構造としても良い。In addition to the non-doped GaAs layer, the active layer 34 includes p-type GaAs and n-type
Of course, it may be formed of a GaAs layer. Furthermore, the active layer may have a quantum well structure.
また、結晶成長処理は、MO−CVD法の他にもVPE(Vapor
Phase Epitaxy)法やMBE(Molecular Beam Epitaxy)法
を採用しても良い。In addition to the MO-CVD method, the crystal growth process is performed by VPE (Vapor
The Phase Epitaxy method or MBE (Molecular Beam Epitaxy) method may be adopted.
また、実施例ではGaAs/GaAlAs系の半導体発光装置につ
いて説明したがInP/InGaAsP系の半導体発光装置にも適
用できることは勿論である。Further, in the embodiment, the GaAs / GaAlAs based semiconductor light emitting device has been described, but it is needless to say that the present invention can be applied to an InP / InGaAsP based semiconductor light emitting device.
[発明の効果] 以上説明した如く、本発明に係る半導体発光装置及びそ
の製造方法によれば、活性層部分のエッチング処理を不
要にして、一度で一連の結晶成長処理によって活性層を
埋込む埋込層までの形成が可能であり、長期に亘って高
い信頼性を発揮する半導体発光装置を容易に得ることが
できる。更に本発明方法によれば、MO−CVD法等の結晶
成長処理を採用できるので、上述の半導体発光装置を高
い歩留りで量産することができるものである。[Effects of the Invention] As described above, according to the semiconductor light emitting device and the method for manufacturing the same according to the present invention, it is possible to embed the active layer by performing a series of crystal growth processes at once without the need for etching the active layer portion. It is possible to form up to the embedded layer, and it is possible to easily obtain a semiconductor light emitting device that exhibits high reliability for a long period of time. Further, according to the method of the present invention, crystal growth treatment such as MO-CVD method can be adopted, so that the above-mentioned semiconductor light emitting device can be mass-produced with high yield.
第1図は、本発明の実施例の半導体発光装置をその工程
順に示す説明図、第2図は、本発明に係る半導体発光装
置の他の実施例の概略構成を示す説明図、第3図は、本
発明の重要な構成を示す説明図、第4図は、従来の半導
体発光装置の概略構成を示す説明図、第5図は、同従来
の半導体発光装置の製造方法を工程順に示す説明図であ
る。 20……半導体基板、21……メサストライプ、22……成長
層、23……メサストライプ構造、30……GaAs基板、31…
…SiO2膜、32……メサストライプ、33,33′……n型Ga
0.7Al0.3Asクラッド層、34……ノンドープGaAs活性層、
35,35′……p型Ga0.7Al0.3Asクラッド層、36……スト
ライプ状のダブルヘテロ構造、37……ノンドープGa0.7A
l0.3As埋込層、38……キャップ層、39……p型電極、40
……n型電極、45……半導体発光装置、46……P型Ga
0.7Al0.3As埋込層、47……n型Ga0.7Al0.3As埋込層。FIG. 1 is an explanatory view showing a semiconductor light emitting device of an embodiment of the present invention in the order of steps, FIG. 2 is an explanatory view showing a schematic configuration of another embodiment of the semiconductor light emitting device according to the present invention, and FIG. FIG. 4 is an explanatory diagram showing an important configuration of the present invention, FIG. 4 is an explanatory diagram showing a schematic configuration of a conventional semiconductor light emitting device, and FIG. It is a figure. 20 ... Semiconductor substrate, 21 ... Mesa stripe, 22 ... Growth layer, 23 ... Mesa stripe structure, 30 ... GaAs substrate, 31 ...
… SiO 2 film, 32 …… Mesa stripe, 33,33 ′ …… n-type Ga
0.7 Al 0.3 As clad layer, 34 ... Non-doped GaAs active layer,
35,35 '…… p-type Ga 0.7 Al 0.3 As cladding layer, 36 …… Striped double heterostructure, 37 …… Undoped Ga 0.7 A
l 0.3 As Buried layer, 38 …… Cap layer, 39 …… P-type electrode, 40
... n-type electrode, 45 ... semiconductor light-emitting device, 46 ... P-type Ga
0.7 Al 0.3 As buried layer, 47 ... n-type Ga 0.7 Al 0.3 As buried layer.
Claims (4)
れと等価な結晶軸方向に略平行に筋状に突出したメサス
トライプと、該メサストライプ上に積層され、両側面が
{}B面である活性層を含むダブルヘテロ構造
と、前記メサストライプを除く前記半導体基板の露出し
た主面上に該ダブルヘテロ構造を埋込むように形成さ
れ、該活性層よりも屈折率が小さく、かつ、禁則帯幅の
大きい半導体層とを具備することを特徴とする半導体発
光装置。1. A mesa stripe projecting in a streak shape on a main surface of a semiconductor substrate in a direction substantially parallel to a <110> direction or a crystal axis direction equivalent to the <110> direction, and stacked on the mesa stripe. A double heterostructure including an active layer which is a surface, and a double heterostructure formed so as to be embedded on the exposed main surface of the semiconductor substrate excluding the mesa stripe, and having a smaller refractive index than the active layer, and And a semiconductor layer having a large forbidden band width.
}B面である断面二等辺三角形形状である特許請求の
範囲第1項記載の半導体発光装置。2. The double hetero structure has a double-sided surface {
The semiconductor light emitting device according to claim 1, which has an isosceles triangular cross-section that is a B plane.
れと等価な結晶軸方向に略平行に筋状に突出したメサス
トライプを形成する工程と、該メサストライプ上に両側
面が{}B面である活性層を含むダブルヘテロ構
造を積層する工程と、前記メサストライプを除く前記半
導体基板の露出した主面上に該ダブルヘテロ構造を埋込
むようにして該活性層よりも屈折率が小さく、かつ、禁
則帯幅の大きい半導体層を前記ダブルヘテロ構造の結晶
成長工程と一連の結晶成長工程で形成する工程とを具備
することを特徴とする半導体発光装置の製造方法。3. A step of forming a mesa stripe projecting in a streak shape substantially parallel to a <110> direction or a crystal axis direction equivalent to the <110> direction on a main surface of a semiconductor substrate, and both side surfaces on the mesa stripe are {}. Stacking a double heterostructure including an active layer which is a B-plane, and having a refractive index smaller than that of the active layer by embedding the double heterostructure on the exposed main surface of the semiconductor substrate except the mesa stripe, A method of manufacturing a semiconductor light emitting device, comprising: a crystal growth step of the double hetero structure and a step of forming a semiconductor layer having a large band gap by a series of crystal growth steps.
法がMO−CVD法である特許請求の範囲第3項記載の半導
体発光装置の製造方法。4. The method for manufacturing a semiconductor light emitting device according to claim 3, wherein the double hetero structure and the crystal growth method of the semiconductor layer are MO-CVD methods.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6872286A JPH0773132B2 (en) | 1986-03-28 | 1986-03-28 | Semiconductor light emitting device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6872286A JPH0773132B2 (en) | 1986-03-28 | 1986-03-28 | Semiconductor light emitting device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62226673A JPS62226673A (en) | 1987-10-05 |
| JPH0773132B2 true JPH0773132B2 (en) | 1995-08-02 |
Family
ID=13381970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6872286A Expired - Fee Related JPH0773132B2 (en) | 1986-03-28 | 1986-03-28 | Semiconductor light emitting device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0773132B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2523643B2 (en) * | 1987-06-03 | 1996-08-14 | 松下電器産業株式会社 | Semiconductor laser device |
| JPH0265288A (en) * | 1988-08-31 | 1990-03-05 | Sony Corp | Semiconductor laser |
| JP3011938B2 (en) * | 1988-12-27 | 2000-02-21 | ソニー株式会社 | Semiconductor laser |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5858831B2 (en) * | 1976-08-31 | 1983-12-27 | 松下電器産業株式会社 | Method for manufacturing semiconductor light emitting device |
| JPS5826834B2 (en) * | 1979-09-28 | 1983-06-06 | 株式会社日立製作所 | semiconductor laser equipment |
-
1986
- 1986-03-28 JP JP6872286A patent/JPH0773132B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62226673A (en) | 1987-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4149175A (en) | Solidstate light-emitting device | |
| US5311533A (en) | Index-guided laser array with select current paths defined by migration-enhanced dopant incorporation and dopant diffusion | |
| JPH01239980A (en) | Semiconductor laser device | |
| JPH0773132B2 (en) | Semiconductor light emitting device and method of manufacturing the same | |
| CA1065461A (en) | Semiconductor light-emitting device and method of making of the same | |
| US6465812B1 (en) | Semiconductor light emitting device | |
| JPH01220492A (en) | Semiconductor laser device and manufacture thereof | |
| JPH0983071A (en) | Semiconductor laser | |
| JPS6381884A (en) | Semiconductor laser device and manufacture of the same | |
| JP3684519B2 (en) | Semiconductor laser manufacturing method | |
| KR970001896B1 (en) | Structure of Semiconductor Laser Diode and Manufacturing Method Thereof | |
| JPH05218585A (en) | Semiconductor light emitting device | |
| KR100363240B1 (en) | Semiconductor laser diode and its manufacturing method | |
| JP2525617B2 (en) | Method for manufacturing semiconductor laser | |
| JPS6318874B2 (en) | ||
| KR100290861B1 (en) | Manufacturing method of semiconductor laser diode | |
| JPH07169993A (en) | Semiconductor structure and semiconductor light emitting device | |
| JPH03190287A (en) | Light-emitting diode array | |
| JP2812187B2 (en) | Manufacturing method of semiconductor laser | |
| JPS6257212A (en) | Manufacture of semiconductor element | |
| JPS63129683A (en) | Manufacture of buried semiconductor laser | |
| JPS6237835B2 (en) | ||
| JPH04260386A (en) | Manufacture of optical semiconductor device | |
| JPH03125491A (en) | Manufacture of semiconductor light emitting element | |
| JPH01117078A (en) | Semiconductor light-emitting device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |