JPH0773171B2 - Complex operational amplifier circuit - Google Patents

Description

The present invention relates to a high-speed and high-accuracy pulse amplifier, and more particularly to a composite operational amplifier circuit formed by synthesizing a plurality of operational amplifiers.

(Prior Art) In recent years, various electron beam exposure apparatuses have been used to form a fine pattern on a sample such as a semiconductor wafer or a mask. This device requires a high-speed and high-precision pulse amplifier in order to deflect the beam at high speed and high precision.

FIG. 9 is a circuit configuration diagram showing an example of a conventional non-inverting amplifier circuit. In the figure, 91 is an operational amplifier, 92 is a resistor R ₁ , and 93 is a resistor R _2.
Is shown. In this circuit, if the input voltage is e ₁ , the output voltage is e ₂ , and the amplification degree of the amplifier 91 is A, the −input voltage e ₇ of the amplifier 91 is e ₇ = R ₁ × e ₁ / (R ₁ + R ₂ ), And the output voltage e ₂ becomes e ₂ = (e ₁ −e ₇ ) A. If you put a _{1 + R 1 / R 2 =} G, the _{e 2 = G {1-G} / (G + A)} e 1. Generally, since G << A, e ₂ = G × e ₁ , but in the case of a highly accurate amplifier such as a deflection amplifier of an electron beam exposure apparatus, the term {1-G / (G + A)} is a problem. . For example, when G = 10, the amplification degree A of the operational amplifier required to obtain 1/2 LSB accuracy of the 16-bit DA converter must be 142 dB or more. There is no high-speed operational amplifier that has this degree of amplification.

On the other hand, in order to achieve high speed and high accuracy, a composite operational amplifier circuit as shown in FIG. 10 has been proposed. With this device,
High-amplitude operational amplifier 94
It is detected by 95 and corrected to the + input of the high speed operational amplifier 94. In the figure, 96, 97 and 98 represent resistors R ₁ , R ₂ and R ₃ , and 99 represents a capacitor C.

However, this circuit has the following problems. That is, when input to the pulse resistor R ₁ , the high speed operational amplifier 94 is delayed by the delay of the high speed operational amplifier 94, as shown in FIG.
A differential waveform is generated at the-input of 94. This differential waveform is integrated by the resistor R ₃ , the capacitor C, and the high-amplification operational amplifier 95, and the + input of the high-speed operational amplifier 94 is changed to increase the output error. Moreover, this error increases depending on the amplitude of the input.

(Problems to be Solved by the Invention) As described above, conventionally, there has been a demand for realization of a high-speed and high-precision amplifier circuit used for a deflection amplifier of an electron beam exposure apparatus. Further, in the complex operational amplifier circuit as shown in FIG. 10, there is a problem that an output error occurs due to the generated differential waveform.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to suppress a differential waveform generated by a delay of a high-speed operational amplifier and enable a high-speed and high-accuracy pulse amplification. To provide.

[Configuration of the Invention] (Means for Solving the Problems) The essence of the present invention is to suppress the generation of the differential waveform by correcting the delay time of the high-speed operational amplifier with the delay circuit.

That is, the present invention provides a composite operational amplifier circuit in which a first operational amplifier that amplifies a large signal at a high speed but has a small DC amplification is combined with a second operational amplifier that amplifies a small signal and has a large DC amplification. , A first resistor R ₁ is connected between the − input terminal and the external input terminal of the first operational amplifier, and between the output terminal and the − input terminal of the second operational amplifier connected to the external output terminal. An inverting amplifier circuit in which a _second resistor R ₂ is connected to the input terminal, a delay circuit whose input end is connected to an external input terminal to correct the delay caused by the first operational amplifier, and an output end of the delay circuit A voltage dividing circuit connected between the output terminal of the operational amplifier and the voltage dividing circuit for dividing the voltage of each output terminal and a second operational amplifier as main components, and integrating the voltage divided by the voltage dividing circuit And an integrating circuit applied to the + input terminal of the operational amplifier of.

(Operation) According to the present invention, the differential waveform generated by the delay of the high speed operational amplifier can be suppressed by the delay circuit and input to the high amplification operational amplifier for error detection. Therefore, it is possible to eliminate the output error caused by the generation of the differential waveform.

(Examples) The details of the present invention will be described below with reference to illustrated examples.

FIG. 1 is a circuit configuration diagram showing a composite operational amplifier circuit according to the first embodiment of the present invention. In the figure, 11 and 12 are operational amplifiers (O
P) and 15 are delay circuits (DL), 16 is an external input terminal, 17 is an external output terminal, 21 to 25 are resistors R ₁ to R ₅ , and 26 is a capacitor C. The first OP11 is a high speed operational amplifier, and the second OP12 is a high amplification operational amplifier.

A resistor R ₁ is provided between the input terminal of the first OP11 and the external input terminal 16.
Is connected to OP11 connected to the external output terminal 17, and the resistor R ₂ is connected between the output terminal and the − input terminal. A delay line is provided between the external input terminal 16 and the external output terminal 17.
DL15, resistors R _3, R ₄ are connected in series. Resistor R _3, the connection point of R ₄ through a resistor R ₅ of the second OP12 - is connected to the input terminal. The + input terminal of OP12 is grounded, and the capacitor C is connected between the − input terminal and the output terminal. And
These OP12, resistors R ₅ and the integrating circuit from the capacitor C is formed, the output of the integration circuit becomes shall be given to the + input of OP11.

The characteristic of OP11 is A (S) = A ₁ / (1 + sT), and the output e _{5 of} OP12 does not change even if e ₁ is added to the input.
When e ₅ = 0, FIG. 1 is equivalent to FIG. A ₁ is OP 11
Is the amplification degree of. Characteristic of the second figure _{(e 1 -e 3) / R} 1 = (e 3 -e 2) / R 2 ... (1) e 2 = -e 3 × A (S) ... (2) A (S) = A ₁ / (1 / sT) (3) Substituting the equations (1) and (3) into the equation (2) and rearranging them, e ₂ =-(R ₂ / R ₁ ) × A ₁ × e ₁ / [1 + A ₁ + (R ₂ / R ₁ ) + {( R ₁ + R ₂ ) / R ₁ } × sT]. Generally, since A ₁ >> ₁ , (R ₂ / R ₁ ), e ₂ = − (R ₂ / R ₁ ) × e ₁ / {1 + sT × (R ₁ + R ₂ ) / (R ₁ ×
A ₁ )} becomes (4), and the step response of the equation (4) becomes e ₂ = − (R ₂ / R ₁ ) × (e ₁ / s) / (1 + sT ₁ ). However, since T ₁ = (R ₁ + R ₂ ) × T / (R ₁ × A ₁ ), e ₂ = − (R ₂ / R ₁ ) {1-exp (−t / T ₁ )} e ₁ ... (5)

FIG. 3 is a circuit diagram for explaining the correction of the output e ₂ .
E ₂ when the input step voltage to the input e ₁ (waveform determined by Equation (5)), the waveform of the output e ₅ of e _4, OP12 shown in Figure 4.
e _4, e ₅ of the delay time of the DL15 in the solid line in waveform is zero, and the broken line DL15
This is the waveform when the delay time is 1.1 × T ₁ (the time when the integrated value of the transient waveform of e ₄ becomes zero is 1.1 × T ₁ ). Ideally, the output e ₅ of the OP 12 does not respond during such a transient period. Therefore, set to the delay time of the DL15 output e ₅ of OP12 unchanged. That is, the delay time of DL15 is 1.1 × T
Set to ₁ . Note that (R ₄ / R ₃ = R ₂ / R ₁ ).

With this setting, return to Fig. 1 and output e of OP12
₅ becomes irrelevant to the transient period of input e ₁ and output e ₂ of OP11, and O
The drift and thermal tail of P11 will be improved.

Thus, according to this embodiment, the output e ₅ of OP12 input e _1, OP1
It becomes irrelevant to the transient period of output e ₂ of 1 and can improve the drift and thermal tail of OP 11. Furthermore, OP11
The high-speed characteristic is not impaired, and high-accuracy and high-speed pulse amplification operation can be realized. Therefore, it is extremely effective as a deflection amplifier in an electron beam exposure apparatus.

In the above embodiments, the OP11 as shown in Figure 5 - the resistance to the input terminal 27 (R ₆₎ and capacitor 28 (C ') may be added. It is also possible to use a non-inverting amplifier circuit instead of DL15.

FIG. 6 is a circuit configuration diagram showing a non-inverting composite operational amplifier circuit according to the second embodiment of the present invention. In the figure, 61, 62 and 63 are operational amplifiers (OP), 64 is an integrating circuit, 65 is a delay circuit (DL), 66
Is an external input terminal, 67 is an external output terminal, and 71, ...,
Reference numeral 77 is resistors R ₁ , ..., R ₇ , and 78 is a capacitor C. First OP
A high-speed operational amplifier 61 constitutes a non-inverting amplifier circuit. The second OP62 constitutes a low frequency subtraction circuit, and the third OP63
Is an integrator circuit.

The + input terminal of the first OP 61 is connected to the external input terminal 66, and the output terminal is connected to the external output terminal 67. Furthermore, OP61
The − input terminal of is connected to the resistor R ₁ and is connected to the + output terminal via the resistor R ₂ . A non-inverting amplifier circuit is formed from the OP 61 and the resistors R ₁ and R ₂ . External input terminal 66 is connected to DL65 made from the delay line, the output terminal of the DL65 resistors R _6, R
Grounded via ₅ in series. The output terminal of OP61 is a resistor R
_It is connected to the-input terminal of the second OP62 via
The input end is connected to the output end of OP62 via a resistor R ₃ . The + input terminal of OP12 is connected to the connection point of resistors R ₅ and R ₆ . Output of OP62 third OP63 through a resistor R ₇ - is connected to the input terminal, the OP63 - input terminal is connected to the output of OP63 through the capacitor C. The + input terminal of OP63 is grounded, and the output terminal is connected to the resistor R ₁ .

In the configuration of FIG. 6, when the output e ₄ of the integrating circuit 64 is 0,
The relationship between the input voltage e ₁ and the output voltage e ₂ is 1 + R ₁ / R ₂ = G and e ₂ = G {1-G / (G + A ₁ )} e ₁ (6). A ₁ is the amplification degree of OP61. The error voltage e _E of the output voltage e ₂ is e _E = −G × G × e ₁ / (G + A ₁ ), and the relationship among the resistors R ₁ , R ₂ , R ₃ , R ₄ , R ₅ , and R ₆ is 1 + R ₄ / R ₃ = (R ₁ + R ₂ ) (R ₅ + R ₆ ) / (R ₁ + R ₅ ), OP62 output voltage e ₃ is e ₃ = R ₃ × G × G × e ₁ / { R ₄ (G + A ₁ )}, and the output voltage e ₃ is input to the integrating circuit 64 including the resistor R ₇ , the capacitance C, and the OP 63. When the OP63 output voltage e ₄ is e ₄ =-(R ₁ + R ₂ ) (R ₁ + R ₂ ) × e ₁ / (A ₁ × R ₁ × R ₂ ), the output voltage e ₂ is e ₂ = G × It becomes e ₁ , which is an ideal expression equivalent to the case of A ₁ = ∞.

Here, the calculation method of the _{e 4, (e 4 -e 7} ) / R 1 = (e 7 -e 2) / R 2 ... (7) e 2 = (e 1 -e 7) × A 1 ... (8) From equations (7) and (8), e ₂ = G × e ₁ −G × G × e ₁ / (G + A ₁ ) −A ₁ × R ₂ × e ₄ / (R ₁ + R ₂ + A ₁ + R ₁ ) (9) e ₄ such that the 2nd and 3rd terms of the equation (9) become zero is e ₄ =-(R ₁ + R ₂ ) (R ₁ + R ₂ ) × e ₁ / (A ₁ × R ₁ × R ₂ )… (1
0). That is, if there is an error in the output voltage e ₂ , the error is
It is detected by 62, integrated by the integrating circuit 64, and fed back at the output of the integrating circuit 64. This feedback is performed until the expression (10) is satisfied.

When a stepped signal is input to the input voltage e ₁ , and the output voltage e ₂ is generated after Td time from this input signal,
The DL65 delays the input by the delay time Td, and the error detection OP62
Match the + and-input phases of. By matching the phases, unnecessary signals are cut during the transient period when the input voltage e ₁ changes. That is, the above DC analysis can be applied as it is by adjusting the phases of the + input and the-input of the error detection OP62.

If there is no DL65 and the phase of the + input and-input of the OP62 for error detection is not aligned, the waveform shown in FIG. 7 is obtained.
By not aligning the + and-input phases of OP62,
The output voltage e ₃ generates a differential waveform and is input to the integrating circuit 64, and the output e ₄ of the integrating circuit 64 generates an unnecessary output.

Thus, according to the present embodiment, the OP62 for error detection receives an input,
By removing unnecessary signals in the transient period due to output,
It is possible to improve the OP61's lack of amplification, drift, and thermal tail. The high speed of OP61 is not impaired,
High-accuracy and high-speed pulse amplification becomes possible. Therefore,
It is extremely effective as a deflection amplifier for an electron beam exposure apparatus.

In the second embodiment, the resistors R ₅ , R ₆ and OP62
It is also possible to add a capacitor C ′ to the connection point of the + input end of the OP 62 to match the phase of the + input and the − input of the OP 62. Further, as shown in FIG. 8, it is possible to divide the resistor R ₆ into a plurality of pieces, add a capacitance to each division point, and omit the delay circuit.

Further, the present invention is not limited to the above-mentioned embodiments. For example, in the first embodiment, the resistor R ₃ may be divided into a plurality of pieces, and the capacitance may be connected between each division point and the ground terminal. Similarly, the resistor R ₄ may be divided into a plurality of pieces, and a capacitance may be connected between each division point and the ground terminal. Further, the capacitor connected between the dividing point and the ground terminal may be replaced with a varactor diode, and the capacitance value may be controlled by the voltage. Also in the second embodiment, the resistor R ₄ may be divided into a plurality of pieces, and the capacitance may be connected between each division point and the ground terminal. In addition, various modifications can be made without departing from the scope of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, the differential waveform generated by the delay of the high-speed operational amplifier is suppressed to enable high-speed and high-accuracy pulse amplification, and the deflection amplifier of the electron beam exposure apparatus, etc. It is possible to realize a composite operational amplifier circuit that is excellent for use as.

[Brief description of drawings]

1 is a circuit configuration diagram showing a composite operational amplifier circuit according to a first embodiment of the present invention, FIG. 2 is a diagram showing a circuit configuration of the high speed operational amplifier of FIG. 1, and FIG. 3 is FIG. Showing the circuit configuration of the high-precision operational amplifier of FIG. 4, FIG. 4 is a signal waveform diagram showing the waveform of each part in FIG. 3, FIG. 5 is a circuit configuration diagram showing a modification of the first embodiment, and FIG. Is a circuit configuration diagram showing a non-inverting composite operational amplifier circuit according to a second embodiment of the present invention,
FIG. 8 is a signal waveform diagram showing the waveform of each part when there is no phase matching between the + input and the − input of the operational amplifier for error detection, and FIG. 8 is a circuit configuration diagram showing a modified example of the second embodiment. FIGS. 1 to 11 are each for explaining the conventional problems, FIGS. 9 and 10 are circuit configuration diagrams, and FIG. 11 is a signal waveform diagram. 11,61 ... First operational amplifier, 12,62 ... Second operational amplifier, 63 ... Second operational amplifier, 15,65 ... Delay circuit, 16,
66 …… External input terminal, 17,67 …… External output terminal, 21, ..., 2
5,27,71, ~, 77 …… Resistance, 26,28,78,79 …… Capacitor.

Claims (8)

[Claims] 1. A composite operational amplifier circuit in which a first operational amplifier having a high direct current amplification degree for amplifying a large signal and a small direct current amplification degree is combined with a second operational amplifier having a large direct current amplification degree for amplifying a small signal. , A first resistor R ₁ is connected between the − input terminal and the external input terminal of the first operational amplifier, and between the output terminal and the − input terminal of the first operational amplifier connected to the external output terminal. An inverting amplifier circuit formed by connecting a _second resistor R ₂ to the input terminal, a delay circuit having an input terminal connected to an external input terminal to correct a delay caused by the inverting amplifier circuit, an output terminal of the delay circuit, and a first calculation A voltage divider circuit that is connected between the output terminal of the amplifier and divides the voltage of each output terminal and a second operational amplifier are the main components, and the voltage divided by the voltage divider circuit is integrated to perform the first operation. A compound performance characterized by comprising an integrating circuit applied to the + input terminal of the amplifier. Amplifier circuit. 2. The voltage dividing circuit connects a third resistor R ₃ connected to the output end of the delay circuit and a fourth resistor R ₄ connected to the output end of the first operational amplifier. The compound operational amplifier circuit according to claim 1, wherein 3. The composite operational amplifier circuit according to claim ₂ , wherein the resistors R _{1 to} R ₄ have a relationship of R ₂ / R ₁ = R ₄ / R ₃ . 4. The composite operational amplifier circuit according to claim 2, wherein the resistor R ₃ is divided into a plurality of parts, and capacitors are respectively connected between the respective division points and the ground terminal. 5. The composite operational amplifier circuit according to claim 2, wherein the resistor R ₄ is divided into a plurality of pieces, and a capacitor is connected between each divided point and the ground terminal. 6. The capacitor according to claim 4, wherein the capacitor connected between the dividing point and the ground terminal is replaced by a varactor diode, and the capacitance value is controlled by a voltage. Complex operational amplifier circuit. 7. The integrator circuit grounds the + input terminal of the second operational amplifier, connects a fifth resistor to the − input terminal, and connects a capacitor C between the − input terminal and the output terminal. The composite operational amplifier circuit according to claim 1, characterized in that 8. The composite operational amplifier circuit according to claim 1, wherein a delay line is used for the delay circuit.