JPH0773192B2 - Signal processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a device for converting a signal such as a video signal into a signal having a desired frequency characteristic, and particularly to S / N and waveform distortion of a signal in a transmission system. The present invention relates to a signal processing method and apparatus suitable for improving the signal.

[Conventional technology]

In a recording / reproducing apparatus such as a video tape recorder or a video disc player for recording / reproducing a video signal, or a signal transmission medium such as a satellite broadcast, a method of frequency-modulating (FM) the video signal and transmitting (or recording / reproducing) is generally used. Is used for. S / of the signal received by such FM transmission system
In order to prevent a decrease in N, a signal processing method that performs so-called pre-emphasis, which emphasizes the high-frequency components of the modulated signal in advance, and suppresses high-frequency components after demodulating the FM signal, that is, performs so-called de-emphasis, has been generally used. ing.

In such a signal processing method, in order to faithfully transmit the signal, the transfer function of the pre-emphasis circuit for emphasizing the high frequency component of the above signal is G ₁ (s). The transfer function of the de-emphasis circuit to suppress
Given G ₂ (s), the following equation must be satisfied invariantly with frequency.

G ₁ (s) × G ₂ (s) = k (1) where S = jω, ω is the angular frequency of the signal, and k is a constant.

If this equation (1) is not satisfied, the transmitted (or recorded / reproduced) signal will have phase distortion and amplitude distortion, and the reproduced signal will be distorted. This (1)
As a pre-emphasis circuit and a de-emphasis circuit that satisfy the equation, their transfer functions are Since the circuit network given by can be easily and economically realized by resistors and capacitors, it has been widely used.

However, this conventional method does not consider the phase characteristics of the emphasis circuit and the de-emphasis circuit.

Regarding the method for improving the phase characteristic of the emphasis circuit, Japanese Patent Laid-Open Nos. 53-131814, 53-131815 and 61-61
The method described in 8632 is well known, but these are described in (1) above.
Sufficient consideration was not given to the de-emphasis method that satisfies the formula.

The methods described in JP-A-59-221126 and JP-A-60-7279 are well known as methods for improving the S / N of a signal by using the emphasis circuit represented by the above formula (2). However, no consideration was given to the linearity of the phase characteristic of the emphasis circuit itself of the equation (2).

[Problems to be solved by the invention]

In the above conventional method, as is apparent from the above equation (2), the linearity of the phase characteristic of the emphasis circuit is poor, so that if the above-mentioned pre-emphasis is applied to a signal having a rectangular pulse, for example, one of rising and falling of the signal will occur. A large level of overshoot and undershoot occurs only in the direction, and if frequency modulation is performed using this as a modulation signal, the amount of frequency deviation increases by that amount, and the FM signal occupied band increases, resulting in a wider transmission band. There is a necessary problem. In the recording / reproducing apparatus such as the video tape recorder and the video disc player, the signal band that can be recorded on the medium is naturally limited. In the above conventional pre-emphasis method, a large peak waveform in one direction is generated with respect to the high frequency components of the signal, so that the instantaneous frequency of the FM signal becomes extremely high against overshoot and the high frequency due to the band limitation of the medium. Can no longer reproduce the signal at a sufficient level,
A so-called reversal phenomenon (black horizontal noise is generated in the contour portion of the video signal changing from black to white) occurs, and the instantaneous frequency of the FM signal is drastically reduced due to undershoot, causing so-called spectrum folding. Beat-like noise is generated in the image contour portion, and reproduction image quality is significantly deteriorated. In order to prevent this, it is common to configure to forcibly clip (amplitude limit) the overshoot waveform and undershoot waveform of the signal after emphasis.
This waveform clip loses some of the signal, so
The above equation (1) no longer holds, and there is a problem that the reproduced waveform is greatly distorted. In order to prevent this, a method of reducing the amount of emphasis or the amount of frequency shift is also commonly used. However, although the waveform distortion is improved, as a matter of course, the essential problem that the S / N deteriorates by that amount remains.

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, to satisfy the above equation (1), to have good linearity of phase characteristics, to prevent amplitude distortion and phase distortion, and to increase the amount of emphasis. It is to provide an emphasis circuit and a de-emphasis circuit that can improve the S / N of a signal.

[Means for solving problems]

In order to achieve the above object, the present invention configures a ladder network with an inductance L and a capacitance C, so that a hyperbolic tangent function with respect to an angular frequency ω (S = jω) is obtained.
Focusing on the realization of an impedance circuit Z and an admittance circuit Y having tanh (ST) (T is a delay time),
This impedance circuit Z or admittance circuit Y
, The amplitude characteristic is the function of angular frequency ω 1 / (1 + K ₁ · co
s ² (ωT)) or (1 + K ₂ · sin ² (ωT)) (K ₁ , K
₂ is a constant) and constitutes a pre-emphasis circuit having a linear phase characteristic (that is, a flat group delay characteristic). Similarly, the impedance circuit Z or the admittance circuit Y is used to set the amplitude characteristic of the pre-emphasis circuit. Inverse function of amplitude characteristic (1 + K ₁ · cos ² (ωT)) or 1 / (1+
The first point is that a de-emphasis circuit having K ₂ · sin ² (ωT)) and a linear phase characteristic is configured to realize a signal processing device that sufficiently satisfies the above expression (1). Characterize.

A second feature of the present invention is that the first pre-emphasis circuit composed of the impedance circuit Z or the admittance circuit Y is added to the function G ₁ expressed by the equation (2).
The second pre-emphasis circuit having (s) is connected in cascade, and the first de-emphasis circuit composed of the impedance circuit Z or the admittance circuit Y is added to the function expressed by the equation (2). The second de-emphasis circuit having G ₂ (S) is connected in cascade.

A third feature of the present invention is that the pre-emphasis circuit or the de-emphasis circuit is configured by a digital filter using digital signal processing means.

[Action]

The amplitude characteristic of the first pre-emphasis circuit is 1 / (1
＋ K ₁・ cos ² (ωT)) or (1 + K ₂・ sin ² (ω
T)), it operates so as to emphasize the level of the mid-range component or high-range component of the input signal, and its phase characteristic is linear, so that the output waveform in which the waveform symmetry of the input signal is maintained is can get. More specifically, with respect to the rectangular pulse signal, pre-shoot and post-shoot are generated in odd symmetry before and after each of the rising edge and the falling edge of the signal with substantially equal peak levels. in this way,
The high-frequency components of the input signal are almost equally distributed as pre-shoots and post-shoots before and after each rising and falling edge of the signal due to the enhancement, and therefore the peak value (peak-to-peak value) is The phase characteristic represented by the equation (2) is significantly smaller than that of the conventional emphasis system, which is not linear. Therefore, in FM transmission, the transmission band can be narrowed, and the inversion phenomenon due to overmodulation and The occurrence of beat noise due to spectrum folding can be suppressed, and the waveform after emphasis need not be forcibly clipped, so that waveform distortion does not occur.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a basic circuit 100 for forming a pre-emphasis circuit or a de-emphasis circuit according to an embodiment of the present invention.

The transfer function F ₀ (s) of this basic circuit 100 is such that the signal supplied to the input terminal 1 is Vi and the signal output from the output terminal 2 is V
₀ is given by the following equation.

However, θ = ST = jωT, and T corresponds to the delay time and is a constant. K is also a constant.

This basic circuit 100 has a transfer function F ₁ (s) represented by the following equation.
And a second basic circuit 20 having a transfer function F ₂ (s) are connected in cascade.

From this, the transfer function F ₀ (s) of the basic circuit 100 is the transfer function F ₀ of the two first and second basic circuits 10 and 20.
It can be expressed by the following equation using ₁ (s) and F ₂ (s).

F ₀ (s) = F ₁ (s) × F ₂ (s) (5) FIG. 2 is a four-terminal circuit network showing an embodiment of the first basic circuit 10. In FIG. 3A, 11 is an impedance circuit Z and 13 is a resistor R ₁ . In FIG.
Reference numeral 14 is a resistor R ₂ and reference numeral 12 is an admittance circuit Y. Both the impedance circuit Z and the admittance circuit Y are two-terminal network networks that approximately realize the hyperbolic tangent function tanhθ, and are given by the following equation with the reference resistance R ₀ .

Two-terminal network for approximating these Z and Y values
11 and 12 are the documents disclosed by the inventor (Japanese Patent Publication No.
-53483), an LC ladder network having the configuration shown in FIG. 3 is known. For reference, in FIGS. 3A and 3B, the respective values of the inductance L and the capacitance C for satisfying the above expression (6) are given by the following expressions. For the impedance Z in FIG. 3 (a), For the admittance Y in FIG. 3 (b), However, n is an integer of 1 or more.

In the four-terminal network 10 of FIG. 2 (a), the transfer function F ₁ (s) of the output voltage V ₂ with respect to the input voltage V ₁ is expressed by the following equation using the equation (6).

From this, if k = R ₀ / R ₁ is satisfied, it matches one of the functions F ₁ (s) in the above equation (4), and this function can be realized. Similarly, in the four-terminal network 10 of FIG. 2 (b), the transfer function F ₁ (s) of the output voltage V ₂ with respect to the input voltage V ₁
Is expressed by the following equation using the above equation (6), Therefore, if k = R ₂ / R ₀ , the function F of the above equation (4) is
This agrees with ₁ (s), which means that this function has been realized.

Next, FIG. 4 shows an embodiment for realizing the other function F ₂ (s) of the equation (4), that is, the second basic circuit 20 of FIG.

In general, regarding the hyperbolic tangent function, tanh (−θ) = − tanh (θ) (11) holds, so the conversion of θ → −θ (that is, S → −S) in the equation (4) is performed. If given, It is clear that Based on this, the embodiment of FIG. 4 equivalently performs the function F ₂ (s) by performing S → −S conversion (so-called time axis conversion) and then filtering by the first basic circuit 10. ) (That is, the second
The basic circuit 20) is realized.

In FIG. 4, 21 is an input terminal for the signal Ei, and 22 is an output terminal for the signal E ₀ processed by the circuit 20. 200
Is a time axis conversion circuit that performs time axis conversion so that the time series of the input signal Ei has a time series in the opposite direction.
The time axis conversion circuit 200 is composed of a memory for buffering the time axis, and outputs the input signal Ei at appropriate unit cycles, for example, the signal Ei.
When a video signal is input as, the unit cycle is sequentially written in the memory at a horizontal scanning cycle of the video signal or a cycle of an integral multiple thereof, or at a field cycle or a frame cycle which is a vertical scanning cycle of the video signal, After the writing is completed, the data is sequentially read out from the memory for each unit time in the order opposite to the writing order. The signal output from the circuit 200 after the time series is converted in the reverse direction by the time base conversion is the first basic signal having the transfer function F ₁ (s) realized in the embodiment shown in FIG. After being filtered by the circuit 10, the time axis conversion circuit 300 again performs time axis conversion in the reverse time series. This time base conversion circuit 30
Similarly to the circuit 200, 0 is composed of a memory for buffering the time axis, and the output signal from the circuit 10 is sequentially written into the memory at each of the unit cycles, and after the writing is completed, the order in the direction opposite to the order of writing is written. Then, the data is sequentially read from the memory and output. Therefore,
The output signal E ₀ from this time axis conversion circuit 300 is the input signal E _0.
It has the same original correct time series as i. Through the above series of signal processing, the conversion of S → −S and the function operation corresponding to F ₁ (−S) are performed, and therefore the above basic circuit
The transfer function from the input terminal 21 to the output terminal 22 of 20 becomes equal to F ₂ (s) as shown in the above equation (12), which means that this function could be realized.

A fifth embodiment of the signal processing circuit 30 using the basic circuit 100 of FIG. 1 which is composed of the first basic circuit 10 and the second basic circuit 20 realized by the above embodiment Shown in the figure.

In the figure, the signal Si input to the terminal 31 is the above (3).
It is input to the basic circuit 100 having the transfer function F ₀ (s) of the equation and also input to the + side input terminal of the adder 34.

The output from the basic circuit 100 is amplified by k ₀ times in the coefficient unit 33 and then supplied to the-side input terminal of the adder 34.
In the adder 34, the input signal Si from the terminal 31 and the output signal from the coefficient unit 33 are subtracted, and the output signal S ₀
Is output to terminal 32.

With the above configuration, the transfer function H ₁ (s) from the input terminal 31 to the output terminal 32 is given by the following equation.

Here, if the coefficient value k ₀ of the coefficient unit 33 is set to k ₀ = 1−k ² (14), the cos ² (ωT) term in the numerator of the above equation (13) disappears and this signal The transfer function H ₁ (s) of the processing circuit 30 is simplified as the following equation.

Alternatively, FIG. 6 shows frequency characteristics of the signal processing circuit 30 shown in FIG. 5 which is determined by the transfer function H ₁ (s).

From this, the signal processing circuit 30 is arranged such that when k = 1, that is, when k <1 (that is, K ₁ > 0 in the above equation (15)), the input signal Si is in the midrange or high range. It operates as a pre-emphasis circuit that emphasizes the component, and when k> 1 (that is, k ₂ > 0 in equation (16) above), as a de-emphasis circuit that suppresses the mid-range or high-range component of the input signal Si. Obviously it works.

Next, FIG. 7 shows a response waveform to the rectangular pulse type input signal Si when the signal processing circuit 30 is operated as a pre-emphasis circuit by setting k <1. In the figure, (a) shows the waveform of the input signal Si, and (b) shows the output signal S _0.
Shows the waveform of. As described above, the response waveform with respect to the rectangular pulse-like signal causes pre-shoot and post-shoot in odd symmetry at almost the same peak level before and after each rising and falling edge of the signal. That is, since the high frequency components of the input signal Si are almost evenly distributed to the preshoot and the postshoot by the enhancement, the peak-to-peak value of the output signal S ₀ is
It is smaller than the conventional emphasis method shown by the above equation (2).

Therefore, in the case of frequency-modulating and transmitting (or recording / reproducing) the signal S ₀ that has been subjected to such signal processing and output,
Since the amount of frequency deviation can be kept small,
The FM signal occupied band can be narrowed, and the restriction of the transmission band can be suppressed. In addition, since overmodulation can be prevented, the occurrence of spurious due to the inversion phenomenon and the spectrum folding can be suppressed, and the waveform need not be forcibly clipped, so that the waveform distortion can be prevented.

Next, by applying the signal processing circuit 30 complementarily, the pre-emphasis characteristic and the de-emphasis characteristic are almost completely matched, and an example of the signal processing circuit 40 capable of correctly restoring the original signal is shown. Is shown in FIG.

FIG. 8 operates as a de-emphasis circuit that suppresses the mid-range or high-range components of the signal.

In the figure, 43 is a squared cosine circuit having an amplitude characteristic approximated by a linear phase characteristic and a raised cosine characteristic, 44 is a coefficient unit, 45 is an adder, and 90 is a delay unit. An embodiment of the raised cosine circuit 43 is shown in FIG. In FIG. 9, 11 is the impedance circuit Z shown in FIG. 3 (a), 12 is the admittance circuit Y shown in FIG. 3 (b), and these are functions of the equation (6). Needless to say, it will be displayed. 15 is for the reference resistance R ₀ ,
A resistor having a value of R _0/2 . The transfer function F ₃ of the output voltage V ₂ with respect to the input voltage V ₁ of the raised cosine circuit 43 shown in FIG.
(S) can be expressed by the following equation using the above equation (6).

In FIG. 8, the input signal Si from the terminal 41 is
It is filtered by the raised cosine circuit 43 having the transfer function F ₃ (s) of the equation (8), and its output is amplified by K ₁ times in the coefficient unit 44. The output of the coefficient unit 44 is supplied to one + side input of the adder 45. On the other hand, the input signal Si from the terminal 41 is delayed by the delay device 90 for a time of 2T. Transfer function D of this delay device 90
As is well known, (s) can be expressed by the following equation.

D (s) = e ^−2TS (19) The output of the delay device 90 is supplied to the other + side input of the adder 45, is added to the output from the coefficient device 44, and its output signal S ₀
Is output to terminal 42.

The transfer function H ₂ (s) from the input terminal 42 to the output terminal 42 of the signal processing circuit 40 is given by the following equation using the equations (18) and (19).

H ₂ (s) = D (s) + K ₁ · F ₃ (s) = [1 + K ₁ · cos ² (ωT)] · e ^-2TS (20) The above signal determined by this transfer function H ₂ (s) Processing circuit
The frequency characteristics of 40 are shown in FIG. From this, it is apparent that the signal processing circuit 40 operates as a de-emphasis circuit that suppresses the mid-range or high-range components of the input signal Si.

Here, the coefficient value K ₁ of the coefficient unit 44 in the signal processing circuit 40 is made to match the value of K _{1 in} the equation (17), and K ₁ > 0 (hence, k <1 from the equation (17)). Using the signal processing circuit 30 of FIG. 5 having the transfer function H ₁ (s) of the above equation (15) and operating as a pre-emphasis circuit, the signal to be transmitted (or to be recorded / reproduced) is Processing circuit 30
After performing pre-emphasis by, it is FM-modulated and transmitted (or recorded), the received signal (or reproduced signal) is FM-demodulated, and then the signal processing circuit 40 performs de-emphasis to obtain the original signal. If the system is configured to restore, the overall transfer characteristic of this transmission system is (15) above.
It is given by the following equation using the equation and equation (20).

H ₁ (s) × H ₂ (s) = e ^-2TS (21) That is, the total transfer characteristic of this system has a constant (2T) delay time and the phase characteristic becomes linear. There is no distortion, and since the amplitude characteristic is constant regardless of the frequency, there is no amplitude distortion at all, and therefore, the signal can be transmitted extremely faithfully without waveform distortion, and according to the above K ₁ value. It is clear that the S / N can be improved by suppressing the noise received on the transmission line according to the amount of emphasis.

The above is an example of the case where the signal processing circuit 30 is applied as a pre-emphasis circuit.Next, the signal processing circuit 30 is used as a de-emphasis circuit, and a signal processing that complementarily operates as a pre-emphasis circuit. circuit
An example of 50 is shown in FIG.

In FIG. 11, 53 is a square sine circuit having a linear phase characteristic and an amplitude characteristic approximated by a square sine characteristic.
Is a coefficient unit, 55 is an adder, and 90 is the same delay unit as 90 in FIG.

An embodiment of the square sine circuit 53 is shown in FIG. In FIG. 12, 11 and 12 are the impedance circuit Z and the admittance circuit Y shown in FIGS. 3 (a) and 3 (b), respectively. Reference numeral 15 is a resistor having a value of R _0/2 with respect to the reference resistor R ₀ . The transfer function F ₄ (s) of the output voltage V ₂ with respect to the input voltage V ₁ of the square sine circuit 53 shown in FIG. 12 can be expressed by the following equation using the equation (6).

In FIG. 11, the input signal Si from the terminal 51 is
It is filtered by the square sine circuit 53 having the transfer function F ₄ (s) of the equation (2), and its output is amplified by K ₂ times in the coefficient unit 54. The output of the coefficient unit 54 is supplied to one-side input of the adder 55. On the other hand, the input signal Si from the terminal 51 is delayed by the delay device 90 for a time of 2T. Transfer function D of this delay device 90
(S) is given by the above equation (19). The output of the delay device 90 is supplied to the other + side input of the adder 55, and the coefficient device 54
And the output signal S ₀ is output to the terminal 52.

The transfer function H ₃ (s) from the input terminal 51 to the output terminal 52 of the signal processing circuit 50 is given by the following equation using the equations (22) and (19).

_{H 3 (s) = D (} s) -K 2 · K 4 (s) = ^{_{[1 + K 2 · sin 2 (}} ωT) ] · e ^-2TS ...... (2
3) The above signal processing circuit determined by this transfer function H ₃ (s)
The frequency characteristics of 50 are shown in FIG.

From this, it is clear that the signal processing circuit 50 operates as a pre-emphasis circuit for emphasizing the mid-range or high-range components of the input signal Si.

Here, the coefficient value K ₂ of the coefficient unit 54 in the signal processing circuit 50 is made to match the value of K _{2 in} the equation (17), and K ₂ > 0 (hence, k> 1 from the equation (17)). Using the signal processing circuit 30 of FIG. 5 which has the transfer function H ₁ (s) of the above equation (16) and operates as a de-emphasis circuit, a signal to be transmitted (or recorded / reproduced) is converted into the signal processing circuit. After performing pre-emphasis by 50, FM modulation is transmitted (or recorded), the received signal (or reproduced signal) is FM demodulated, and then de-emphasis is performed by the signal processing circuit 30 to restore the original signal. If the system is configured to restore, the total transfer characteristics of this transmission system can be calculated by the equation (23) and (1
It is given by the following equation using equation (6).

H ₃ (s) × H ₁ (s) = k ² · e ^-2TS (24) That is, the total transfer characteristic of this system has a constant (2T) delay time, and the phase characteristic becomes linear. , No phase distortion is generated, and the amplitude characteristic is constant regardless of the frequency. Therefore, no amplitude distortion is generated, so that the signal can be transmitted extremely faithfully without waveform distortion, and the above K It is clear that the noise received on the transmission line can be suppressed and the S / N can be improved according to the amount of emphasis according to the value of ₂ .

As described above, the signal processing circuit 30 shown in FIG. 5 and the signal processing circuit 40 shown in FIG. 8 or the signal processing circuit 50 shown in FIG. The de-emphasis characteristics can be matched almost perfectly.

Further, as shown in FIG. 7 above, the waveforms pre-emphasized by these are evenly distributed to the preshoot and the postshoot by the high frequency emphasis of the signal, and the peak-to-peak value of the signal becomes It is smaller than the conventional emphasis method shown by the equation (2). In other words, if the peak-to-peak value of the high-frequency-emphasized signal determined by the conditions such as the bandwidth of the transmission path is considered under a certain condition, the method of the present invention further increases the emphasis amount compared to the conventional method. It becomes possible to increase, and the effect that S / N can be improved accordingly is obtained.

The easiest way to increase the amount of emphasis is to increase the coefficient value K ₁ or K ₂ , but the conventional method having the transfer functions G ₁ (s) and G ₂ (s) of the above equation (2) Known pre-emphasis circuit and de-emphasis circuit may be used together with the signal processing circuit of the present invention. More specifically, when the signal processing circuit 30 shown in FIG. 5 is operated as a pre-emphasis circuit and the signal processing circuit (that is, de-emphasis circuit) 40 shown in FIG. 8 is applied complementarily, , A pre-emphasis circuit having the transfer function G ₁ (s) of the equation (2) is intermittently connected to the signal processing circuit 30 to form a de-emphasis circuit having the transfer function G ₂ (s) of the equation (2). The signal processing circuits 40 are connected in cascade. Similarly, when the signal processing circuit 30 shown in FIG. 5 is operated as a de-emphasis circuit and the signal processing circuit (that is, pre-emphasis circuit) 50 shown in FIG. 11 is complementarily applied, Transfer function G of equation (2) above
A pre-emphasis circuit having ₁ (s) is connected in cascade with the signal processing circuit 50, and the transfer function G of the equation (2) is
_The de-emphasis circuit having ₂ (s) and the signal processing circuit 30 are connected in cascade.

According to the above configuration, if the time constants T ₁ and T ₂ of the above equation (2) are set to relatively large values, the pre-emphasis circuit of _one transfer function G ₁ (s) is mainly used to emphasize the low frequency range of the signal. The signal processing circuit 30 or 50, which operates as a pre-emphasis circuit on the other side, can be mainly used for mid-range or high-range emphasis of the signal.
Therefore, S / N can be improved over a wide frequency range without waveform distortion.

Next, another embodiment of the basic circuit according to the present invention is shown in FIG.

This basic circuit 100 'has a transfer function ▲ F ^' shown by the following equation.
₁ ▼ (s) 3rd basic circuit 10 'and transfer function ▲
A fourth basic circuit 20 ′ having F ^′ ₂ ▼ (s) is connected in cascade.

Therefore, the transfer function ▲ F ^' ₀ ▼ (s) from the input terminal 1 to the output terminal 2 of the basic circuit 100' is given by the following equation.

An embodiment of the third basic circuit 10 'is shown in FIG. First
FIG. 15 (a) is constructed by replacing the impedance circuit Z (11) and the resistor R ₁ (13) of FIG. 2 (a), and its transfer function ▲ F ^′ ₁ ▼ (s) is It is given by the following equation using the above equation (6).

From this, if k = R ₀ / R ₁ , the function of the above equation (25) ▲
This coincides with F ^′ ₁ ▼ (s), which means that this function has been realized.

Similarly, FIG. 15 (b) is constructed by replacing the admittance circuit Y (12) and the resistor R ₂ (14) of FIG. 2 (b), and its transfer function ▲ F ^′ ₁ ▼ ( s) is given by the following equation.

Therefore, if k = R ₂ / R ₀ , the function ▲ F of the above equation (25)
This coincides with ^′ ₁ ▼ (s), which means that this function has been realized.

Next, the other transfer function ▲ F ^′ ₂ ▼ (s) of the above equation (25)
An embodiment of the fourth basic circuit 20 'having the above is shown in FIG. This FIG. 16 is constructed by using the third basic circuit 10 ′ instead of the first basic circuit 10 of FIG. 4, and the time base conversion circuits 200 and 300 of FIG. It is exactly the same as that of FIG. 4 and is designated by the same reference numeral. By the same operation as described in FIG. 4 above, the basic circuit 20 ′ of FIG. 16 performs the conversion of S → −S and the function operation corresponding to ▲ F ^′ ₁ ▼ (−s). becomes, therefore the basic circuit 20 'is the transfer function from the input terminal 21 to the output terminal 22 of the (25) function _{^{▲ F' 2 ▼ (s)}} (= ▲ F '1 ▼
(-S)), which means that this function could be realized.

The third basic circuit 10 'realized by the above embodiment.
FIG. 17 shows an embodiment of a signal processing circuit 30 'using the basic circuit 100' of FIG. 14 which is composed of the above and the fourth basic circuit 20 '.

This FIG. 17 is constructed by using the basic circuit 100 'instead of the basic circuit 100 of FIG. 5, and the other coefficient unit 33 and adder 34 are exactly the same as those of FIG. , Are all denoted by the same reference numerals.

From this, the transfer function ▲ H ^' ₁ ▼ (s) from the input terminal 31 to the output terminal 32 of the signal processing circuit 30' is given by the following equation.

Here, the coefficient value k ₀ of the coefficient unit 33 is , The sin ² (ωT) term in the numerator of the above equation (29) is eliminated, and the transfer function ▲ H ^' ₁ ▼ of the signal processing circuit 30' is eliminated.
(S) is simplified as the following equation.

Or The transfer function ▲ H ^′ ₁ ▼ (s) determines the above 17th
FIG. 18 shows the frequency characteristic of the signal processing circuit 30 'shown in the figure.

As is clear from comparing FIG. 18 with FIG. 6,
The signal processing circuit 30 'has exactly the same basic frequency characteristic as the signal processing circuit 30 except for the value in the DC region (that is, the DC gain).
30 'operates as a pre-emphasis circuit for emphasizing the mid-range or high-range components of the input signal Si when k <1, when k = 1, and when k> 1,
It is clear that it operates as a de-emphasis circuit that suppresses the mid-range and high-range components of Si.

In the above embodiments, the LC ladder circuit network shown in FIG. 3 is used and the analog processing means is used. However, the present invention is not limited to this.
You may make it comprised by what is called a digital filter using a digital processing means.

FIG. 19 shows an embodiment of a digital processing type basic circuit 100D in the case where the basic circuit 100 of FIG. 1 is constituted by a digital filter.

In the figure, 3 is an A / D converter and 4 is a D / A converter.
10D1 and 10D2 are both transfer functions F of the above equation (4)
It is a digital filter that realizes ₁ (s), and corresponds to the first basic circuit 10 in FIG. Both 200D and 300D are memories composed of RAM, etc., and correspond to the time axis conversion circuits 200 and 300 of FIG.
A block 20D shown by a broken line in the figure, which is composed of 200D, a digital filter 10D2 and a memory 300D, corresponds to the second basic circuit 20 of FIG. 1, and the transfer function of this block 20D is F _{2 of the} equation (4). Given in (s).

The input signal Vi from the terminal 1 is sequentially converted into a digital signal at the sampling period T ₀ by the A / D converter 3, and its output is supplied to the digital filter 10D1. The output filtered by the digital filter 10D1 is sequentially written in the memory 200D every unit cycle. The signal written in the memory 200D is sequentially read in every unit cycle in the reverse order of the writing order and output. The signal read from the memory 200D is filtered by the digital filter 10D2.
The output from the digital filter 10D2 is sequentially written in the memory 300D for each unit cycle, and the signals written in the memory 300D are sequentially read for each unit cycle in the reverse order of the writing order. The signals read from the memory 300D are D / A
It is converted into an analog signal by the converter 4 and output to the terminal 2.

Next, FIG. 20 shows an embodiment of the digital filter 10D1 (and 10D2).

As a method of converting an analog filter into a digital filter, a method using so-called bilinear Z conversion of the following equation is known.

By substituting the equation (34) into the transfer function F ₁ (s) of the equation (4), the following equation is obtained.

The embodiment of FIG. 20 has a transfer function equal to F ₁ (z) in the above equation (35).

In the figure, 101 is a terminal to which the digital signal from the A / D converter 3 is input, 110 and 113 are adders and 11
2 and 114 are coefficient units, and 111 is a delay unit. The input signal from the terminal 101 is subtracted by the adder 110 from the output from the coefficient multiplier 112. The output from the adder 110 is delayed by N bits in the delay unit 111 (delayed by 2T in time). The output from the delay unit 111 is amplified m times by the coefficient unit 112, and the output is supplied to the adder 110.

A negative feedback loop is formed by the adder 110, the delay unit 111, and the coefficient unit 112 described above.

The adder 113 outputs the output from the adder 110 and the delay device.
The outputs from 111 are added, and the output is n in the coefficient unit 114.
It is amplified twice. The output from the coefficient unit 114 is supplied to the memory 200D via the terminal 102.

The same circuit as that shown in FIG. 10 is applied to the digital filter 10D2 shown in FIG.

It goes without saying that with the above configuration, the transfer function from the input terminal 1 to the output terminal 2 matches the function F ₀ (s) of the above equation (3).

The embodiment shown in FIG. 20 is based on the transfer function F of the equation (4).
₁ (s) is a digital filter having a shows an embodiment of a digital filter having the above-mentioned (25) of the transfer function ▲ F _^'1 ▼ (s) in the same manner as in FIG. 21.

In FIG. 21, circuits having the same functions and operations as those in FIG. 20 are designated by the same reference numerals.

115 is an adder, 116 is a coefficient unit, the output from the adder 110 and the output from the delay device 111 are subtracted in the adder 115,
The output is amplified by the coefficient multiplier 116 by n ′ times.

The transfer function ▲ F ^′ ₁ ▼ (z) from the input terminal 101 to the output terminal 102 in FIG. 21 is given by the following equation.

Equation (37) above is the transfer function ▲ F ^′ ₁ ▼ of Equation (25) above.
It matches the function obtained by substituting the equation (34) into (s).
Therefore, the digital filter shown in FIG.
If applied in place of the digital filters 10D1 and 10D2 shown in FIG. 19, the transfer function from the input terminal 1 to the output terminal 2 matches the function ▲ F ^′ ₀ ▼ (s) of the above equation (26), and
A digital processing basic circuit 100D 'corresponding to the figure can be constructed.

The coefficient unit 114 shown in FIG. 20 and the coefficient unit 116 shown in FIG. 21 can be omitted.

By using the above digital processing type basic circuits 100D and 100D ', a digital processing type signal processing circuit corresponding to FIG. 5 and a digital processing type signal processing circuit corresponding to FIG. 17 can be constructed.

Also, the digital processing type signal processing circuit corresponding to FIGS. 8 and 11 can be easily constructed by using the bilinear conversion of the above expression (34).

〔The invention's effect〕

As described above, according to the present invention, a signal to be transmitted or recorded / reproduced is converted into a signal having a linear phase characteristic and a desired amplitude characteristic, and particularly, the middle or high range of the signal is amplitude-emphasized. The phase characteristic linear pre-emphasis circuit and the de-emphasis circuit which has characteristics opposite to the amplitude characteristics and has a linear phase characteristic and which can be sufficiently matched with the pre-emphasis circuit over a wide frequency range are comparatively provided. It can be realized with a simple configuration. In addition, these can be easily configured by a digital circuit, the accuracy and stability of signal processing can be improved, and the circuit can be easily integrated. Also, if this is applied to an FM transmission system, the amount of frequency deviation can be made large without widening the transmission band, and the means for waveform clipping to prevent overmodulation is unnecessary, and S / N without waveform distortion is required. Can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a basic circuit according to the present invention, FIG. 2 is a wiring diagram showing an embodiment of a first basic circuit constituting the basic circuit, and FIG. 3 is used in the present invention. FIG. 4 is a connection diagram showing a specific example of the impedance circuit Z and the admittance circuit Y, which are shown in FIG.
FIG. 5 is a block diagram showing an embodiment of a basic circuit, FIG. 5 is a block diagram showing an embodiment of a signal processing circuit configured by the basic circuit, and FIG. 6 is a characteristic diagram showing amplitude characteristics of the signal processing circuit.
FIG. 7 is a waveform diagram showing a response waveform of the signal processing circuit, and FIG.
FIG. 9 is a block diagram showing another embodiment of the signal processing circuit of the present invention, FIG. 9 is a connection diagram showing one embodiment of a raised cosine circuit constituting the signal processing circuit, and FIG. 10 is an amplitude of the signal processing circuit. FIG. 11 is a block diagram showing another embodiment of the signal processing circuit of the present invention, FIG. 12 is a connection diagram showing one embodiment of a square sine circuit forming the signal processing circuit, and FIG. FIG. 14 is a characteristic diagram showing the amplitude characteristic of the signal processing circuit, FIG. 14 is a block diagram showing another embodiment of the basic circuit according to the present invention, and FIG.
FIG. 17 is a connection diagram showing an embodiment of a third basic circuit forming the basic circuit, FIG. 16 is a block diagram showing an embodiment of a fourth basic circuit forming the basic circuit, and FIG. 18 is a block diagram showing an embodiment of a signal processing circuit composed of a circuit.
FIG. 19 is a characteristic diagram showing an amplitude characteristic of the signal processing circuit, FIG. 19 is a block diagram showing one embodiment of a digital processing type basic circuit according to the present invention, and FIG. 20 is a digital filter constituting the basic circuit. FIG. 21 is a block diagram showing an embodiment, and FIG. 21 is a block diagram showing another embodiment of the digital filter constituting the basic circuit. 100,100 '... Basic circuit 10 ... First basic circuit 20 ... Second basic circuit 10' ... Third basic circuit 20 '... Fourth basic circuit 30,40,50,30' ... Signal processing circuit 11 ...... Impedance circuit 12 …… Admittance circuit 200,300 …… Time axis conversion circuit 33,44,54,112,114,116 …… Coefficient unit 34,45,55,110,113,115 …… Adder 90,111 …… Delayer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-58-80107 (JP, A) JP-A-63-10917 (JP, A) Actual development Sho-60-98983 (JP, U) JP-B-61- 8632 (JP, B2) Japanese Patent Sho 60-53483 (JP, B2)

Claims (7)

[Claims] 1. A signal processing device for processing an input signal to convert it into a signal having a predetermined frequency characteristic, wherein ω is an angular frequency, T is a constant having a unit of time, and k is a constant. Alternatively, A basic circuit having a transfer function approximated by the following function; means for synthesizing a signal based on the input signal and a signal obtained by processing the input signal by the basic circuit at a predetermined ratio; A signal processing device characterized by the above. 2. The basic circuit comprises: Alternatively, A first basic circuit having a transfer function approximated by Alternatively, The signal processing device according to claim 1, wherein the signal processing device is configured by cascading a second basic circuit having a transfer function approximated by the following function. Wherein said first basic circuit, as a reference value of resistance _{R 0, tanh (bjωT) ×} R 0 consists impedance circuit is approximated by a function Z or,, tanh (jωT) / R 0 becomes a function 3. The signal processing device according to claim 2, wherein the admittance circuit Y approximated by [4] and a resistor R are configured by a four-terminal circuit network connected in series. 4. The second basic circuit sequentially writes an input signal to the first memory for each unit cycle, and for each unit cycle in a time series order opposite to the time series order of the writing. A means for sequentially reading from the first memory; a read output from the first memory is processed by a circuit having the same transfer function as the first basic circuit, and then sequentially written to the second memory for each unit cycle thereof; 3. A signal according to claim 2, further comprising: means for sequentially reading from the second memory for each unit cycle in a time series order opposite to the time series order of writing. Processing equipment. 5. The first basic circuit z-transforms its transfer function (z = exp (jωT ₀ )), sets T ₀ as a sampling period, m as a coefficient, and N = 2T / T ₀ , Alternatively, The signal processing apparatus according to claim 2, wherein the signal processing apparatus is configured by a digital filter having a transfer function approximated by the following function. 6. ω is an angular frequency, T is a constant having a unit of time, and k is a constant, Alternatively, Means for inputting a second signal obtained by synthesizing a signal obtained by processing the first signal by a basic circuit having a transfer function approximated by the following function and a signal based on the first signal at a predetermined ratio A signal processing circuit having an amplitude characteristic approximated by a function of 1 + K · cos ² (ωT) or 1 + K · sin ² (ωT), where K is a constant, and a substantially linear phase characteristic; A signal processing device configured to process a second signal from an input means by the signal processing circuit to restore a signal based on the first signal. 7. T ₁ and T ₂ are constants each having a unit of time (T ₁ > T ₂ ), ω is an angular frequency, and the amplitude characteristic is | H (j
ω) | and a second signal processing circuit having a transfer function approximated by a function of (1 + jωT ₁ ) / (1 + jωT ₂ ), which has a substantially linear phase characteristic. A signal processing device for converting a second signal, which is obtained by processing the first signal and amplitude-enhancing the high frequency band by the circuit, into a predetermined frequency characteristic, and means for inputting the second signal; A third signal processing circuit having a transfer function approximated by a function of 1 + jωT ₂ ) / (1 + jωT ₁ ); the amplitude characteristic is approximated by 1 / | H (jω) |, and the phase characteristic is substantially linear. A fourth signal processing circuit having: a means for processing the second signal from the input means by the third signal processing circuit and the fourth signal processing circuit to suppress the amplitude of the high frequency range. Recovering the signal based on the first signal by providing A signal processing device, which is configured to: