JPH0773368B2 - Time base collector - Google Patents

Description

The present invention relates to a time base collector that corrects the time axis of a video signal, and reproduces a video with a simple circuit configuration even at a high speed such as a special VTR. It is related to a time base collector.

[Prior art and its problems]

In a video tape recorder (VTR), the time base of the video output signal during high-speed playback operation fluctuates significantly compared to normal playback. Therefore, a method of correcting the time axis using a digital memory is used.The input video signal is sampled at a speed according to the fluctuation of the horizontal time axis of the input video signal, written in the memory, input processing is performed, and a constant speed is applied. Then, it is read and decoded to generate a normal video output signal. The operating frequency of the input processing unit also changes according to the frequency fluctuation of the input horizontal synchronizing signal. Operation must be guaranteed within the full range of frequency variation. When performing high-speed VTR playback, the horizontal sync signal frequency fluctuation is ±
Since the operating frequency range of the input processing unit is widened, the load on the input processing circuit increases.

〔Purpose〕

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a time base collector with a simple circuit configuration of an input processing unit which is not affected by frequency fluctuations of a horizontal synchronizing signal.

[Means for solving problems]

The present invention achieves the above-mentioned object by generating a reference clock by switching the input horizontal synchronizing signal and the vertical synchronizing signal so that the phase can be locked.

That is, according to the present invention, the input video signal is written in the memory by the input system reference clock generated by phase-locking with the synchronizing signal of the input video signal, and the written content is read by the stable output system reference clock to determine the time of the video signal. In the time base collector that performs axis correction, an oscillation circuit that generates the input system reference clock by phase locking to the input synchronization signal, and the synchronization signal that is input to this oscillation circuit is the horizontal or vertical synchronization signal of the input video signal. And a switch circuit for switching to
When the horizontal sync frequency of the input video signal is switched to the specified value, the horizontal sync signal is applied to the oscillator circuit when the horizontal sync frequency is lower than the specified value. Is characterized by switching so as to apply a vertical synchronizing signal to the oscillation circuit.

[Action]

When the frequency of the input horizontal synchronizing signal, which is normally phase-locked to obtain the operation reference clock, exceeds a certain threshold value, it is phase-locked to the vertical synchronizing signal to obtain the operation reference clock of the input processing unit. Since the frequency fluctuation of the vertical synchronizing signal is small, the change of the operating frequency can be suppressed small.

That is, at the time of high-speed playback of a VTR or the like, it has a reference clock generated by phase-locking the vertical synchronizing signal and an input processing unit that operates by obtaining horizontal synchronization from the horizontal synchronizing signal, and synchronizes with the reference synchronizing input signal. The time axis can be corrected by the output processing unit that performs the output processing according to the above.

In this case, the difference from the operation reference clock frequency obtained by synchronously coupling with the input horizontal synchronizing signal appears as image distortion, but the purpose of search by high-speed reproduction can be sufficiently achieved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

Note that the description is limited to only the part related to the processing of the luminance signal for convenience.

The sync separator 11 separates the sync signal from the input video signal,
The composite sync signal C _i and the vertical sync signal V _i are output. Frequency - voltage converter 12 generates a voltage V _H which is proportional to the horizontal sync frequency of the input video signal is input to the voltage comparator 13. The reference voltage V _S is applied to the other input of the voltage comparator 13,
The output drives the switch circuits 24, 25 and 26.

The phase comparator 21 constitutes a PLL together with the voltage-controlled oscillator 22, phase locks to the input video horizontal synchronizing signal, and generates an input system reference clock CK _W having an n-fold frequency. The synchronization signal generator 23 is a comparison synchronization signal C ₀ required by the phase comparator 21,
V ₀ is generated by clock CK _W.

Similarly, the output system control unit 31 operates by phase-locking to the reference TV sync signal for reading, which is externally applied, and operates as a horizontal sync signal n.
Generating a multiple of a stable output system reference clock CK _R.

AD converter 14, DA converter 32 each input system, the reference clock CK _W of the output system, is driven by CK _R, the sampling of the video, the decoding performed. The video memory buffer 27 can write and read asynchronously with different clocks.

Next, the operation will be described.

During normal playback, both switch circuits 24, 25, and 26 are set to 1.
The reference voltage V _S is set to be in the direction of. Therefore, the input processing unit operates in a phase-locked manner with the horizontal and vertical synchronizing signals of the input video, and the number of samples n in one horizontal period does not change even if expansion / compression occurs during the horizontal sync period of the input video. Since it is stably reproduced by the system clock, the time axis is corrected.

In high-speed playback, if there is compression of the horizontal sync period of the input video and the output V _{H of} the frequency-voltage converter 12 becomes larger than V _S ,
The output of the voltage comparator 13 changes so that both the switch circuits 24 and 25 switch in the direction of 2, and the input processing unit locks the phase with the vertical synchronizing signal of the input video signal. At this time, since the horizontal synchronizing signal generated by the synchronizing signal generator 23 is not synchronized with that of the input signal, the switch circuit 26 is also switched to the 2 direction. As a result, the memory 27 and the write horizontal address are directly reset by the input horizontal synchronizing signal, and the vertical address is advanced by one.

Therefore, the number of samples in the input video-horizontal synchronization period is smaller than n during normal reproduction by the amount of horizontal compression.
The output processing restores the signal as the video output waveform 41 shown in FIG. This is horizontally compressed with respect to the vertical synchronizing signal 42, and the reproduced image is also horizontally compressed.

With respect to the vertical direction, horizontal scanning line segments that are more than the specified number within one vertical period are ignored, so that the image is distorted in the vertical direction. These image distortions depend on the speed of high-speed reproduction and change when the speed is changed, but none of them impair the purpose of the search.

Regarding high-speed reproduction in the direction in which the horizontal synchronization period is extended (usually, forward direction), even if the circuit configuration is the same as during normal reproduction, the input processing operating frequency changes in the direction of lowering, so there is usually no problem.

The fluctuation of the vertical sync frequency during VTR high-speed playback is extremely small compared to the fluctuation of the horizontal sync signal. Therefore, if the threshold voltage V _S is set so that the clock frequency of the input processing circuit configured for normal reproduction operation does not exceed its limit, a special high-speed input processing circuit for high-speed reproduction processing is configured. There is no need, and the device can be realized with a simple circuit configuration.

In the above example, when the input horizontal synchronizing signal exceeds a certain threshold value, switching is performed so that the clock frequency of the input processing system is kept substantially constant, but in the case of search reproduction, it is uniquely switched. The circuit configuration may be changed.

〔effect〕

According to the present invention, it is possible to provide a time base collector having a simple circuit configuration, which is not affected by the frequency variation of the horizontal synchronizing signal at the time of VTR high speed reproduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an operation explanatory diagram thereof. 11 …… Synchronous separator 12 …… Frequency voltage converter 21 …… Phase comparator 22 …… Voltage controlled oscillator 24,25,26 …… Switch circuit

Claims (1)

[Claims] 1. A time axis of a video signal, wherein the input video signal is written in a memory by an input system reference clock generated by phase-locking with a synchronizing signal of the input video signal, and the written contents are read by a stable output system reference clock. In the time base collector for correction, the oscillation circuit that generates the input system reference clock by locking the phase with the input synchronization signal, and the synchronization signal input to the oscillation circuit to the horizontal synchronization signal or the vertical synchronization signal of the input video signal. And a switching circuit for switching, the switching circuit performs a switching operation at a predetermined value of the horizontal synchronizing frequency of the input video signal, and when the horizontal synchronizing frequency is lower than the predetermined value, the horizontal synchronizing signal is applied to the oscillation circuit. When the horizontal synchronizing frequency is equal to or higher than a predetermined value, the vertical synchronizing signal is switched so as to be applied to the oscillation circuit. Time base collector.