JPH077344B2 - Faulty processor identification method - Google Patents

Description

The present invention relates to a method of discriminating a failed processor in a multiprocessor system having a configuration in which a plurality of processors are connected to a common bus.

[Conventional technology]

In a multiprocessor system, when a failure occurs in any of the processors, the remaining processors generally interrupt the program and restore the failed processor at the program level. In this case, conventionally, when a failure occurs in one of the processors, the processor sends an interrupt signal to each of the other processors that are normally operating, and each of the normally operating processors receives the interrupt signal. It was identifying the failing processor. A technique related to this type of system is described in, for example, Japanese Patent Laid-Open No. 62-251866.

[Problems to be Solved by the Invention]

In the above conventional technology, one processor needs an interrupt signal for failure occurrence corresponding to each processor, and the number of interrupt signal lines increases as the number of processors increases. Therefore, each processor has one LSI with a limited number of interface signal lines. Alternatively, there is a problem that it becomes a pin neck in a system that is realized by a few processors and has a large number of processors.

An object of the present invention is to provide a multiprocessor system,
Provides a faulty processor identification method that minimizes the increase in the number of signal lines between processors and, if a fault occurs in one of the processors, all the remaining processors can grasp the faulty processor To do.

[Means for Solving the Problems]

In order to achieve the above object, the present invention provides a means for, in a multiprocessor system having a configuration in which a plurality of processors are connected to a common bus, taking a logical sum of failure occurrence report signals of the processors and transmitting the logical sum to all the processors. In addition, when a failure occurs in any processor, each of the remaining normal processors, to which the failure report signal from the failed processor is transmitted, sends a bus securing request to the bus arbiter, and one normal operation is permitted by the bus arbiter. That is, the processor acquires the right to use the common bus and executes the process of determining the fault source processor using the common bus. Further, the processor, when discriminating the fault source processor, transmits the fault source processor identification information to the remaining processors using the common bus.

[Action]

By transmitting the OR signal of the fault occurrence report signals of each processor to all the processors, when a fault occurs in one processor, the remaining processors can recognize that a fault has occurred in any of the processors in the system. One of the remaining processors acquires the right to use the bus under the control of the bus arbiter, determines the fault source processor using the common bus, and further uses the determined fault source processor identification information for the common bus. To all processors. As a result, the increase in the number of signal lines between the processors can be suppressed to the minimum, and all the normally operating processors can accurately grasp the failure source processor.

Further, the processor that performs the process of discriminating the fault source processor can dynamically select from among the normal processors under the control of the bus arbiter by using the original procedure of bus acquisition.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, a plurality of processors 1 to n are connected to a common bus 300 which enables arbitrary communication among the processors. The bus arbiter 200 controls the bus use right of each of the processors 1 to n.
n4, bus use permission signals 15 to n5, bus use end signals 16 to n6
Are individually connected by signal lines for transmitting and receiving. Each of the processors 1 to n is provided with a fault detection unit 11 to n1, a common bus control unit 12 to n2, and a processor fault interrupt register 13 to n3 as a configuration related to the present invention. Further, the logic gate 100 is provided according to the present invention. The fault occurrence report signals 10 to n0 are input from each of the processors 1 to n to obtain a logical sum, and the logical sum output signal 101 is common to the processors 1 to n. To be sent to. The operation of FIG. 1 will be described below by taking the case where a failure occurs in the processor 1 as an example.

When the fault detection unit 11 of the processor 1 detects a fault, the fault occurrence report signal 10 is transmitted, and the OR gate 100
An OR output 101 is provided to each processor. As a result, the normally operating processors 2 to n know that any one of the processors in the system has failed.

FIG. 2 shows a processing flowchart of each of the processors 2 to n operating normally after receiving the logical sum output signal 101.

Upon receiving the logical sum output signal 101, the processors 2 to n operating normally use the common bus 300 to determine the fault source processor.
Bus securing request signals 24 to n4 are sent from n2 to the bus arbiter 200 (step 501), and bus use permission signals 25 to n5 from the bus arbiter 200 are waited (step 502). When the bus arbiter 200 receives the bus reservation request signals 24 to n4, it selects one of the processors 2 to n and sends a bus use permission signal to the selected processor. Here, it is assumed that the bus arbiter 200 selects the processor 2 and sends the bus use permission signal 25 to the processor 2. Processor 2
When the bus use permission signal 25 is received, the common bus 300 is used to start the fault source processor determination process (step 503).

FIG. 3 shows a time chart of each signal when the processor 2 uses the common bus 300 to determine the fault source processor and transmits it to the remaining processors.

The processor 2, which has received the bus use permission signal 25, determines the processor from which the failure has occurred in order to specify the destination processor number from the common bus control unit 22 through the common bus 300, in order, to identify the common processor 1 to n. A fault display data request command is issued to the bus control units 12 to n2 to fetch the fault display data. That is, first, the common bus control unit 22 of the processors 1 to n2 uses the processor 1 as the destination processor number.
To output the fault display data request command 2-a to the command / data bus. When the bus direction is "1", the processor 2 is the sending side, and when it is "0", the receiving side is the receiving side. When the command / data identification is “1”, it means that data is transmitted, and when the command / data identification is “0”, it means that a command is transmitted. When the common bus control unit 22 of the processor 2 sends all the signals, it sends a trigger and then sets the bus direction to "0". The common bus control unit 12 of the processor 1 fetches the fault occurrence report signal 10 output from the fault detection unit 11,
The fault display data 1-a is sent to the command / data bus. The common bus control unit 22 of the processor 2 takes in the fault display data 1-a. Next, in the same manner, the common bus control unit 22 of the processor 2 designates the processor 3 and issues a fault display data request command 2-a to the command / data bus.
To receive the fault display data 3-a from the common control unit 32 of the processor 3. This is repeated, and finally the common bus control unit 22 of the processor 2 receives the fault display data n-a from the processor n. In this way, the processor 2 consequently recognizes that the processor 1 is in failure. Although the processor 1 has a failure, the common bus control unit 12 enables the sending operation of the failure display data 1-a without being affected by this failure.

When the processor 2 determines the fault source processor 1, the processor 2 transmits the number of the fault source processor 1 to all the processors using the common bus 300. (Step 504). That is, the common bus control unit 22 of the processor 2 specifies the number indicating all the processors as the destination processor number, and the faulty processor transmission command 2-b on the command / data bus.
And the fault source processor number (here, the number of the processor 1) are transmitted. As a result, the common bus control units 12 to n2 of the processors 1 to n set the bit corresponding to the processor 1 in the processor fault interrupt registers 13 to n3 to "1".

Subsequently, the processor 2 resets the fault occurrence report signal 10 of the fault origin processor 1 using the common bus 300 (step 505). That is, the common bus control unit 22 of the processor 2 designates the processor 1 as the destination processor number and sends the fault occurrence report signal reset command 2-d to the command / data bus. As a result, the common bus control unit 12 of the processor 1 sends a reset instruction for the fault occurrence report signal 10 to the fault detection unit 11, and the fault detection unit 11 performs the reset operation. After that, the common bus control unit 22 of the processor 2
Sends a bus use end signal 26 to the bus arbiter 200 (step 506) and shifts to interrupt processing in order to deal with the failure of the processor 1.

On the other hand, the processors 3 to n which cannot acquire the right to use the common bus 300 test whether the output signal (fault occurrence report signal) 101 of the OR gate 101 is continuously transmitted (step 5).
07), if it has been sent, continue to wait for the bus use permission signals 35 to n5 from the bus arbiter 200 (step 502). After that, when the fault occurrence report signal 10 of the processor 1 is reset and the output signal 101 of the logical sum gate 100 falls, the processors 3 to n are not connected to the common bus 300 by the other processors.
The bus reservation request signals 34 to n4 are dropped upon recognizing that the process of discriminating the fault source processor and the process of transmitting the processor number to all the processors have been completed by acquiring the use right of the bus reservation request signals (step 508). Then, each of the processors 3 to n also shifts to the interrupt processing to cope with the failure of the processor 1.

In FIG. 1, the OR gate 100 may be realized as a wired OR of the failure occurrence report signals 10 to n0, and the bus arbiter 200 may be included in any of the processors 1 to n.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, in the multiprocessor system, all the processors receive the logical sum of the failure occurrence report signals of the respective processors, and which processor has a failure depends on which processor. Uses the common bus to determine the result and transmits the result to all the processors using the common bus, so that the number of interface signals required for determining the fault source processor in each processor can be minimized.

Also, the processor that performs the determination processing of the faulty processor can dynamically select from among the normal processors by using the original procedure of bus acquisition under the control of the bus arbiter, and the processor that performs the determination processing can be selected in advance. There is no need to specify a procedure or a procedure assuming a case where the processor designated in advance fails.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which the present invention is applied, and FIG. 2 is a method for discriminating the remaining normally operating processors when a failure occurs in any of the processors in the system. FIG. 3 is a flowchart showing the processing, and FIG. 3 is a time chart in the case where the normal processor uses the common bus to determine the fault source processor and transmits the determination result to the remaining processors. 1-n ... Processor, 10-n0 ... Fault occurrence report signal,
11 to n1 …… Fault detection unit, 12 to n2 …… Common bus control unit, 13
~ N3 ...... Processor failure interrupt register, 14 to n4 ...... Bus reservation request signal, 15 to n5 ...... Bus use enable signal, 16 to n6
...... Bus end signal, 100 …… OR gate, 101 ……
OR gate output signal, 200 …… bus arbiter, 300 ……
Common bus.

Claims (2)

[Claims] 1. A method for determining a faulty processor in a multiprocessor in which a plurality of processors are connected to a common bus and a bus arbiter for controlling the right to use the common bus is connected to each processor by an individual signal line. A means for providing a logical sum of the failure occurrence report signals of the respective processors and transmitting the logical sum to all the processors is provided, and the failure occurrence report signals from the faulty processors are simultaneously transmitted to each of the remaining normal processors. Each of the normal processors to which the report signal is transmitted sends a bus reservation request signal to the bus arbiter via the individual signal line, and when the bus arbiter receives the bus reservation request signal from each normal processor, one normal processor Select a processor and send a bus use permission signal to the normal processor through the individual signal line. , Normal processor receiving the bus grant signal,
A faulty processor discriminating method, characterized in that a fault source processor discriminating process is executed by using the common bus. 2. A normal processor that has received the bus use permission signal transmits the failure source processor identification information to the remaining normal processors using the common bus after the fault origin processor determination processing. The method for determining a faulty processor according to claim 1, wherein